256M32 JE -14 : A. 8Gb: 2 Channels x16/x8 GDDR6 SGRAM Features. FBGA Part Marking Decoder. Advance. Figure 1: Part Numbering

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1 GDD6 SGAM 8Gb: 2 Channels x16/x8 GDD6 SGAM eatures MT61K256M32 2 Channels x 256 Meg x 16 I/O, 2 Channels x 512 Meg x 8 I/O eatures DD = DDQ = 1.35 ±3% PP = 1.8 3%/+6% Data rate: 12 Gb/s, 13 Gb/s, 14 Gb/s 2 separate independent channels (x16) x16/x8 and 2-channel/pseudo channel (PC) mode configurations set at reset Single ended interfaces per channel for command/ address (CA) and data Differential clock input CK_t/CK_c for CA per 2 channels One differential clock input WCK_t/WCK_c per channel for data (DQ, DBI_n, EDC) Double data rate (DD) command/address (CK) Quad data rate (QD) and double data rate (DD) data (WCK), depending on operating frequency 16n prefetch architecture with 256 bits per array read or write access 16 internal banks 4 bank groups for t CCD = 3 t CK and 4 t CK Programmable EAD latency: 9 to 20 Programmable WITE latency: 5 to 7 Write data mask function via CA bus with single and double byte mask granularity Data bus inversion (DBI) and CA bus inversion (CABI) Input/output P CA bus training: CA input monitoring via DQ/ DBI_n/EDC signals WCK2CK clock training with phase information via EDC signals Data read and write training via read IO (depth = 6) ead/write data transmission integrity secured by cyclic redundancy check using half data rate CC Programmable CC EAD latency = 2 to 3 Programmable CC WITE latency = 10 to 14 Programmable EDC hold pattern for CD DQS mode on EDC pins ow power modes On chip temperature sensor with read out Auto precharge option for each burst access Auto refresh mode (32ms, 16k cycles) with per-bank and per-2-bank refresh options Temperature sensor controlled self refresh rate Digital t AS lockout On die termination (ODT) for all high speed inputs Pseudo open drain (POD 135) compatible outputs ODT and output driver strength auto calibration with external resistor ZQ pin (120Ω) Internal E with DE for data inputs, with input receiver characteristics programmable per pin Selectable external or internal E for CA inputs; programmable E offsets for internal E endor ID for device identification IEEE compliant boundary scan 180-ball BGA package ead-free (os-compliant) and halogen-free packaging T C = 0 C to +95 C Options 1 Marking Organization 256 Meg 32 (words bits) 256M32 BGA package 180-ball (12.0mm 14.0mm) JE Timing maximum data rate 12 Gb/s Gb/s Gb/s -14 Operating temperature Commercial (0 C T C +95 C) None evision A Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 1 Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.

2 8Gb: 2 Channels x16/x8 GDD6 SGAM eatures igure 1: Part Numbering Micron Memory Product amily 61 = GDD6 SGAM Operating oltage K = 1.35 MT Configuration 256M32 = 256 Meg x K Package JE = 180-ball BGA, 12.0mm x 14.0mm 256M32 JE -14 : A evision A Temperature : = Commercial Data ate -12 = 12 Gb/s -13 = 13 Gb/s -14 = 14 Gb/s BGA Part Marking Decoder Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. or a quick conversion of an BGA code, see the BGA Part Marking Decoder on Micron s web site: gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 2

3 8Gb: 2 Channels x16/x8 GDD6 SGAM Operating requency anges Operating requency anges igure 2: Operating requency anges MT61K256M32JE-12 GDD6 ow Speed GDD6 igh Speed DQS Mode [Gb/s/pin] MT61K256M32JE-13 GDD6 ow Speed GDD6 igh Speed DQS Mode MT61K256M32JE [Gb/s/pin] GDD6 ow Speed GDD6 igh Speed DQS Mode [Gb/s/pin] Table 1: Operating requency anges Operating Mode Symbol Min Max Min Max Min Max Unit GDD6 igh Speed f CK Mz f WCK GDD6 ow Speed f CK f WCK DQS Mode f CK f WCK Note: 1. This Micron GDD6 SGAM is available in different speed bins. The operating range and AC timings of a faster speed bin are a superset of all slower speed bins. Therefore it is safe to use a faster bin device as a drop-in replacement of a slower bin device when operated within the supply voltage and frequency range of the slower bin device. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 3

4 8Gb: 2 Channels x16/x8 GDD6 SGAM Ball Assignments and Descriptions Ball Assignments and Descriptions igure 3: 180-Ball BGA (Top iew) A DD SS DQ1_A SS PP PP SS DQ9_A SS DD A B SS DQ3_A DQ2_A DQ0_A DDQ DDQ DQ8_A DQ10_A DQ11_A SS B C DDQ EDC0_A SS DDQ SS SS DDQ SS EDC1_A DDQ C D SS DBI0_n_A SS WCK_t _A WCK_c _A NC NC SS DBI1_n_A SS D E DDQ DQ5_A DQ4_A SS DD DD SS DQ12_A DQ13_A DDQ E SS DQ6_A SS DDQ TMS TDI DDQ SS DQ14_A SS G SS DQ7_A SS CA2_A NC CKE_n_A CA1_A SS DQ15_A SS G DDQ DD CA0_A SS CA4_A CA5_A SS CA3_A DD DDQ J ESET _n DDQ CA9_A CA8_A CABI_n_A CK_t CA7_A CA6_A DDQ ZQ_A J K EC DDQ CA9_B CA8_B CABI_n_B CK_c CA7_B CA6_B DDQ ZQ_B K DDQ DD CA0_B SS CA4_B CA5_B SS CA3_B DD DDQ M SS DQ7_B SS CA2_B NC CKE_n_B CA1_B SS DQ15_B SS M N SS DQ6_B SS DDQ TCK TDO DDQ SS DQ14_B SS N P DDQ DQ5_B DQ4_B SS DD DD SS DQ12_B DQ13_B DDQ P SS DBI0_n_B SS NC NC WCK_c _B WCK_t _B SS DBI1_n_B SS T DDQ EDC0_B SS DDQ SS SS DDQ SS EDC1_B DDQ T U SS DQ3_B DQ2_B DQ0_B DDQ DDQ DQ8_B DQ10_B DQ11_B SS U DD SS DQ1_B SS PP PP SS DQ9_B SS DD Data Command/ Address Other signal Supply Ground Note: 1. Channel A byte 1 and channel B byte 0 are disabled when the device is configured to x8 mode. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 4

5 8Gb: 2 Channels x16/x8 GDD6 SGAM Ball Assignments and Descriptions Table 2: 180-Ball BGA Ball Descriptions Symbol Type Description CK_t, CK_c WCK_t, WCK_c Input Input Clock: CK_t and CK_c are differential clock inputs. CK_t and CK_c do not have channel indicators as one clock is shared between both channel A and channel B on a device. Command address (CA) inputs are latched on the rising and falling edge of CK. All latencies are referenced to CK. Write clock: WCK_t and WCK_c are differential clocks used for write data capture and read data output. WCK_t/WCK_c are associated with DQ[15:0], DBI[1:0]_n, and EDC[1:0]. CKE_n Input Clock enable: CKE_n OW activates and CKE_n IG deactivates the internal clock, device input buffers, and output drivers excluding ESET_n, TDI, TDO, TMS, and TCK. Taking CKE_n IG provides PECAGE POWE-DOWN and SE EES operations (all banks idle), or ACTIE POWE-DOWN (row ACTIE in any bank). CKE_n must be maintained OW throughout read and write accesses. CA[9:0] Input Command address (CA): The CA inputs receive packetized DD command, address or other information, for example, the op-code for the MS command. See Command Truth Table for details. CABI_n Input Command address bus inversion DQ[15:0] I/O Data input/output: Bidirectional 16-bit data bus. DBI[1:0]_n I/O Data bus inversion: DBI0_n is associated with DQ[7:0], DBI1_n is associated with DQ[15:8]. EDC[1:0] Output Error detection code: The calculated CC data is transmitted on these signals. In addition these signals drive a "hold" pattern when idle. EDC0 is associated with DQ[7:0], EDC1 is associated with DQ[15:8]. DDQ Supply I/O power supply: Isolated on the die for improved noise immunity. DD Supply Power supply SS Supply Ground PP Supply Pump voltage EC Supply eference voltage for CA, CABI_n, and CKE_n signals ZQ eference External reference for auto calibration TDI Input JTAG test data input TDO Output JTAG test data output TMS Input JTAG test mode select TCK Input JTAG test clock ESET_n Input eset: ESET_n low asynchronously initiates a full chip reset. With ESET_n OW all ODTs are disabled. A full chip reset may be performed at any time by pulling E- SET_n OW. NC No connect Note: 1. Index "_A" or "_B" represents the channel indicator "A" and "B" of the device. Signal names including the channel indicator are used whenever more than one channel is referenced, for example, with the ball assignment. The channel indicator is omitted whenever features and functions common to both channels are described. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 5

6 8Gb: 2 Channels x16/x8 GDD6 SGAM Package Dimensions Package Dimensions igure 4: 180-Ball BGA (JE) 0.12 Seating plane 0.6 CT nonconductive overmold A 0.1 A 180X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads Ball A1 ID (covered by S) Ball A1 ID 14 ± CT 0.75 TYP A B C D E G J K M N P T U 0.75 TYP 1.1 ± CT 0.34 ± ±0.1 Notes: 1. Package dimension specification is compliant to JC11 MO328 variation P14.0x12.0- GJ-180A. 2. All dimensions are in millimeters. 3. Solder ball material: SAC-Q (92.5% Sn, 4% Ag, 3% Bi, 0.5% Cu). gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 6

7 unctional Description 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description The GDD6 SGAM is a high-speed dynamic random-access memory designed for applications requiring high bandwidth. It is internally configured as 16 bank memory and contains 8,589,934,592 bits. The GDD6 SGAM s high-speed interface is optimized for point-to-point connections to a host controller. On-die termination (ODT) is provided for all high-speed interface signals to eliminate the need for termination resistors in the system. GDD6 uses a 16n-prefetch architecture and a DD or QD interface to achieve highspeed operation. The device s architecture consists of two 16-bit-wide fully independent channels. ead and write accesses to GDD6 are burst oriented; accesses start at a selected location and consist of a total of 16 data words. Accesses begin with the registration of an ACTIATE command, which is then followed by a EAD, WITE (WOM), or masked WITE (WDM, WSM) command. The row and bank address to be accessed is registered coincident with the ACTIATE command. The address bits registered coincident with the EAD, WITE, or masked WITE command are used to select the bank and the starting column location for the burst access. Clocking GDD6 operates from a differential clock CK_t and CK_c. CK is common to both channels. Command and address (CA) are registered at every rising and falling CK edge. There are both single-cycle and multi-cycle commands. See Command Truth Table for details. GDD6 uses a free running differential forwarded clock (WCK_t/WCK_c) with both input and output data registered and driven respectively at both edges of the forwarded WCK. GDD6 supports DD and QD operating modes for WCK frequency which differ in the DQ/DBI_n pin to WCK clock frequency ratio. The figure below illustrates the difference between both modes. This GDD6 SGAM device is designed with a WCK/word granularity which is equivalent to one WCK per channel. The DAM info bits for WCK granularity, WCK frequency, and internal WCK can be read by the host during the initialization process to determine the WCK architecture for the device. Table 3: Example Clock and Interface Signal requency elationship Pin DD WCK QD WCK Unit CK_t, CK_c Gz CA Gb/s/pin WCK_t, WCK_c Gz DQ, DBI_n Gb/s/pin EDC Gb/s/pin gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 7

8 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description igure 5: Clocking and Interface elationship CK_c CK_t CA QD WCK DD WCK DQ, DBI_n EDC f (for example, 1.5 Gz) 2f (for example, 3 Gb/s) 2f (for example, 3 Gz) 4f (for example, 6 Gz) 8f (for example, 12 Gb/s) 4f (for example, 6 Gb/s) Note: 1. The figure shows the relationship between the data rate of the buses and the clocks; it is not a timing diagram. igure 6: Block Diagram of an Example Clock System Controller GDD6 SGAM ADD/CMD centered with CK_t/CK_c CMD/ADD D Q CA (3 Gb/s) CK_t, CK_c (1.5 Gz) ADD/CMD sampled by CK_t/CK_c as DD D Q to internal state machine WCK2CK Alignment D Q to EDC pin Osc. P Data Tx/x WCK_t, WCK_c (3 Gz or 6 Gz) /2 /4 P Internal WCK 3.0 Gz EAD data Q D Q D WITE data clock phase ctrl early/ late D Q DATA (12 Gb/s) D Q DAM Core clock phase ctrl gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 8

9 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description Addressing GDD6 addressing is defined for a single channel with devices having two channels per device. Table 4: Addressing 8Gb Density Parameter x16 Mode x8 Mode Number of channels 2 Memory density (per channel) 4Gb Memory prefetch (per channel) 256b 128b Bank address (per channel) BA[3:0] ow address (per channel) [13:0] Column address (per channel) C[5:0] C[6:0] Page size (per channel) 2KB efresh 16k/32ms Notes: 1. The column address notation for GDD6 does not include the lower four address bits as the burst order is always fixed for EAD and WITE. 2. Page size = 2^COBITS (Prefetch_Size/8) where COBITS is the number of column address bits. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 9

10 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description Operations Command Truth Table GDD6 uses a packetized DD command/address bus that encodes all commands and addresses on a 10-bit CA bus as outlined in the table below. igure 7: Command Truth Table Operation Symbol CK Edge n - 1 CKE_n n CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Notes NO OPEATION NOP (1) 1, 10 NOP (2) NOP (3) MODE EGISTE SET MS M3 M2 M1 M0 OP3 OP2 OP1 OP0 1, 2, 3 ACTIATE ACT OP11 OP10 OP9 OP8 OP7 3 OP6 2 OP5 1 OP4 0 1, 2, EAD D C3 CE C2 C6 C1 C5 C0 C4 1, 2, 5, 6 EAD with AUTO PECAGE DA C3 CE C2 C6 C1 C5 C0 C4 1, 2, 5, 6 OAD IO D B3 B2 B1 B0 D3 D2 D1 D0 1, 2, 8 EAD TAINING DT D9 D8 D7 D6 D5 D4 1, 2, 6 CE WITE WOM C3 CE C2 C6 C1 C5 C0 C4 1, 2, 5, 6 WITE with AUTO PECAGE WITE SINGE BYTE MASK WOMA WSM C3 CE C3 CE C2 C6 C2 C6 C1 C5 C1 C5 C0 C4 C0 C4 1, 2, 5, 6 1, 2, 5, 6 BST7 BST6 BST5 BST4 BST3 BST2 BST1 BST0 BST15 BST14 BST13 BST12 BST11 BST10 BST9 BST8 BST7 BST6 BST5 BST4 BST3 BST2 BST1 BST0 BST15 BST14 BST13 BST12 BST11 BST10 BST9 BST8 gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 10

11 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description igure 8: Command Truth Table (Continued) Operation Symbol CK Edge n - 1 CKE_n n CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Notes WITE SINGE BYTE MASK with AUTO PECAGE WSMA BST7 BST6 BST5 BST4 C3 CE BST3 C2 C6 BST2 C1 C5 BST1 C0 C4 BST0 1, 2, 5, 6 BST15 BST14 BST13 BST12 BST11 BST10 BST9 BST8 BST7 BST6 BST5 BST4 BST3 BST2 BST1 BST0 BST15 BST14 BST13 BST12 BST11 BST10 BST9 BST8 WITE DOUBE BYTE MASK WDM BST7 BST6 BST5 BST4 C3 CE BST3 C2 C6 BST2 C1 C5 BST1 C0 C4 BST0 1, 2, 5, 6 BST15 BST14 BST13 BST12 BST11 BST10 BST9 BST8 WITE DOUBE BYTE MASK with AUTO PECAGE WDMA BST7 BST6 BST5 BST4 C3 CE BST3 C2 C6 BST2 C1 C5 BST1 C0 C4 BST0 1, 2, 5, 6 WITE TAINING WT BST15 BST14 BST13 BST12 BST11 BST10 BST9 BST8 1, 2, 6 CE PECAGE PEpb 1, 2, 9 PECAGE A PEab 1, 2 PE-BANK EES Epb/ Ep2b 1, 2, 7, 9 EES Eab 1, 2, 7 POWE-DOWN ENTY POWE-DOWN EXIT PDE PDX 1, 2 1, 2 SE EES ENTY SE 1, 2, 7 SE EES EXIT SX 1, 2 COMMAND/ADDESS TAINING CAPTUE CAT 1, 2 Notes: 1. = ogic IG level; = ogic OW level; = alid signal ( or, but not floating)., = ising, alling CK clock edge. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 11

12 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description Clamshell (x8) Mode Enable 2. alues shown for CA[9:0] are logical values; the physical values are inverted when command/address bus inversion (CABI) is enabled and CABI_n =. 3. M[3:0] provide the mode register address (MA), OP[11:0] the opcode to be loaded. 4. BA[3:0] provide the bank address, [13:0] provide the row address. 5. B[3:0] provide the bank address, C[6:0] provide the column address; no sub-word addressing within a burst of 16. BST[15:0] provide the write data mask for each burst position with WDM(A) and WSM(A) commands. 6. CE (channel enable) is intended for PC mode. The command is active when CE =. When CE = the data access is suppressed. 7. The command is EES or PE-BANK EES/PE-2-BANK EES when CKE_n(n) = and SE EES ENTY when CKE_n(n) =. 8. B[3:0] select the burst position, and D[9:0] provide the data. 9. BA[3:0] provide the bank address. 10. CA8 must be IG on either the rising or falling (or both) CK clock edges. A GDD6 SGAM-based memory system is typically divided into several channels. GDD6 has been optimized for a 16-bit-wide channel. A channel can be comprised of a single device operated in x16 mode, or two devices each operated in x8 mode. or x8 mode the devices are typically assembled on opposite sides of the PCB in what is referred as a clamshell layout. Whether in x16 mode or x8 mode the device will operate with a point-to-point connection on the high-speed data signals. The disabled signals in x8 mode should all be in a igh-z state, non-terminating. The x8 mode is detected at power-up on EDC1_A and EDC0_B. or x8 mode these signals are tied to SS ; they are part of the bytes that are disabled in this mode and therefore not needed for EDC functionality. or x16 mode these signals are active and always terminated to DDQ in the system or by the controller. The configuration is set with ESET_n going IG. Once the configuration has been set, it cannot be changed during normal operation. Typically, the configuration is fixed in the system. Details of the x8 mode detection are depicted in igure 9. A comparison of x16 mode and x8 mode systems is shown in igure 10. Table 5: Clamshell (x8) Mode Enable Mode EDC0_A EDC1_A EDC0_B EDC1_B x8 DDQ SS (on board) SS (on board) DDQ x16 DDQ (terminated by the system or controller) gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 12

13 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description igure 9: Enabling Clamshell (x8) Mode Controller Enable Termination DDQ EDC data from other DAM GDD6 in x8 mode non-mirrored X EDC1_A EDC0_B EDC x8 EDC1_A EDC0_B TX EN EDC Data SS X D 0 = x8 ESET_n ESET_n ESET_n Controller Enable Termination DDQ EDC data from other DAM GDD6 in x8 mode mirrored X EDC0_A EDC1_B EDC x8 EDC1_A EDC0_B TX EN EDC Data SS X D 0 = x8 ESET_n ESET_n ESET_n Controller Enable Termination DDQ GDD6 in x16 mode X EDC1_A EDC0_B EDC x16 EDC1_A EDC0_B TX EN EDC Data SS X D 1 = x16 ESET_n ESET_n ESET_n gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 13

14 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description igure 10: System iew for x16 and x8 Modes ost GDD6 x16 ost GDD6 x8 GDD6 x8 Channel X DQ[7:0]_X, DBI[1:0]_n_X EDC0_X WCK_t_X, WCK_c_X DQ[15:8]_X, DBI[3:2]_n_X EDC1_X CA[9:0]_X, CABI_n_X CKE_n_X _A EDC0_A WCK_A _A EDC1_A ADD/ CMD (Ch A) Channel X DQ[7:0]_X, DBI[1:0]_n_X EDC0_X WCK0_t_X, WCK0_c_X WCK1_t_X, WCK1_c_X DQ[15:8]_X, DBI[3:2]_n_X EDC1_X CA[9:0]_X, CABI_n_X CKE_n_X _A EDC0_A EDC0_B WCK_A WCK_B _B EDC1_B EDC1_A ADD/ ADD/ CMD CMD (Ch A) (Ch B) Channel Y DQ[15:8]_Y, DBI[3:2]_n_Y EDC1_Y WCK_t_Y, WCK_c_Y DQ[7:0]_Y, DBI[1:0]_n_Y EDC0_Y CA[9:0]_Y, CABI_n_Y CKE_n_Y _B EDC1_B WCK_B _B EDC0_B ADD/ CMD (Ch B) Channel Y DQ[15:8]_Y, DBI[3:2]_n_Y EDC1_Y WCK1_t_Y, WCK1_c_Y WCK0_t_Y, WCK0_c_Y DQ[7:0]_Y, DBI[1:0]_n_Y EDC0_Y CA[9:0]_Y, CABI_n_Y CKE_n_Y _B EDC1_B EDC1_A WCK_B WCK_A _A EDC0_A EDC0_B ADD/ ADD/ CMD CMD (Ch B) (Ch A) CK_t, CK_c ESET_n CK_t, CK_c ESET_n igure 11 clarifies the use of x8 mode and how the bytes are enabled/disabled to give the controller the view of the same bytes that a controller sees with a single x16 device. or a 16-bit channel using two devices in a clamshell design, byte 0 comes from channel A from the top device and byte 1 comes from channel B from the bottom device and will look equivalent at the controller to a x16 mode. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 14

15 8Gb: 2 Channels x16/x8 GDD6 SGAM unctional Description igure 11: Byte Orientation in Clamshell Topology Ch A Byte 0 Ch B Byte 1 Ch A Byte 0 Ch B Byte 1 + = Ch A Byte 0 Ch B Byte 0 Ch A Byte 1 Ch B Byte 1 x8 x8 top egend: Data ADD/CMD CK, WCK x8 x8 bottom Pseudo-Channel Mode GDD6 has been optimized for a 32B access across a 16-bit channel by providing a unique CA bus to each 16-bit-wide channel. or applications requiring fewer CA pins, GDD6 includes support for a pseudo-channel (PC) mode where CA[9:4], CKE_n, and CABI_n on each channel are connected to a common bus, while CA[3:0] of each channel are connected to a separate bus. The command truth table is organized such that in PC mode the same command is decoded in both pseudo-channels, but EAD and WITE commands support a unique column address to each pseudo-channel. In PC mode, CKE_n and CABI_n are also shared across pseudo-channels. In PC mode, the only difference in the DAM is that termination on CA[9:4], CKE_n, and CABI_n can be configured differently from CA[3:0]. PC mode can be selected during initialization by driving CA6 = OW on both channels when ESET_n is driven IG. igure 12: CA Pins in Pseudo-Channel Mode Pseudo-Channel Mode Controller CA[3:0]_A CA[9:4], CABI_n, CKE_n CA[3:0]_B GDD6 CA[3:0]_A CA[9:4]_A, CABI_n_A, CKE_n_A CA[9:4]_B, CABI_n_B, CKE_n_B CA[3:0]_B gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 15

16 8Gb: 2 Channels x16/x8 GDD6 SGAM Operating Conditions Operating Conditions Absolute Maximum atings Table 6: Absolute Maximum atings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Unit Notes DD oltage on DD pin relative to SS DDQ oltage on DDQ pin relative to SS PP oltage on PP pin relative to SS IN / OUT oltage on any pins relative to SS T STG Storage temperature C Notes: 1. DD and DDQ must be within 300m of each other at all times the device is poweredup. 2. PP must be equal or greater than DD and DDQ at all times the device is powered up. DC and AC Operating Conditions Table 7: DC Operating Conditions The interface of GDD6 with 1.35 DDQ will follow the POD135 Standard (JESD8-21), Class D. All AC and DC values are referenced to the ball. Symbol Parameter Min Typ Max Unit Notes DD Device supply voltage DDQ Output supply voltage PP Pump voltage ED eference voltage for DQ and DBI_n 0.69 DDQ 0.71 DDQ 3, 4 ED DDQ 0.51 DDQ 3, 4, 5 EC eference voltage for CA 0.69 DDQ 0.71 DDQ 3, 6 EC DDQ 0.51 DDQ 3, 6, 7 IA(DC) DC input logic IG voltage with EC for CA EC IA(DC) DC input logic OW voltage with EC for CA EC IA2(DC) DC input logic IG voltage with EC2 for CA EC IA2(DC) DC input logic OW voltage with EC2 for CA EC ID(DC) ID(DC) DC input logic IG voltage with ED for DQ and DBI_n DC input logic OW voltage with ED for DQ and DBI_n ED ED 0.09 gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 16

17 8Gb: 2 Channels x16/x8 GDD6 SGAM Operating Conditions Table 7: DC Operating Conditions (Continued) Symbol Parameter Min Typ Max Unit Notes ID2(DC) ID2(DC) I I IN DC input logic IG voltage with ED2 for DQ and DBI_n DC input logic OW voltage with ED2 for DQ and DBI_n ESET_n and boundary scan input logic IG voltage; EDC and CA input logic IG voltage for x16/x8 mode, PC vs. 2-channel mode, CK and CA ODT select at reset ESET_n and boundary scan input logic OW voltage; EDC and CA input logic OW voltage for x16/x8 mode, PC vs. 2-channel mode, CK and CA ODT select at reset Single ended clock input voltage level: CK_t, CK_c, WCK_t, WCK_c ED ED DDQ DDQ DDQ MP(DC) CK_t, CK_c clock input midpoint voltage EC EC , 13 IDCK(DC) CK_t, CK_c clock input differential voltage , 13 IDWCK(DC) WCK_t, WCK_c clock input differential voltage , 14 I I OZ Input leakage current (any input 0 IN DDQ ; all other signals not under test = 0) Output leakage current (outputs are disabled; 0 OUT DDQ ) 5 5 µa 5 5 µa O(DC) Output logic low voltage 0.56 ZQ External resistor value Ω Notes: 1. GDD6 SGAM devices are designed to tolerate PCB designs with separate DD and DDQ power regulators. 2. DC bandwidth is limited to 20 Mz. 3. AC noise in the system is estimated at 50m peak-to-peak for the purpose of DAM design. 4. The reference voltage source and control for DQ and DBI_n pins are determined by half ED, and ED level mode register bits. 5. Programmable ED levels are not supported with ED2. 6. The reference voltage source (external or internal) is determined at power up; the reference voltage level is determined by half EC and the EC offset mode register bit. 7. Programmable EC offsets are not supported with EC2. 8. I and I apply to boundary scan input pins TDI, TMS, and TCK. I and I apply to EDC and CA inputs at reset when latching default device configurations. I and I also apply to CA, CABI_n, CKE_n, CK, DQ, DBI_n, EDC, and WCK inputs when boundary scan mode is active and input data are latched in the capture-d TAP controller state. 9. Use I and I when boundary scan mode is active and input data are latched in the capture-d TAP controller state. 10. This provides a minimum of to a maximum of with POD135, and is normally 70% of DDQ. DAM timings relative to CK cannot be guaranteed if these limits are exceeded. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 17

18 8Gb: 2 Channels x16/x8 GDD6 SGAM Operating Conditions 11. IDCK is the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input reference level for signals other than CK_t and CK_c is EC. 12. IDWCK is the magnitude of the difference between the input level on WCK_t and the input level on WCK_c. The input reference level for signals other than WCK_t and WCK_c is either EC, EC2, ED, or ED The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and CK_c cross. efer to the applicable timings in the AC Timings table. 14. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which WCK_t and WCK_c cross. efer to the applicable timings in the AC Timings table. Table 8: AC Operating Conditions (or Design Only 9 ) Symbol Parameter Min Typ Max Unit Notes IA(AC) AC input logic IG voltage with EC for CA EC IA(AC) AC input logic OW voltage with EC for CA EC 0.18 IA2(AC) AC input logic IG voltage with EC2 for CA EC IA2(AC) AC input logic OW voltage with EC2 for CA EC ID(AC) ID(AC) ID2(AC) ID2(AC) AC input logic IG voltage with ED for DQ, DBI_n AC input logic OW voltage with ED for DQ, DBI_n AC input logic IG voltage with ED2 for DQ, DBI_n AC input logic OW voltage with ED2 for DQ, DBI_n ED ED ED ED IDCK(AC) CK_t, CK_c clock differential voltage , 3, 5 IDWCK(AC) WCK_t, WCK_c clock input differential voltage , 4, 6 IXCK(AC) CK_t, CK_c clock input crossing point voltage EC EC , 2, 5 IXWCK(AC) WCK_t, WCK_c clock input crossing point voltage ED ED , 2, 6, 7 Notes: 1. or AC operations, all DC clock requirements must be satisfied as well. 2. The value of IXCK and IXWCK is expected to equal 70% DDQ for the transmitting device and must track variations in the DC level of the same. 3. IDCK is the magnitude of the difference between the input level on CK_t and the input level on CK_c. The input reference level for signals other than CK_t and CK_c is EC. 4. IDWCK is the magnitude of the difference between the input level on WCK_t and the input level on WCK_c. The input reference level for signals other than WCK_t and WCK_c is either EC, EC2, ED, or ED2. 5. The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and CK_c cross. efer to the applicable timings in the AC Timings table. 6. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which WCK_t and WCK_c cross. efer to the applicable timings in the AC Timings table. 7. ED is either ED, or ED2. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 18

19 8Gb: 2 Channels x16/x8 GDD6 SGAM Operating Conditions 8. igure 14 (page 20) illustrates the exact relationship between (CK_t - CK_c) or (WCK_t - WCK_c) and ID(AC), ID(DC). 9. The AC operating conditions are for DAM design only and are valid on the silicon at the input of the receiver. They are not intended to be measured. igure 13: oltage Waveform DDQ O System noise margin (power/ground, crosstalk, ISI, attenuation) I(AC) I(DC) E + AC noise E + DC error E - DC error E - AC noise I(DC) IN(AC) provides margin between O(MAX) and I(MAX) O,max Input I(AC) Output Note: 1. E, I, and I refer to whichever Exx ( ED, ED2, EC, or EC2 ) is being used. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 19

20 8Gb: 2 Channels x16/x8 GDD6 SGAM Operating Conditions igure 14: Clock Waveform Maximum clock level CK_t ID(AC) MP(DC) IX(AC) ID(DC) CK_c Minimum clock level 8000 S. ederal Way, P.O. Box 6, Boise, ID , Tel: Sales inquiries: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains initial descriptions of products still under development. gddr6_sgram_8gb_brief.pdf - ev. D 10/17 EN 20