1.35V DDR3L-RS SDRAM. MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks. Description. 2Gb: x8, x16 DDR3L-RS SDRAM.

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1 .35R3L-RS SDRAM MT4K256M8 32 Meg x 8 x 8 banks MT4K28M6 6 Meg x 6 x 8 banks 2Gb: x8, x6 DDR3L-RS SDRAM Description Description DDR3L-RS SDRAM.35V is a low current self refresh version, via a TCSR feature, of the DDR3L SDRAM.35V device. Unless stated otherwise, the DDR3L- RS SDRAM meets the functional and timing specifications listed in the equivalent density standard or automotive DDR3L SDRAM data sheets located on Features = Q =.35V V Backward-compatible to = Q =.5V ±.75V Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs CK, CK# 8 internal banks Nominal and dynamic on-die termination ODT for data, strobe, and mask signals Programmable CAS READ latency CL Programmable posted CAS additive latency AL Programmable CAS WRITE latency CWL Fixed burst length BL of 8 and burst chop BC of 4 via the mode register set [MRS] Selectable BC4 or BL8 on-the-fly OTF Write leveling Output driver calibration Multipurpose register T C of C to +95 C Features 64ms, 892-cycle refresh at C to +85 C 32ms at +85 C to +95 C; See SRT Self refresh temperature SRT Automatic self refresh ASR Temperature-compensated self refresh TCSR mode Very low current self refresh mode when at room temperature Options Marking Configuration 256 Meg x 8 256M8 28 Meg x 6 28M6 FBGA package Pb-free x4, x8 78-ball 8mm x.5mm Rev. M, K DA FBGA package Pb-free x6 96-ball FBGA 8mm x 4mm Rev. K JT Timing cycle CL = DDR3-6 CL = 9 DDR3-333 CL = 7 DDR E Temperature Commercial C T C +95 C None Power Saving TCSR M Revision :M /:K Table : Key Timing Parameters Speed Grade Data Rate MT/s Target t RCD- t RP-CL t RCD ns t RP ns CL ns -25, E E Notes:. Backward compatible to 66, CL = 7-87E. 2. Backward compatible to 333, CL = 9-5E. Products and specifications discussed herein are subject to change by Micron without notice.

2 Description Table 2: Addressing Parameter 256 Meg x 8 28 Meg x 6 Configuration 32 Meg x 8 x 8 banks 6 Meg x 6 x 8 banks Refresh count 8K 8K Row address 32K A[4:] 6K A[3:] Bank address 8 BA[2:] 8 BA[2:] Column address K A[9:] K A[9:] Figure : DDR3L-RS Part Numbers Example Part Number: MT4K256M8JE-5M:M Configuration MT4K Package Speed PS Revision - { : Configuration 256 Meg x 8 256M8 28 Meg x 6 28M6 Package 78-ball 8mm x.5mm FBGA 96-ball 8mm x 4mm FBGA DA JT :M/:K Revision Power Saving TCSR M Temperature Commercial None -25-5E -87E Speed Grade t CK =.25ns, CL = t CK =.5ns, CL = 9 t CK =.87ns, CL = 7 Note:. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron s Web site: 2

3 Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 2: 78-Ball FBGA x4, x8 Ball Assignments Top View A NC NF, NF/TDQS# B Q DQ DM, DM/TDQS Q Q C Q DQ2 DQS DQ DQ3 Q D Q NF, DQ6 DQS# Q E F G H J K L M N V REFDQ NC ODT NC Q NF, DQ4 RAS# CAS# CS# WE# BA BA2 A3 A A5 A2 A7 A9 RESET# A3 NF, DQ7 NF, DQ5 CK CK# A/AP ZQ NC V REFCA A2/BC# BA A A4 A A6 A4 A8 Q NC CKE NC Notes:. Ball descriptions listed in Table 3 page 5 are listed as x4, x8 if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only selectable between NF or TDQS# via MRS symbols are defined in Table 3. 3

4 Ball Assignments and Descriptions Figure 3: 96-Ball FBGA x6 Ball Assignments Top View A Q DQ3 DQ5 DQ2 Q B Q UDQS# DQ4 Q C Q DQ DQ9 UDQS DQ Q D Q Q UDM DQ8 Q E Q DQ LDM Q Q F Q DQ2 LDQS DQ DQ3 Q G Q DQ6 LDQS# Q H V REFDQ Q DQ4 DQ7 DQ5 Q J NC RAS# CK NC K ODT CAS# CK# CKE L NC CS# WE# A/AP ZQ NC M BA BA2 NC V REFCA N A3 A A2/BC# BA P A5 A2 A A4 R T A7 RESET# A9 A3 A NC A6 A8 Notes:. Ball descriptions listed in Table 4 page 7 are listed as x6. 2. A comma separates the configuration; a slash defines a selectable function. 4

5 Ball Assignments and Descriptions Table 3: 78-Ball FBGA x4, x8 Ball Descriptions Symbol Type Description A[4:3], A2/BC#, A, A/AP, A[9:] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit A for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA[2:] or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A2/BC#: When enabled in the mode register MR, A2 is sampled during READ and WRITE commands to determine whether burst chop on-the-fly will be performed HIGH = BL8 or no burst chop, LOW = BC4 burst chop. BA[2:] Input Bank address inputs: BA[2:] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:] define which mode register MR, MR, MR2, or MR3 is loaded during the LOAD MODE command. BA[2:] are referenced to V REFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe DQS, DQS# is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables registered HIGH and disables registered LOW internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations all banks idle or active power-down row active in any bank. CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers excluding CK, CK#, CKE, RESET#, and ODT are disabled during power-down. Input buffers excluding CKE and RESET# are disabled during SELF REFRESH. CKE is referenced to V REFCA. CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to V REFDQ. DM has an optional use as TDQS on the x8 device. ODT Input On-die termination: ODT enables registered HIGH and disables registered LOW termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:], DQS, DQS#, and DM for the x8; DQ[3:], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to V REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered and are referenced to V REFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH.8 Q and DC LOW.2 Q. RESET# assertion and deassertion are asynchronous. DQ[3:] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:] are referenced to V REFDQ. 5

6 Ball Assignments and Descriptions Table 3: 78-Ball FBGA x4, x8 Ball Descriptions Continued Symbol Type Description DQ[7:] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:] are referenced to V REFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# I/O Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. Supply Power supply:.35v, v operational; compatible to.5v operation. Q Supply DQ power supply:.35v, v operational; compatible with.5v operation. V REFCA Supply Reference voltage for control, command, and address: V REFCA must be maintained at all times including self refresh for proper device operation. V REFDQ Supply Reference voltage for data: V REFDQ must be maintained at all times including self refresh for proper device operation. Supply Ground. Q Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 24Ω resistor R ZQ, which is tied to Q. NC No connect: These balls should be left unconnected the ball has no connection to the DRAM or to other balls. NF No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. 6

7 Ball Assignments and Descriptions Table 4: 96-Ball FBGA x6 Ball Descriptions Symbol Type Description A3, A2/BC#, A, A/AP, A[9:] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit A for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA[2:] or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A2/BC#: When enabled in the mode register MR, A2 is sampled during READ and WRITE commands to determine whether burst chop on-the-fly will be performed HIGH = BL8 or no burst chop, LOW = BC4 burst chop. BA[2:] Input Bank address inputs: BA[2:] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:] define which mode register MR, MR, MR2, or MR3 is loaded during the LOAD MODE command. BA[2:] are referenced to V REFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe LDQS, LDQS#, UDQS, UDQS# is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables registered HIGH and disables registered LOW internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations all banks idle or active power-down row active in any bank. CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers excluding CK, CK#, CKE, RESET#, and ODT are disabled during power-down. Input buffers excluding CKE and RESET# are disabled during SELF REFRESH. CKE is referenced to V REFCA. CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and LDQS balls. LDM is referenced to V REFDQ. ODT Input On-die termination: ODT enables registered HIGH and disables registered LOW termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[5:], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x6. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to V REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered and are referenced to V REFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH.8 Q and DC LOW.2 Q. RESET# assertion and deassertion are asynchronous. 7

8 Ball Assignments and Descriptions Table 4: 96-Ball FBGA x6 Ball Descriptions Continued Symbol Type Description UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with the input data during a write access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and UDQS balls. UDM is referenced to V REFDQ. DQ[7:] I/O Data input/output: Lower byte of bidirectional data bus for the x6 configuration. DQ[7:] are referenced to V REFDQ. DQ[5:8] I/O Data input/output: Upper byte of bidirectional data bus for the x6 configuration. DQ[5:8] are referenced to V REFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. LDQS is center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. UDQS is center-aligned to write data. Supply Power supply:.35v, v operational; compatible to.5v operation. Q Supply DQ power supply:.35v, v operational; compatible with.5v operation. V REFCA Supply Reference voltage for control, command, and address: V REFCA must be maintained at all times including self refresh for proper device operation. V REFDQ Supply Reference voltage for data: V REFDQ must be maintained at all times including self refresh for proper device operation. Supply Ground. Q Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 24Ω resistor R ZQ, which is tied to Q. NC No connect: These balls should be left unconnected the ball has no connection to the DRAM or to other balls. 8

9 Package Dimensions Package Dimensions Figure 4: 78-Ball FBGA x4, x8; Die Rev. M, K DA.8 ±.5.55 Seating Plane.2 A A.8 CTR Nonconductive overmold 78X Ø.45 Dimensions apply to solder balls post-reflow on Ø.35 SMD ball pads Ball A ID A B C D E F 9.6 CTR G.5 ±. H J K L.8 TYP M N Ball A ID.8 TYP 6.4 CTR 8 ±..2 MAX.25 MIN Notes:. All dimensions are in millimeters. 2. Solder ball material: SAC % Sn, 3% Ag,.5% Cu. 9

10 Package Dimensions Figure 5: 96-Ball FBGA x6; Die Rev. K JT.55 Seating plane.8 CTR Nonconductive overmold A.2 A 96X Ø.45 Dimensions apply to solder balls postreflow on Ø.35 SMD ball pads Ball A ID Ball A ID A B C D E 4 ±. 2 CTR F G H J K L M N P.8 TYP R T.8 TYP 6.4 CTR. ±..25 MIN 8 ±. Notes:. All dimensions are in millimeters. 2. Solder ball material: SAC % Sn, 3% Ag,.5% Cu.

11 Electrical Characteristics I DD Specifications 2Gb: x8, x6 DDR3L-RS SDRAM Electrical Characteristics I DD Specifications Table 5: I DD Maximum Limits Die Rev. M Speed Bin Parameter Symbol Width Operating current : One bank ACTIVATE-to-PRECHARGE Operating current : One bank ACTIVATE-to-READ-to-PRE- CHARGE Precharge power-down current: Slow exit Precharge power-down current: Fast exit DDR3L-RS -66 DDR3L-RS -333 DDR3L-RS -6 Unit Notes I DD x ma I DD x ma I DD2P x ma I DD2P x ma Precharge quiet standby current I DD2Q x ma Precharge standby current I DD2N x ma Precharge standby ODT current I DD2NT x ma Active power-down current I DD3P x ma Active standby current I DD3N x ma Burst read operating current I DD4R x ma Burst write operating current I DD4W x ma Burst refresh current I DD5B x ma Room temperature self refresh I DD6 x ma C temperature self refresh I DD6 x ma 3 Elevated temperature self refresh I DD6 x ma 4 I DD6 x ma 5 Extended temperature self refresh I DD6ET x ma 6 I DD6ET x ma 7 All banks interleaved read current I DD7 x ma Reset current I DD8 x8 I DD2P + 2mA I DD2P + 2mA I DD2P + 2mA ma Notes:. T C = +85 C; SRT is disabled, ASR is disabled. Value is maximum. 2. T C Room Temperature; SRT is disabled, ASR is enabled. Value is typical. 3. T C +45 C; SRT is disabled, ASR is enabled. Value is typical. 4. T C = +8 C; SRT is disabled, ASR is enabled. Value is typical C < T C +8 C; SRT is disabled, ASR is enabled. Value is maximum. 6. T C = +95 C; SRT is disabled, ASR is enabled. Value is typical C < T C +95 C; SRT is disabled, ASR is enabled. Value is maximum.

12 Electrical Characteristics I DD Specifications Table 6: I DD Maximum Limits Die Rev. K Parameter Speed Bin Operating current : One bank ACTIVATE-to-PRECHARGE Operating current : One bank ACTIVATE-to-READ-to-PRE-CHARGE Precharge power-down current: Slow exit Precharge power-down current: Fast exit Symbol Width DDR3L-RS -66 DDR3L-RS -333 DDR3L-RS -6 DDR3L-RS -866 Unit Notes I DD x ma x ma I DD x ma x ma I DD2P All ma I DD2P All ma Precharge quiet standby current I DD2Q All ma Precharge standby current I DD2N All ma Precharge standby ODT current I DD2NT x ma x ma Active power-down current I DD3P All ma Active standby current I DD3N x ma x ma Burst read operating current I DD4R x ma x ma Burst write operating current I DD4W x ma x ma Burst refresh current I DD5B All ma Room temperature self refresh I DD6 All ma C temperature self refresh I DD6 All ma 3 Elevated temperature self refresh I DD6 All ma 4 All ma 5 Extended temperature self refresh I DD6ET All ma 6 All ma 7 All banks interleaved read current I DD7 x ma Reset current I DD8 all I DD2P + 2mA x ma I DD2P + 2mA I DD2P + 2mA I DD2P + 2mA ma Notes:. T C = +85 C; SRT is disabled, ASR is disabled. Value is maximum. 2. T C Room Temperature; SRT is disabled, ASR is enabled. Value is typical. 3. T C +45 C; SRT is disabled, ASR is enabled. Value is typical. 4. T C = +8 C; SRT is disabled, ASR is enabled. Value is typical C < T C +8 C; SRT is disabled, ASR is enabled. Value is maximum. 6. T C = +95 C; SRT is disabled, ASR is enabled. Value is typical C < T C +95 C; SRT is disabled, ASR is enabled. Value is maximum. 2

13 Temperature Compensated Self Refresh TCSR Mode Register 2 MRS Figure 6: Mode Register 2 MR2 Definition 2Gb: x8, x6 DDR3L-RS SDRAM Temperature Compensated Self Refresh TCSR Temperature compensated self refresh TCSR feature substantially reduces the self refresh current I DD6. TCSR takes affect when when T C is less than 45 C and the auto self refresh ASR function is enabled. ASR is required to utilize the TCSR feature and is enabled manually via Mode Register 2 MR2[6]. See Figure 6 page 3. Enabling ASR also automatically changes the DRAM self refresh rate from x to 2x when the case temperature exceeds +85 C. This allows the user to operate the DRAM beyond the standard 85 C limit up to the optional extended temperature range of +95 C while in self refresh mode. When ASR is disabled and T C is C to 85 C, the self refresh mode s refresh rate is assumed to be at the normal rate sometimes referred to as x refresh rate. Also, if ASR is disabled and T C is 85 C to 95 C, the user must select the SRT extended temperature self refresh rate sometimes referred to as 2x refresh rate. SRT is selected via mode register 2 MR2[7] register. See Figure 6 page 3. SPD settings should always support 5h binary in Byte 3. The mode register 2 MR2 controls additional functions and features not available in the other mode registers. The auto self refresh ASR function is of particular interest for the DDR3L-RS SDRAM because the Micron DDR3L-RS SDRAM goes into TCSR mode when ASR has been enabled. This function is controlled via the bits shown in the figure below. BA2 BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address bus R TTWR SRT ASR CWL Mode register 2 MR2 M5 M4 Mode Register Mode register set MR Mode register set MR Mode register set 2 MR2 Mode register set 3 MR3 M M9 Dynamic ODT R TTWR R TTWR disabled RZQ/4 RZQ/2 Reserved M7 Self Refresh Temperature Normal C to 85 C Extended C to 95 C M6 Auto Self Refresh Optional Disabled: Manual Enabled: Automatic M5 M4 M3 CAS Write Latency CWL 5 CK t CK 2.5ns 6 CK 2.5ns > t CK.875ns 7 CK.875ns > t CK.5ns 8 CK.5ns > t CK.25ns 9 CK.25ns > t CK.7ns CK.7ns > t CK.938ns Reserved Reserved Note:. MR2[7, 4:, 8, and 2:] are reserved for future use and must all be programmed to. 3

14 Electrical Specifications Electrical Specifications Table 7: Input/Output Capacitance Gray-shaded cells have the same values as those in the.5r3 data sheet Capacitance Parameters Symbol DDR3L-8 DDR3L-66 DDR3L-333 DDR3L-6 DDR3L-866 Min Max Min Max Min Max Min Max Min Max Single-end I/O: DQ, DM C IO pf Differential I/O: DQS, DQS#, TDQS, TDQS# Inputs CTRL, CMD,ADDR C IO pf C I pf Units Table 8: DC Electrical Characteristics and Operating Conditions.35V Operation All voltages are referenced to Parameter/Condition Symbol Min Nom Max Units Notes Supply voltage V, 2, 3, 4 I/O supply voltage Q V, 2, 3, 4 Notes:. Maximum DC value may not be greater than.425v. The DC value is the linear average of /Q t over a very long period of time for example, sec. 2. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 3. Under these supply voltages, the device operates to this DDR3L specification. 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while and Q are changed for DDR3 operation see Figure 7 page 26. Table 9: DC Electrical Characteristics and Operating Conditions.5V Operation All voltages are referenced to Parameter/Condition Symbol Min Nom Max Units Notes Supply voltage V, 2, 3 I/O supply voltage Q V, 2, 3 Notes:. If the minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while and Q are changed for DDR3L operation see Figure 7 page 26. 4

15 Electrical Specifications Table : Input Switching Conditions Command and Address Parameter/Condition Symbol DDR3L-8/66 DDR3L-333/6 DDR3L-866 Units Input high AC voltage: Logic V IHAC6min 6 6 mv Input high AC voltage: Logic V IHAC35min mv Input high AC voltage: Logic V IHAC25min 25 mv Input high DC voltage: Logic V IHDC9min mv Input low DC voltage: Logic V ILDC9min mv Input low AC voltage: Logic V ILAC25min 25 mv Input low AC voltage: Logic V ILAC35min mv Input low AC voltage: Logic V ILAC6min 6 6 mv Note:. When two V IHAC values and two corresponding V ILAC values are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IHAC value may be used for address/command inputs and the other V IHAC value may be used for data inputs. For example, for DDR3L-8, two input AC levels are defined: V IHAC6,min and V IHAC35,min corresponding V ILAC6,min and V ILAC35,min. For DDRL-8, the address/ command inputs must use either V IHAC6,min with t ISAC6 of 25ps or V IHAC35,min with t ISAC35 of 365ps; independently, the data inputs may use either V IHAC6,min or V IHAC35,min. Table : Input Switching Conditions DQ and DM Parameter/Condition Symbol DDR3L-8/66 DDR3L-333/6 DDR3L-866 Units Input high AC voltage: Logic V IHAC6min 6 6 mv Input high AC voltage: Logic V IHAC35min mv Input high AC voltage: Logic V IHAC3min 3 mv Input high DC voltage: Logic V IHDC9min mv Input low DC voltage: Logic V ILDC9min mv Input low AC voltage: Logic V ILAC3min 3 mv Input low AC voltage: Logic V ILAC35min mv Input low AC voltage: Logic V ILAC6min 6 6 mv Note:. When two V IHAC values and two corresponding V ILAC values are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IHAC value may be used for address/command inputs and the other V IHAC value may be used for data inputs. For example, for DDR3L-8, two input AC levels are defined: V IHAC6,min and V IHAC35,min corresponding V ILAC6,min and V ILAC35,min. For DDRL-8, the data inputs must use either V IHAC6,min with t ISAC6 of 9ps or V IHAC35,min with t ISAC35 of 4ps; independently, the address/command inputs may use either V IHAC6,min or V IHAC35,min. 5

16 Electrical Specifications Table 2: Differential Input Operating Conditions CK, CK# and DQS, DQS# Parameter/Condition Symbol Min Max Units Differential input logic high slew V IH,diffACslew 8 N/A mv Differential input logic low slew V IL,diffACslew N/A 8 mv Differential input logic high V IH,diffAC 2 V IHAC - V REF /Q mv Differential input logic low V IL,diffAC /Q 2 V ILAC - V REF mv Single-ended high level for strobes V SEH Q /2 + 6 Q mv Single-ended high level for CK, CK# /2 + 6 mv Single-ended low level for strobes V SEL Q Q /2-6 mv Single-ended low level for CK, CK# /2-6 mv Table 3: Minimum Required Time t DVAC for CK/CK#, DQS/DQS# Differential for AC Ringback Slew Rate V/ns DDR3L-8/66/333/6 t DVAC at 32mV ps t DVAC at 27mV ps t DVAC at 27mV ps DDR3L-866 t DVAC at 25mV ps t DVAC at 26mV ps > Note Note Note Note Note Note <. Note Note Note Note Note Note:. Rising input signal shall become equal to or greater than VIHac level and Falling input signal shall become equal to or less than VILac level. 6

17 Electrical Specifications Table 4: R TT Effective Impedance Gray-shaded cells have the same values as those in the.5r3 data sheet MR [9, 6, 2] R TT Resistor V OUT Min Nom Max Units,, 2Ω R TT,2PD24.2 Q.6..5 RZQ/.5 Q.9..5 RZQ/.8 Q RZQ/ R TT,2PU24.2 Q RZQ/.5 Q.9..5 RZQ/.8 Q.6..5 RZQ/ 2Ω V ILAC to V IHAC RZQ/2,, 6Ω R TT,6PD2.2 Q.6..5 RZQ/2.5 Q.9..5 RZQ/2.8 Q RZQ/2 R TT,6PU2.2 Q RZQ/2.5 Q.9..5 RZQ/2.8 Q.6..5 RZQ/2 6Ω V ILAC to V IHAC RZQ/4,, 4Ω R TT,4PD8.2 Q.6..5 RZQ/3.5 Q.9..5 RZQ/3.8 Q RZQ/3 R TT,4PU8.2 Q RZQ/3.5 Q.9..5 RZQ/3.8 Q.6..5 RZQ/3 4Ω V ILAC to V IHAC RZQ/6,, 3Ω R TT,3PD6.2 Q.6..5 RZQ/4.5 Q.9..5 RZQ/4.8 Q RZQ/4 R TT,3PU6.2 Q RZQ/4.5 Q.9..5 RZQ/4.8 Q.6..5 RZQ/4 3Ω V ILAC to V IHAC RZQ/8,, 2Ω R TT,2PD4.2 Q.6..5 RZQ/6.5 Q.9..5 RZQ/6.8 Q RZQ/6 R TT,2PU4.2 Q RZQ/6.5 Q.9..5 RZQ/6.8 Q.6..5 RZQ/6 2Ω V ILAC to V IHAC RZQ/2 7

18 Electrical Specifications Table 5: Reference Settings for ODT Timing Measurements Gray-shaded cells have the same values as those in the.5r3 data sheet Measured Parameter R TT,nom Setting R TTWR Setting V SW V SW2 t AON RZQ/4 6Ω N/A 5mV mv RZQ/2 2Ω N/A mv 2mV t AOF RZQ/4 6Ω N/A 5mV mv RZQ/2 2Ω N/A mv 2mV t AONPD RZQ/4 6Ω N/A 5mV mv RZQ/2 2Ω N/A mv 2mV t AOFPD RZQ/4 6Ω N/A 5mV mv RZQ/2 2Ω N/A mv 2mV t ADC RZQ/2 2Ω RZQ/2 2Ω 2mV 25mV Table 6: 34Ω Driver Impedance Characteristics Gray-shaded cells have the same values as those in the.5r3 data sheet MR [5, ] R ON Resistor V OUT Min Nom Max Units, 34.3Ω R ON,34PD.2 Q.6..5 RZQ/7.5 Q.9..5 RZQ/7.8 Q RZQ/7 R ON,34PU.2 Q RZQ/7.5 Q.9..5 RZQ/7.8 Q.6..5 RZQ/7 Pull-up/pull-down mismatch MM PUPD V ILAC to V IHAC N/A % Note:. A larger maximum limit will result in slightly lower minimum currents. Table 7: 4Ω Driver Impedance Characteristics Gray-shaded cells have the same values as those in the.5r3 data sheet MR [5, ] R ON Resistor V OUT Min Nom Max Units, 4Ω R ON,4PD.2 Q.6..5 RZQ/6.5 Q.9..5 RZQ/6.8 Q RZQ/6 R ON,4PU.2 Q RZQ/6.5 Q.9..5 RZQ/6.8 Q.6..5 RZQ/6 Pull-up/pull-down mismatch MM PUPD V ILAC to V IHAC N/A % Note:. A larger maximum limit will result in slightly lower minimum currents. 8

19 Electrical Specifications Table 8: Single-Ended Output Driver Characteristics Gray-shaded cells have the same values as those in the.5r3 data sheet Parameter/Condition Symbol Min Max Units Output slew rate: Single-ended; For rising and falling edges, measure between V OLAC = V REF -.9 Q and V OHAC = V REF +.9 Q SRQ se.75 6 V/ns Table 9: Differential Output Driver Characteristics Gray-shaded cells have the same values as those in the.5r3 data sheet Parameter/Condition Symbol Min Max Units Output slew rate: Differential; For rising and falling edges, measure between V OL,diffAC =.8 Q and V OH,diffAC =.8 Q SRQ diff V/ns Output differential crosspoint voltage V OXAC V REF - 35 V REF + 35 mv Table 2: Electrical Characteristics and AC Operating Conditions Note applies to base timing specifications Parameter Data setup time to DQS, DQS# Data setup time to DQS, DQS# Data hold time from DQS, DQS# Data setup time to DQS, DQS# Data hold time from DQS, DQS# CTRL, CMD, ADDR setup to CK, CK# CTRL, CMD, ADDR setup to CK, CK# Base specification Symbol AC6 DDR3L-8 DDR3L-66 DDR3L-333 DDR3L-6 DDR3L-866 Min Max Min Max Min Max Min Max Min Max DQ Input Timing Units 9 4 N/A N/A N/A ps V V/ns 25 2 N/A N/A N/A ps Base specification AC N/A ps V V/ns N/A ps Base specification DC N/A ps V V/ns N/A ps Base specification AC3 N/A N/A N/A N/A 7 ps V 2 V/ns N/A N/A N/A N/A 35 ps Base specification DC9 N/A N/A N/A N/A 75 ps V 2 V/ns N/A N/A N/A N/A ps Base specification t IS AC6 Command and Address Timing N/A ps V V/ns N/A ps Base specification t IS AC ps V V/ns ps 9

20 Electrical Specifications Table 2: Electrical Characteristics and AC Operating Conditions Continued Note applies to base timing specifications Parameter CTRL, CMD, ADDR setup to CK, CK# CTRL, CMD, ADDR hold from CK, CK# Base specification Symbol t IS AC25 DDR3L-8 DDR3L-66 DDR3L-333 DDR3L-6 DDR3L-866 Min Max Min Max Min Max Min Max Min Max Units N/A N/A N/A N/A 5 ps V V/ns N/A N/A N/A N/A 275 ps Base specification t IH DC ps V V/ns ps Notes:. When two V IHAC values and two corresponding V ILAC values are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IHAC value may be used for address/command inputs and the other V IHAC value may be used for data inputs. For example, for DDR3-8, two input AC levels are defined: V IHAC6,min and V IHAC35,min corresponding V ILAC6,min and V ILAC35,min. For DDR3-8, the address/ command inputs must use either V IHAC6,min with t ISAC6 of 25ps or V IHAC35,min with t ISAC35 of 365ps; independently, the data inputs must use either V IHAC6,min with AC6 of 9ps or V IHAC35,min with AC35 of 4ps. 2. When DQ single-ended slew rate is V/ns, the DQS differential slew rate is 2V/ns; when DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns; Table 2: Derating Values for t IS/ t IH AC6/DC9-Based CMD/ADDR Slew Rate V/ns t IS, t IH Derating ps AC/DC-Based CK, CK# Differential Slew Rate 4. V/ns 3. V/ns 2. V/ns.8 V/ns.6 V/ns.4 V/ns.2 V/ns. V/ns t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH

21 Electrical Specifications Table 22: Derating Values for t IS/ t IH AC35/DC9-Based CMD/ADDR Slew Rate V/ns t IS, t IH Derating ps AC/DC-Based CK, CK# Differential Slew Rate 4. V/ns 3. V/ns 2. V/ns.8 V/ns.6 V/ns.4 V/ns.2 V/ns. V/ns t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH Table 23: Derating Values for t IS/ t IH AC25/DC9-Based CMD/ADDR Slew Rate V/ns t IS, t IH Derating ps AC/DC-Based CK, CK# Differential Slew Rate 4. V/ns 3. V/ns 2. V/ns.8 V/ns.6 V/ns.4 V/ns.2 V/ns. V/ns t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH t IS t IH

22 Electrical Specifications Table 24: Minimum Required Time t VAC Above V IHAC Below V IL[AC] for Valid ADD/CMD Transition DDR3L-8/66/333/6 DDR3L-866 Slew Rate V/ns t VAC at 6mV ps t VAC at 35mV ps t VAC at 35mV ps t VAC at 25mV ps > Note 64 Note 8 <.5 Note 64 Note 8 Note:. Rising input signal shall become equal to or greater than V IHAC level and Falling input signal shall become equal to or less than V ILAC level. Table 25: Derating Values for / AC6/DC9-Based DQ Slew Rate V/ns, Derating ps AC/DC-Based DQS, DQS# Differential Slew Rate 4. V/ns 3. V/ns 2. V/ns.8 V/ns.6 V/ns.4 V/ns.2 V/ns. V/ns

23 Electrical Specifications Table 26: Derating Values for / AC35/DC9-Based DQ Slew Rate V/ns, Derating ps AC/DC-Based DQS, DQS# Differential Slew Rate 4. V/ns 3. V/ns 2. V/ns.8 V/ns.6 V/ns.4 V/ns.2 V/ns. V/ns

24 24 Table 27: Derating Values for / AC3/DC-Based at 2V/ns Shaded cells indicate slew rate combinations not supported, Derating ps AC/DC-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate 8. V/ns 7. V/ns 6. V/ns 5. V/ns 4. V/ns 3. V/ns 2. V/ns.8 V/ns.6 V/ns.4 V/ns.2 V/ns. V/ns Gb: x8, x6 DDR3L-RS SDRAM Electrical Specifications

25 Voltage Initialization / Change Table 28: Minimum Required Time t VAC Above V IHAC Below V ILAC for Valid DQ Transition Slew Rate V/ns t VAC at 6mV ps t VAC at 35mV ps t VAC at 3mV ps > Note.7 6 Note.6 Note Note.5 Note Note <.5 Note Note Note:. Rising input signal shall become equal to or greater than V IHAC level and Falling input signal shall become equal to or less than V ILAC level. Voltage Initialization / Change If the SDRAM is powered up and initialized for the.35v operating voltage range, voltage can be increased to the.5v operating range provided that: Just prior to increasing the.35v operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. The.5V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. The DLL is reset and relocked after the.5v operating voltages are stable and prior to any READ command. The ZQ calibration is performed. t ZQinit must be satisfied after the.5v operating voltages are stable and prior to any READ command. If the SDRAM is powered up and initialized for the.5v operating voltage range, voltage can be reduced to the.35v operation range provided that: Just prior to reducing the.5v operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. The.35V operating voltages are stable prior to issuing new commands, other than NOPs or COMMAND INHIBITs. The DLL is reset and relocked after the.35v operating voltages are stable and prior to any READ command. The ZQ calibration is performed. t ZQinit must be satisfied after the.35v operating voltages are stable and prior to any READ command. 25

26 Voltage Switching 2Gb: x8, x6 DDR3L-RS SDRAM Voltage Initialization / Change After the DDR3L DRAM is powered up and initialized, the power supply can be altered between the DDR3L and DDR3 levels, provided the sequence in Figure 7 is maintained. Figure 7: Voltage Switching Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, CK# t CKSRX, Q DDR3 T MIN = ns, Q DDR3L T MIN = ns T MIN = 2µs T = 5µs RESET# tis CKE T MIN = ns Valid t DLLK txpr tmrd tmrd tmrd tmod t ZQinit t IS Command Note MRS MRS MRS MRS ZQCL Note Valid BA MR2 MR3 MR MR Valid t IS t IS ODT Static LOW in case R TT,nom is enabled at time Tg, otherwise static HIGH or LOW Valid R TT Time break Don t Care Note:. From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands. 8 S. Federal Way, P.O. Box 6, Boise, ID , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 26