Automotive DDR3 SDRAM

Transcription

1 Automotive DDR3 SDRAM MT41J128M8 16 Meg x 8 x 8 banks MT41J64M16 8 Meg x 16 x 8 banks 1Gb: x8, x16 Automotive DDR3 SDRAM Features Features Industrial and automotive temperature compliant V DD = V DDQ = 1.5V ±0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (, #) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS READ latency (CL) POSTED CAS ADTIVE latency (AL) Programmable CAS WRITE latency (CWL) based on t Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode T C 40 0 C to +95 C/+105 C 64ms, 8192 cycle refresh at 40 C to +85 C 32ms, 8192 cycle refresh at 85 C to +95 C/+105 C Self refresh temperature (SRT) Automatic self refresh (ASR) Write leveling Multipurpose register Output driver calibration AEC-Q100 PPAP submission 8D response time Options 1 Marking Configuration 128 Meg x 8 128M8 64 Meg x 16 64M16 FBGA package (Pb-free) x4, x8 78-ball (8mm x 11.5mm) Rev. G JP FBGA package (Pb-free) x16 96-ball (8mm x 14mm) Rev. G JT Timing cycle time CL = 11 (DDR3-1600) -125 CL = 10 (DDR3-1600) -125E CL = 10 (DDR3-1333) -15 CL = 9 (DDR3-1333) -15E CL = 8 (DDR3-1066) -187 CL = 7 (DDR3-1066) -187E Operating temperature Industrial ( 40 C T C +95 C) AIT Automotive ( 40 C T C +105 C) AAT Revision :G Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) , E 1, E E Notes: 1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). 1 Products and specifications discussed herein are subject to change by Micron without notice.

2 Features 3. Backward compatible to 1066, CL = 8 (-187). Table 2: Addressing Parameter 128 Meg x 8 64 Meg x 16 Configuration 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks Refresh count 8K 8K Row addressing 16K (A[13:0]) 8K (A[12:0]) Bank addressing 8 (BA[2:0]) 8 (BA[2:0]) Column addressing 1K (A[9:0]) 1K (A[9:0]) Page Size 1KB 2KB Figure 1: DDR3 Part Numbers Example Part Number: MT41J128M8JP-15 AIT :G MT41J Configuration Package Speed Revision - : G Revision Configuration Temperature 128 Meg x 8 64 Meg x M8 64M16 Automotive industrial temperature Automotive temperature AIT AAT Package 78-ball 8mm x 11.5mm FBGA Rev. G Mark JP -125 Speed Grade t = 1.25ns, CL = ball 8mm x 14mm FBGA G JT -125E t = 1.25ns, CL = t = 1.5ns, CL = 10-15E t = 1.5ns, CL = t = 1.87ns, CL = 8-187E t = 1.87ns, CL = 7 Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron s Web site: 2

3 Features Contents State Diagram Functional Description Automotive Industrial Temperature Automotive Temperature General Notes Functional Block Diagrams Ball Assignments and Descriptions Package Dimensions Thermal Characteristics Electrical Specifications I DD Specifications and Conditions Electrical Characteristics I DD Specifications Electrical Specifications DC and AC DC Operating Conditions Input Operating Conditions AC Overshoot/Undershoot Specification Slew Rate Definitions for Single-Ended Input Signals Slew Rate Definitions for Differential Input Signals ODT Characteristics ODT Resistors ODT Sensitivity ODT Timing Definitions Output Driver Impedance Ohm Output Driver Impedance Ohm Driver Ohm Output Driver Sensitivity Alternative 40 Ohm Driver Ohm Output Driver Sensitivity Output Characteristics and Operating Conditions Reference Output Load Slew Rate Definitions for Single-Ended Output Signals Slew Rate Definitions for Differential Output Signals Speed Bin Tables Electrical Characteristics and AC Operating Conditions Command and Address Setup, Hold, and Derating Data Setup, Hold, and Derating Commands Truth Tables Commands DESELECT NO OPERATION ZQ CALIBRATION LONG ZQ CALIBRATION SHORT ACTIVATE READ WRITE PRECHARGE REFRESH SELF REFRESH DLL Disable Mode Input Clock Frequency Change Write Leveling

4 Features Write Leveling Procedure Write Leveling Mode Exit Procedure Initialization Mode Registers Mode Register 0 (MR0) Burst Length Burst Type DLL RESET Write Recovery Precharge Power-Down (Precharge PD) CAS Latency (CL) Mode Register 1 (MR1) DLL Enable/DLL Disable Output Drive Strength OUTPUT ENABLE/SABLE TDQS Enable On-Die Termination WRITE LEVELING POSTED CAS ADTIVE Latency Mode Register 2 (MR2) CAS Write Latency (CWL) AUTO SELF REFRESH (ASR) SELF REFRESH TEMPERATURE (SRT) SRT vs. ASR DYNAMIC ODT Mode Register 3 (MR3) MULTIPURPOSE REGISTER (MPR) MPR Functional Description MPR Register Address Definitions and Bursting Order MPR Read Predefined Pattern MODE REGISTER SET (MRS) Command ZQ CALIBRATION Operation ACTIVATE Operation READ Operation WRITE Operation DQ Input Timing PRECHARGE Operation SELF REFRESH Operation Extended Temperature Usage Power-Down Mode RESET Operation On-Die Termination (ODT) Functional Representation of ODT Nominal ODT Dynamic ODT Dynamic ODT Special Use Case Functional Description Synchronous ODT Mode ODT Latency and Posted ODT Timing Parameters ODT Off During READs Asynchronous ODT Mode

5 Features Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) Asynchronous to Synchronous ODT Mode Transition (Short E Pulse)

6 Features List of Figures Figure 1: DDR3 Part Numbers... 2 Figure 2: Simplified State Diagram Figure 3: 128 Meg x 8 Functional Block Diagram Figure 4: 64 Meg x 16 Functional Block Diagram Figure 5: 78-Ball FBGA x8 (Top View) Figure 6: 96-Ball FBGA x16 (Top View) Figure 7: 78-Ball FBGA x8 (JP) Figure 8: 96-Ball FBGA x16 (JT) Figure 9: Thermal Measurement Point Figure 10: Input Signal Figure 11: Overshoot Figure 12: Undershoot Figure 13: V IX for Differential Signals Figure 14: Single-Ended Requirements for Differential Signals Figure 15: Definition of Differential AC-Swing and t DVAC Figure 16: Nominal Slew Rate Definition for Single-Ended Input Signals Figure 17: Nominal Differential Input Slew Rate Definition for DQS, DQS# and, # Figure 18: ODT Levels and I-V Characteristics Figure 19: ODT Timing Reference Load Figure 20: t AON and t AOF Definitions Figure 21: t AONPD and t AOFPD Definitions Figure 22: t ADC Definition Figure 23: Output Driver Figure 24: DQ Output Signal Figure 25: Differential Output Signal Figure 26: Reference Output Load for AC Timing and Output Slew Rate Figure 27: Nominal Slew Rate Definition for Single-Ended Output Signals Figure 28: Nominal Differential Output Slew Rate Definition for DQS, DQS# Figure 29: Nominal Slew Rate and t VAC for t IS (Command and Address Clock) Figure 30: Nominal Slew Rate for t IH (Command and Address Clock) Figure 31: Tangent Line for t IS (Command and Address Clock) Figure 32: Tangent Line for t IH (Command and Address Clock) Figure 33: Nominal Slew Rate and t VAC for t DS (DQ Strobe) Figure 34: Nominal Slew Rate for t DH (DQ Strobe) Figure 35: Tangent Line for t DS (DQ Strobe) Figure 36: Tangent Line for t DH (DQ Strobe) Figure 37: Refresh Mode Figure 38: DLL Enable Mode to DLL Disable Mode Figure 39: DLL Disable Mode to DLL Enable Mode Figure 40: DLL Disable t DQS Figure 41: Change Frequency During Precharge Power-Down Figure 42: Write Leveling Concept Figure 43: Write Leveling Sequence Figure 44: Write Leveling Exit Procedure Figure 45: Initialization Sequence Figure 46: MRS to MRS Command Timing ( t MRD) Figure 47: MRS to nonmrs Command Timing ( t MOD) Figure 48: Mode Register 0 (MR0) Definitions Figure 49: READ Latency Figure 50: Mode Register 1 (MR1) Definition

7 Features Figure 51: READ Latency (AL = 5, CL = 6) Figure 52: Mode Register 2 (MR2) Definition Figure 53: CAS Write Latency Figure 54: Mode Register 3 (MR3) Definition Figure 55: Multipurpose Register (MPR) Block Diagram Figure 56: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout Figure 57: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout Figure 58: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble Figure 59: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble Figure 60: ZQ CALIBRATION Timing (ZQCL and ZQCS) Figure 61: Example: Meeting t RRD (MIN) and t RCD (MIN) Figure 62: Example: t FAW Figure 63: READ Latency Figure 64: Consecutive READ Bursts (BL8) Figure 65: Consecutive READ Bursts (BC4) Figure 66: Nonconsecutive READ Bursts Figure 67: READ (BL8) to WRITE (BL8) Figure 68: READ (BC4) to WRITE (BC4) OTF Figure 69: READ to PRECHARGE (BL8) Figure 70: READ to PRECHARGE (BC4) Figure 71: READ to PRECHARGE (AL = 5, CL = 6) Figure 72: READ with Auto Precharge (AL = 4, CL = 6) Figure 73: Data Output Timing t DQSQ and Data Valid Window Figure 74: Data Strobe Timing READs Figure 75: Method for Calculating t LZ and t HZ Figure 76: t RPRE Timing Figure 77: t RPST Timing Figure 78: t WPRE Timing Figure 79: t WPST Timing Figure 80: WRITE Burst Figure 81: Consecutive WRITE (BL8) to WRITE (BL8) Figure 82: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF Figure 83: Nonconsecutive WRITE to WRITE Figure 84: WRITE (BL8) to READ (BL8) Figure 85: WRITE to READ (BC4 Mode Register Setting) Figure 86: WRITE (BC4 OTF) to READ (BC4 OTF) Figure 87: WRITE (BL8) to PRECHARGE Figure 88: WRITE (BC4 Mode Register Setting) to PRECHARGE Figure 89: WRITE (BC4 OTF) to PRECHARGE Figure 90: Data Input Timing Figure 91: Self Refresh Entry/Exit Timing Figure 92: Active Power-Down Entry and Exit Figure 93: Precharge Power-Down (Fast-Exit Mode) Entry and Exit Figure 94: Precharge Power-Down (Slow-Exit Mode) Entry and Exit Figure 95: Power-Down Entry After READ or READ with Auto Precharge (RDAP) Figure 96: Power-Down Entry After WRITE Figure 97: Power-Down Entry After WRITE with Auto Precharge (WRAP) Figure 98: REFRESH to Power-Down Entry Figure 99: ACTIVATE to Power-Down Entry Figure 100: PRECHARGE to Power-Down Entry Figure 101: MRS Command to Power-Down Entry Figure 102: Power-Down Exit to Refresh to Power-Down Entry

8 Features Figure 103: RESET Sequence Figure 104: On-Die Termination Figure 105: Dynamic ODT: ODT Asserted Before and After the WRITE, BC Figure 106: Dynamic ODT: Without WRITE Command Figure 107: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL Figure 108: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC Figure 109: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC Figure 110: Synchronous ODT Figure 111: Synchronous ODT (BC4) Figure 112: ODT During READs Figure 113: Asynchronous ODT Timing with Fast ODT Transition Figure 114: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry Figure 115: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit Figure 116: Transition Period for Short E LOW Cycles with Entry and Exit Period Overlapping Figure 117: Transition Period for Short E HIGH Cycles with Entry and Exit Period Overlapping

9 Features List of Tables Table 1: Key Timing Parameters... 1 Table 2: Addressing... 2 Table 3: 78-Ball FBGA x8 Ball Descriptions Table 4: 96-Ball FBGA x16 Ball Descriptions Table 5: Thermal Characteristics Table 6: Timing Parameters Used for I DD Measurements Clock Units Table 7: I DD0 Measurement Loop Table 8: I DD1 Measurement Loop Table 9: I DD Measurement Conditions for Power-Down Currents Table 10: I DD2N and I DD3N Measurement Loop Table 11: I DD2NT Measurement Loop Table 12: I DD4R Measurement Loop Table 13: I DD4W Measurement Loop Table 14: I DD5B Measurement Loop Table 15: I DD Measurement Conditions for I DD6, I DD6ET, and I DD Table 16: I DD7 Measurement Loop Table 17: I DD Maximum Limits Table 18: DC Electrical Characteristics and Operating Conditions Table 19: DC Electrical Characteristics and Input Conditions Table 20: Input Switching Conditions Table 21: Control and Address Pins Table 22: Clock, Data, Strobe, and Mask Pins Table 23: Differential Input Operating Conditions (, # and DQS, DQS#) Table 24: Allowed Time Before Ringback ( t DVAC) for - # and DQS - DQS# Table 25: Single-Ended Input Slew Rate Definition Table 26: Differential Input Slew Rate Definition Table 27: On-Die Termination DC Electrical Characteristics Table 28: R TT Effective Impedances Table 29: ODT Sensitivity Definition Table 30: ODT Temperature and Voltage Sensitivity Table 31: ODT Timing Definitions Table 32: Reference Settings for ODT Timing Measurements Table 33: 34 Ohm Driver Impedance Characteristics Table 34: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations Table 35: 34 Ohm Driver I OH /I OL Characteristics: V DD = V DDQ = 1.5V Table 36: 34 Ohm Driver I OH /I OL Characteristics: V DD = V DDQ = 1.575V Table 37: 34 Ohm Driver I OH /I OL Characteristics: V DD = V DDQ = 1.425V Table 38: 34 Ohm Output Driver Sensitivity Definition Table 39: 34 Ohm Output Driver Voltage and Temperature Sensitivity Table 40: 40 Ohm Driver Impedance Characteristics Table 41: 40 Ohm Output Driver Sensitivity Definition Table 42: 40 Ohm Output Driver Voltage and Temperature Sensitivity Table 43: Single-Ended Output Driver Characteristics Table 44: Differential Output Driver Characteristics Table 45: Single-Ended Output Slew Rate Definition Table 46: Differential Output Slew Rate Definition Table 47: DDR Speed Bins Table 48: DDR Speed Bins Table 49: DDR Speed Bins Table 50: DDR Speed Bins

10 Features Table 51: Electrical Characteristics and AC Operating Conditions Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions Table 53: Command and Address Setup and Hold Values Referenced at 1 V/ns AC/DC-Based Table 54: Derating Values for t IS/ t IH AC175/DC100-Based Table 55: Derating Values for t IS/ t IH AC150/DC100-Based Table 56: Derating Values for t IS/ t IH AC135/DC100-Based Table 57: Derating Values for t IS/ t IH AC125/DC100-Based Table 58: Minimum Required Time t VAC Above V IH(AC) for Valid Transition Table 59: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) AC/DC-Based Table 60: Derating Values for t DS/ t DH AC175/DC100-Based Table 61: Derating Values for t DS/ t DH AC150/DC100-Based Table 62: Derating Values for t DS/ t DH AC135/DC100-Based Table 63: Required Time t VAC Above V IH(AC) (Below V IL(AC) ) for Valid Transition Table 64: Truth Table Command Table 65: Truth Table E Table 66: READ Command Summary Table 67: WRITE Command Summary Table 68: READ Electrical Characteristics, DLL Disable Mode Table 69: Write Leveling Matrix Table 70: Burst Order Table 71: MPR Functional Description of MR3 Bits Table 72: MPR Readouts and Burst Order Bit Mapping Table 73: Self Refresh Temperature and Auto Self Refresh Description Table 74: Self Refresh Mode Summary Table 75: Command to Power-Down Entry Parameters Table 76: Power-Down Modes Table 77: Truth Table ODT (Nominal) Table 78: ODT Parameters Table 79: Write Leveling with Dynamic ODT Special Case Table 80: Dynamic ODT Specific Parameters Table 81: Mode Registers for R TT,nom Table 82: Mode Registers for R TT(WR) Table 83: Timing Diagrams for Dynamic ODT Table 84: Synchronous ODT Parameters Table 85: Asynchronous ODT Timing Parameters for All Speed Bins Table 86: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period

11 State Diagram State Diagram Figure 2: Simplified State Diagram Power applied Power on Reset procedure Initialization MRS, MPR, write leveling Self refresh E L From any state RESET ZQCL ZQ calibration ZQCL/ZQCS MRS Idle SRX REF SRE Refreshing ACT PDE PDX Active powerdown Activating Precharge powerdown E L PDX PDE E L WRITE WRITE Bank active READ READ Writing WRITE AP WRITE READ AP READ Reading WRITE AP READ AP WRITE AP READ AP Writing PRE, PREA PRE, PREA PRE, PREA Reading ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE Precharging PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry Automatic sequence Command sequence SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION 11

12 Functional Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock ( and #). The crossing of going HIGH and # going LOW is referred to as the positive edge of. Control, command, and address signals are registered at every positive edge of. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Automotive Industrial Temperature The automotive industrial temperature (AIT) device requires that the case temperature not exceed 40 C or +95 C. JEDEC specifications require the refresh rate to double when T C exceeds +85 C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when T C is < 0 C or >+95 C. Automotive Temperature 1Gb: x8, x16 Automotive DDR3 SDRAM Functional Description The automotive temperature (AAT) device requires that the case temperature not exceed 40 C or +105 C. JEDEC specifications require the refresh rate to double when T C exceeds +85 C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when T C is < 0 C or > +95 C. 12

13 Functional Description General Notes The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation). Throughout this data sheet, various figures and text refer to DQs as DQ. DQ is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. The terms DQS and found throughout this data sheet are to be interpreted as DQS, DQS# and, # respectively, unless specifically stated otherwise. Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation. Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4, x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4, x8). Dynamic ODT has a special use case: when DDR3 devices are architect for use in a single rank memory array, the ODT ball can be wired high rather than routed. Refer to the Dynamic ODT Special Use Case section. A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: Connect UDQS to ground via 1k * resistor. Connect UDQS# to V DD via 1k * resistor. Connect UDM to V DD via 1k * resistor. Connect DQ[15:8] individually to either V SS, V DD, or V REF via 1k resistors,* or float DQ[15:8]. *If ODT is used, 1k resistor should be changed to 4x that of the selected ODT. 13

14 Functional Block Diagrams 1Gb: x8, x16 Automotive DDR3 SDRAM Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 128 Meg x 8 Functional Block Diagram ODT ODT control ZQ RZQ RESET# E V SSQ A12 Control logic ZQCL, ZQCS ZQ CAL To ODT/output drivers, # CS# RAS# CAS# WE# Command decode Mode registers 16 BC4 (burst chop) OTF Refresh counter 14 Rowaddress MUX Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 rowaddress latch and decoder 16,384 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 memory array (16,384 x 128 x 64) Columns 0, 1, and 2 READ 64 FIFO and data MUX 8, # DLL READ drivers V DDQ /2 R TT,nom R TT(WR) sw1 sw2 DQ8 DQ[7:0] DQS, DQS# (1... 8) TDQS# DQ[7:0] V DDQ /2 Sense amplifiers 8, BC4 OTF BC4 sw1 R TT,nom R TT(WR) sw2 A[13:0] BA[2:0] 17 Address register 3 3 Bank control logic I/O gating DM mask logic (128 x64) Column decoder 64 Data interface 8 Data WRITE drivers and input logic sw1 V DDQ /2 R TT,nom R TT(WR) sw2 (1, 2) DQS, DQS# 10 Columnaddress counter/ latch 7 3 Columns 0, 1, and 2 DM/TDQS (shared pin), # Column 2 (select upper or lower nibble for BC4) 14

15 Functional Block Diagrams Figure 4: 64 Meg x 16 Functional Block Diagram ODT ODT control ZQ RZQ RESET# E V SSQ A12 Control logic ZQCL, ZQCS ZQ CAL To ODT/output drivers, # CS# RAS# CAS# WE# Command decode Mode registers 16 BC4 (burst chop) OTF Refresh 13 counter Rowaddress MUX Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 rowaddress latch and decoder 8,192 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 memory array (8192 x 128 x 128) Column 0, 1, and 2 READ 128 FIFO and data MUX 16, # DLL READ drivers V DDQ /2 R TT,nom R TT(WR) sw1 sw2 ( ) DQ[15:0] LDQS, LDQS#, UDQS, UDQS# DQ[15:0] Sense amplifiers V DDQ /2 16, BC4 R TT,nom R TT(WR) BC4 sw1 sw2 A[12:0] BA[2:0] 16 Address register 3 3 Bank control logic I/O gating DM mask logic (128 x128) Column decoder OTF 128 Data interface 16 Data WRITE drivers and input logic V DDQ /2 R TT,nom sw1 (1... 4) R TT(WR) sw2 LDQS, LDQS# UDQS, UDQS# 10 Columnaddress counter/ latch 7 3 Columns 0, 1, and 2 (1, 2) LDM/UDM, # Column 2 (select upper or lower nibble for BC4) 15

16 Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 5: 78-Ball FBGA x8 (Top View) A B C D E F G H J K L M N V SS V SS V DDQ V SSQ V REFDQ NC ODT NC V SS V DD V SS V DD V SS V DD V SSQ DQ2 DQ6 V DDQ V SS V DD CS# BA0 A3 A5 A7 RESET# NC DQ0 DQS DQS# DQ4 RAS# CAS# WE# BA2 A0 A2 A9 A13 NF/TDQS# V SS DM/TDQS V SSQ DQ1 DQ3 V DD V SS DQ7 DQ5 V SS # V DD A10/AP ZQ NC V REFCA A12/BC# BA1 A1 A4 A11 A6 NC A8 V DD V DDQ V SSQ V SSQ V DDQ NC E NC V SS V DD V SS V DD V SS Note: 1. A comma separates the configuration; a slash defines a selectable function. Example: NF/TDQS# applies to the x8 configuration only selectable between NF or TDQS# via MRS (symbols are defined in Table 3). 16

17 Ball Assignments and Descriptions Figure 6: 96-Ball FBGA x16 (Top View) A V DDQ DQ13 DQ15 DQ12 V DDQ V SS B V SSQ V DD V SS UDQS# DQ14 V SSQ C V DDQ DQ11 DQ9 UDQS DQ10 V DDQ D V SSQ V DDQ UDM DQ8 V SSQ V DD E V SS V SSQ DQ0 LDM V SSQ V DDQ F V DDQ DQ2 LDQS DQ1 DQ3 V SSQ G V SSQ DQ6 LDQS# V DD V SS V SSQ H V REFDQ V DDQ DQ4 DQ7 DQ5 V DDQ J NC V SS RAS# V SS NC K ODT V DD CAS# # V DD E L NC CS# WE# A10/AP ZQ NC M N P R T V SS V DD V SS V DD V SS BA0 A3 A5 A7 RESET# BA2 A0 A2 A9 NC NC A12/BC# A1 A11 NC V REFCA BA1 A4 A6 A8 V SS V DD V SS V DD V SS 17

18 Ball Assignments and Descriptions Table 3: 78-Ball FBGA x8 Ball Descriptions Symbol Type Description A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/ BC#, A13 Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 64 (page 102). BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to V REFCA., # Input Clock: and # are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of and the negative edge of #. Output data strobe (DQS, DQS#) is referenced to the crossings of and #. E Input Clock enable: E enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking E LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). E is synchronous for power-down entry and exit and for self refresh entry. E is asynchronous for self refresh exit. Input buffers (excluding, #, E, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding E and RESET#) are disabled during SELF REFRESH. E is referenced to V REFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to V REFDQ. DM has an optional use as TDQS on the x8. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to V REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to V REFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V SS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 V DD and DC LOW 0.2 V DDQ. RESET# assertion and de-assertion are asynchronous. 18

19 Ball Assignments and Descriptions Table 3: 78-Ball FBGA x8 Ball Descriptions (Continued) Symbol Type Description DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to V REFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# Output Termination data strobe: When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. V DD Supply Power supply: 1.5V ±0.075V. V DDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. V REFCA Supply Reference voltage for control, command, and address: V REFCA must be maintained at all times (including self refresh) for proper device operation. V REFDQ Supply Reference voltage for data: V REFDQ must be maintained at all times (excluding self refresh) for proper device operation. V SS Supply Ground. V SSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to V SSQ. NC No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). NF No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. 19

20 Ball Assignments and Descriptions Table 4: 96-Ball FBGA x16 Ball Descriptions Symbol Type Description A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/BC# Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 64 (page 102). BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to V REFCA., # Input Clock: and # are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of and the negative edge of #. Output data strobe (DQS, DQS#) is referenced to the crossings of and #. E Input Clock enable: E enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking E LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). E is synchronous for power-down entry and exit and for self refresh entry. E is asynchronous for self refresh exit. Input buffers (excluding, #, E, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding E and RESET#) are disabled during SELF REFRESH. E is referenced to V REFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to V REFDQ. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to V REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to V REFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V SS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 V DD and DC LOW 0.2 V DDQ. RESET# assertion and de-assertion are asynchronous. 20

21 Ball Assignments and Descriptions Table 4: 96-Ball FBGA x16 Ball Descriptions (Continued) Symbol Type Description UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to V REFDQ. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 I/O I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to V REFDQ. Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to V REFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. V DD Supply Power supply: 1.5V ±0.075V. V DDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. V REFCA Supply Reference voltage for control, command, and address: V REFCA must be maintained at all times (including self refresh) for proper device operation. V REFDQ Supply Reference voltage for data: V REFDQ must be maintained at all times (excluding self refresh) for proper device operation. V SS Supply Ground. V SSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to V SSQ. NC No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 21

22 Package Dimensions Package Dimensions Figure 7: 78-Ball FBGA x8 (JP) Seating plane 0.8 ± A A 78X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. 8 ± A Ball A1 ID Ball A1 ID B C 0.8 TYP D E F 9.6 CTR G H 11.5 ±0.1 J K L M N 0.8 TYP 6.4 CTR 1.2 MAX 0.25 MIN Note: 1. All dimensions are in millimeters. 22

23 Package Dimensions Figure 8: 96-Ball FBGA x16 (JT) Seating plane 0.8 ± A A 96X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads A Ball A1 ID Ball A1 ID B C D E F G 12 CTR H J 14 ±0.15 K 0.8 TYP L M N P R T 0.8 TYP 6.4 CTR 8 ± MAX 0.25 MIN Note: 1. All dimensions are in millimeters. 23

24 Thermal Characteristics Thermal Characteristics Table 5: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature 40 to +85 C T C 1, 2, 3 Industrial 40 to +95 C T C 1, 2, 3, 4 Operating case temperature 40 to +85 C T C 1, 2, 3 Automotive 40 to +105 C T C 1, 2, 3, 4 Junction-to-case 78-ball JP 6.4 C/W JC 5 (TOP) 96-ball JT 6.4 Notes: 1. MAX operating case temperature. T C is measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum T C during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T C during operation. 4. If T C exceeds 85 C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs interval refresh rate. The use of SRT or ASR (if available) must be enabled. 5. The thermal resistance data is based off of a number of samples from multiple lots and should be viewed as a typical number. Figure 9: Thermal Measurement Point 24

25 Electrical Specifications I DD Specifications and Conditions Electrical Specifications I DD Specifications and Conditions Within the following I DD measurement tables, the following definitions and conditions are used, unless stated otherwise: LOW: V IN V IL(AC)max ; HIGH: V IN V IH(AC)min. Midlevel: Inputs are V REF = V DD /2. R ON set to RZQ/7 (34 R TT,nom set to RZQ/6 (40 R TT(WR) set to RZQ/2 (120 Q OFF is enabled in MR1. ODT is enabled in MR1 (R TT,nom ) and MR2 (R TT(WR) ). TDQS is disabled in MR1. External DQ/DQS/DM load resister is 25 to V DDQ /2. Burst lengths are BL8 fixed. AL equals 0 (except in I DD7 ). I DD specifications are tested after the device is properly initialized. Input slew rate is specified by AC parametric test conditions. Optional ASR is disabled. Read burst type uses nibble sequential (MR0[3] = 0). Loop patterns must be executed at least once before current measurements begin. Table 6: Timing Parameters Used for I DD Measurements Clock Units DDR3-800 DDR DDR DDR DDR I DD -25E E E E Parameter Unit t (MIN) I DD ns CL I DD t RCD (MIN) I DD t RC (MIN) I DD t RAS (MIN) I DD t RP (MIN) t FAW x4, x x t RRD I DD x4, x x t RFC 1Gb Gb Gb

26 Electrical Specifications I DD Specifications and Conditions Table 7: I DD0 Measurement Loop, # Toggling E Static HIGH Sub- Loop Cycle Number Command CS# RAS# CAS# WE# 0 ACT D D D# D# Repeat cycles 1 through 4 until nras - 1; truncate if needed nras PRE Repeat cycles 1 through 4 until nrc - 1; truncate if needed nrc ACT F 0 nrc + 1 D F 0 nrc + 2 D F 0 nrc + 3 D# F 0 nrc + 4 D# F 0 Repeat cycles nrc + 1 through nrc + 4 until nrc nras -1; truncate if needed nrc + nras PRE F 0 Repeat cycles nrc + 1 through nrc + 4 until 2 RC - 1; truncate if needed 1 2 nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = 7 ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. Only selected bank (single) active. 26

27 Electrical Specifications I DD Specifications and Conditions Table 8: I DD1 Measurement Loop, # Toggling E Static HIGH Sub-Loop Cycle Number Command CS# RAS# CAS# WE# 0 ACT D D D# D# Repeat cycles 1 through 4 until nrcd - 1; truncate if needed nrcd RD Repeat cycles 1 through 4 until nras - 1; truncate if needed nras PRE Repeat cycles 1 through 4 until nrc - 1; truncate if needed nrc ACT F 0 nrc + 1 D F 0 nrc + 2 D F 0 nrc + 3 D# F 0 nrc + 4 D# F 0 Repeat cycles nrc + 1 through nrc + 4 until nrc + nrcd - 1; truncate if needed nrc + nrcd RD F Repeat cycles nrc + 1 through nrc + 4 until nrc + nras - 1; truncate if needed nrc + nras PRE F 0 Repeat cycle nrc + 1 through nrc + 4 until 2 nrc - 1; truncate if needed 1 2 nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = nrc Repeat sub-loop 0, use BA[2:0] = 7 ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data 2 Notes: 1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command. 2. DM is LOW. 3. Burst sequence is driven on each DQ signal by the RD command. 4. Only selected bank (single) active. 27

28 Electrical Specifications I DD Specifications and Conditions Table 9: I DD Measurement Conditions for Power-Down Currents Name I DD2P0 Precharge Power-Down Current (Slow Exit) 1 I DD2P1 Precharge Power-Down Current (Fast Exit) 1 I DD2Q Precharge Quiet Standby Current I DD3P Active Power-Down Current Timing pattern n/a n/a n/a n/a E LOW LOW HIGH LOW External clock Toggling Toggling Toggling Toggling t t (MIN) I DD t (MIN) I DD t (MIN) I DD t (MIN) I DD t RC n/a n/a n/a n/a t RAS n/a n/a n/a n/a t RCD n/a n/a n/a n/a t RRD n/a n/a n/a n/a t RC n/a n/a n/a n/a CL n/a n/a n/a n/a AL n/a n/a n/a n/a CS# HIGH HIGH HIGH HIGH Command inputs LOW LOW LOW LOW Row/column addr LOW LOW LOW LOW Bank addresses LOW LOW LOW LOW DM LOW LOW LOW LOW Data I/O Midlevel Midlevel Midlevel Midlevel Output buffer DQ, DQS Enabled Enabled Enabled Enabled ODT 2 Enabled, off Enabled, off Enabled, off Enabled, off Burst length Active banks None None None All Idle banks All All All None Special notes n/a n/a n/a n/a Notes: 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0). 2. Enabled, off means the MR bits are enabled, but the signal is LOW. 28

29 Electrical Specifications I DD Specifications and Conditions Table 10: I DD2N and I DD3N Measurement Loop, # Toggling E Static HIGH Sub-Loop Cycle Number Command CS# RAS# CAS# WE# 0 D D D# F 0 3 D# F Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = 7 ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. All banks closed during I DD2N ; all banks open during I DD3N. Table 11: I DD2NT Measurement Loop, # Toggling E Static HIGH Sub-Loop Cycle Number Command CS# RAS# CAS# WE# 0 D D D# F 0 3 D# F Repeat sub-loop 0, use BA[2:0] = 1; ODT = Repeat sub-loop 0, use BA[2:0] = 2; ODT = Repeat sub-loop 0, use BA[2:0] = 3; ODT = Repeat sub-loop 0, use BA[2:0] = 4; ODT = Repeat sub-loop 0, use BA[2:0] = 5; ODT = Repeat sub-loop 0, use BA[2:0] = 6; ODT = Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1 ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. All banks closed. 29

30 Electrical Specifications I DD Specifications and Conditions Table 12: I DD4R Measurement Loop, # Toggling E Static HIGH Sub-Loop Cycle Number Command CS# RAS# CAS# WE# 0 RD D D# D# RD F D F 0 6 D# F 0 7 D# F Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = 7 ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data 3 Notes: 1. DQ, DQS, DQS# are midlevel when not driving in burst sequence. 2. DM is LOW. 3. Burst sequence is driven on each DQ signal by the RD command. 4. All banks open. 30

31 Electrical Specifications I DD Specifications and Conditions Table 13: I DD4W Measurement Loop, # Toggling E Static HIGH Sub-Loop Cycle Number Command CS# RAS# CAS# WE# 0 WR D D# D# WR F D F 0 6 D# F 0 7 D# F Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = Repeat sub-loop 0, use BA[2:0] = 7 ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data 3 Notes: 1. DQ, DQS, DQS# are midlevel when not driving in burst sequence. 2. DM is LOW. 3. Burst sequence is driven on each DQ signal by the WR command. 4. All banks open. 31

32 Electrical Specifications I DD Specifications and Conditions Table 14: I DD5B Measurement Loop, # Toggling E Static HIGH Sub-Loop Cycle Number Command CS# RAS# CAS# WE# 0 0 REF D a 2 D D# F 0 4 D# F 0 1b 5 8 Repeat sub-loop 1a, use BA[2:0] = 1 1c 9 12 Repeat sub-loop 1a, use BA[2:0] = 2 1d Repeat sub-loop 1a, use BA[2:0] = 3 1e Repeat sub-loop 1a, use BA[2:0] = 4 1f Repeat sub-loop 1a, use BA[2:0] = 5 1g Repeat sub-loop 1a, use BA[2:0] = 6 1h Repeat sub-loop 1a, use BA[2:0] = nrfc - 1 Repeat sub-loop 1a through 1h until nrfc - 1; truncate if needed ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 32

33 Electrical Specifications I DD Specifications and Conditions Table 15: I DD Measurement Conditions for I DD6, I DD6ET, and I DD8 I DD Test I DD6 : Self Refresh Current Normal Temperature Range T C = 0 C to +85 C I DD6ET : Self Refresh Current Extended Temperature Range T C = 0 C to +95 C I DD8 : Reset 2 E LOW LOW Midlevel External clock Off, and # = LOW Off, and # = LOW Midlevel t n/a n/a n/a t RC n/a n/a n/a t RAS n/a n/a n/a t RCD n/a n/a n/a t RRD n/a n/a n/a t RC n/a n/a n/a CL n/a n/a n/a AL n/a n/a n/a CS# Midlevel Midlevel Midlevel Command inputs Midlevel Midlevel Midlevel Row/column addresses Midlevel Midlevel Midlevel Bank addresses Midlevel Midlevel Midlevel Data I/O Midlevel Midlevel Midlevel Output buffer DQ, DQS Enabled Enabled Midlevel ODT 1 Enabled, midlevel Enabled, midlevel Midlevel Burst length n/a n/a n/a Active banks n/a n/a None Idle banks n/a n/a All SRT Disabled (normal) Enabled (extended) n/a ASR Disabled Disabled n/a Notes: 1. Enabled, midlevel means the MR command is enabled, but the signal is midlevel. 2. During a cold boot RESET (initialization), current reading is valid after power is stable and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current reading is valid after RESET has been LOW for 200ns + t RFC. 33