RLDRAM 3. MT44K32M18 2 Meg x 18 x 16 Banks MT44K16M36 1 Meg x 36 x 16 Banks. Features. 576Mb: x18, x36 RLDRAM 3. Features.

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1 RLDRAM 3 MT44K32M8 2 Meg x 8 x 6 Banks MT44K6M36 Meg x 36 x 6 Banks 576Mb: x8, x36 RLDRAM 3 Features Features 66 MHz DDR operation 233 Mb/s/ball data rate 76.8 Gb/s peak bandwidth x36 at 66 MHz clock frequency Organization 32 Meg x 8, and 6 Meg x 36 common I/O CIO 6 banks.2v center-terminated push/pull I/O 2.5V V EXT,.35V V DD,.2V V DDQ I/O Reduced cycle time t RC MIN = 8-2ns SDR addressing Programmable READ/WRITE latency RL/WL and burst length Data mask for WRITE commands Differential input clocks CK, CK# Free-running differential input data clocks DKx, DKx# and output data clocks QKx, QKx# On-die DLL generates CK edge-aligned data and differential output data clock signals 64ms refresh 28K refresh per 64ms 68-ball FBGA package 4Ω or 6Ω matched impedance outputs Integrated on-die termination ODT Single or multibank writes Extended operating range 2 66 MHz READ training register Multiplexed and non-multiplexed addressing capabilities Mirror function Output driver and ODT calibration JTAG interface IEEE Options Marking Clock cycle and t RC timing.93ns and t RC MIN = 8ns -93E RL ns and t RC MIN = ns -93 RL ns and t RC MIN = 8ns -7E RL ns and t RC MIN = ns -7 RL ns and t RC MIN = 8ns -25F RL3-6.25ns and t RC MIN = ns -25E RL3-6.25ns and t RC MIN = 2ns RL Configuration 32 Meg x 8 32M8 6 Meg x 36 6M36 Operating temperature Commercial T C = to +95 C None Industrial T C = 4 C to +95 C IT Package 68-ball FBGA PA 2 68-ball FBGA Pb-free RB Revision :A Notes:. Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. 2. Consult factory. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 2 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

2 576Mb: x8, x36 RLDRAM 3 Features Figure : 576Mb RLDRAM 3 Part Numbers Example Part Number: MT44K6M36PA-93E MT44K Configuration Package Speed Temp - Configuration 32 Meg x 8 32M8 6 Meg x 36 6M36 Package 68-ball FBGA 68-ball FBGA Pb-free PA RB Temperature Commercial None Industrial IT Speed Grade -93E t CK =.93ns 8ns t RC -93 t CK =.93ns ns t RC -7E t CK =.7ns 8ns t RC -7 t CK =.7ns ns t RC -25F t CK =.25ns 8ns t RC -25E t CK =.25ns ns t RC -25 t CK =.25ns 2ns t RC BGA Part Marking Decoder Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Micron s BGA Part Marking Decoder is available on Micron s Web site at PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 2 2 Micron Technology, Inc. All rights reserved.

3 576Mb: x8, x36 RLDRAM 3 Features Contents General Description... 8 General Notes... 8 State Diagram... 9 Functional Block Diagrams... Ball Assignments and Descriptions... 2 Package Dimensions... 6 Electrical Characteristics I DD Specifications... 7 Electrical Specifications Absolute Ratings and I/O Capacitance... 2 Absolute Maximum Ratings... 2 Input/Output Capacitance... 2 AC and DC Operating Conditions AC Overshoot/Undershoot Specifications Slew Rate Definitions for Single-Ended Input Signals Slew Rate Definitions for Differential Input Signals ODT Characteristics... 3 ODT Resistors... 3 ODT Sensitivity Output Driver Impedance Output Driver Sensitivity Output Characteristics and Operating Conditions Reference Output Load Slew Rate Definitions for Single-Ended Output Signals... 4 Slew Rate Definitions for Differential Output Signals... 4 Speed Bin Tables AC Electrical Characteristics Temperature and Thermal Impedance Characteristics Command and Address Setup, Hold, and Derating... 5 Data Setup, Hold, and Derating Commands MODE REGISTER SET MRS Command Mode Register MR t RC Data Latency DLL Enable/Disable Address Multiplexing Mode Register MR Output Drive Impedance DQ On-Die Termination ODT DLL Reset ZQ Calibration ZQ Calibration Long... 7 ZQ Calibration Short... 7 AUTO REFRESH Protocol... 7 Burst Length BL... 7 Mode Register 2 MR READ Training Register RTR WRITE Protocol WRITE Command Multibank WRITE READ Command PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 3 2 Micron Technology, Inc. All rights reserved.

4 576Mb: x8, x36 RLDRAM 3 Features AUTO REFRESH Command INITIALIZATION Operation... 8 WRITE Operation READ Operation AUTO REFRESH Operation... 9 Multiplexed Address Mode Data Latency in Multiplexed Address Mode REFRESH Command in Multiplexed Address Mode Mirror Function... 2 RESET Operation... 2 IEEE 49. Serial Boundary Scan JTAG... 3 Disabling the JTAG Feature... 3 Test Access Port TAP... 3 TAP Controller... 4 Performing a TAP RESET... 6 TAP Registers... 6 TAP Instruction Set... 7 PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 4 2 Micron Technology, Inc. All rights reserved.

5 576Mb: x8, x36 RLDRAM 3 Features List of Figures Figure : 576Mb RLDRAM 3 Part Numbers... 2 Figure 2: Simplified State Diagram... 9 Figure 3: 32 Meg x 8 Functional Block Diagram... Figure 4: 6 Meg x 36 Functional Block Diagram... Figure 5: 68-Ball FBGA... 6 Figure 6: Single-Ended Input Signal Figure 7: Overshoot Figure 8: Undershoot Figure 9: V IX for Differential Signals Figure : Single-Ended Requirements for Differential Signals Figure : Definition of Differential AC Swing and t DVAC Figure 2: Nominal Slew Rate Definition for Single-Ended Input Signals Figure 3: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# Figure 4: ODT Levels and I-V Characteristics... 3 Figure 5: Output Driver Figure 6: DQ Output Signal Figure 7: Differential Output Signal Figure 8: Reference Output Load for AC Timing and Output Slew Rate Figure 9: Nominal Slew Rate Definition for Single-Ended Output Signals... 4 Figure 2: Nominal Differential Output Slew Rate Definition for QKx, QKx#... 4 Figure 2: Example Temperature Test Point Location... 5 Figure 22: Nominal Slew Rate and t VAC for t IS Command and Address - Clock Figure 23: Nominal Slew Rate for t IH Command and Address - Clock Figure 24: Tangent Line for t IS Command and Address - Clock Figure 25: Tangent Line for t IH Command and Address - Clock Figure 26: Nominal Slew Rate and t VAC for t DS DQ - Strobe Figure 27: Nominal Slew Rate for t DH DQ - Strobe... 6 Figure 28: Tangent Line for t DS DQ - Strobe... 6 Figure 29: Tangent Line for t DH DQ - Strobe Figure 3: MRS Command Protocol Figure 3: MR Definition for Non-Multiplexed Address Mode Figure 32: MR Definition for Non-Multiplexed Address Mode Figure 33: ZQ Calibration Timing ZQCL and ZQCS... 7 Figure 34: Read Burst Lengths Figure 35: MR2 Definition for Non-Multiplexed Address Mode Figure 36: READ Training Function - Back-to-Back Readout Figure 37: WRITE Command Figure 38: READ Command Figure 39: Bank Address-Controlled AUTO REFRESH Command Figure 4: Multibank AUTO REFRESH Command Figure 4: Power-Up/Initialization Sequence... 8 Figure 42: WRITE Burst Figure 43: Consecutive WRITE Bursts Figure 44: WRITE-to-READ Figure 45: WRITE - DM Operation Figure 46: Consecutive Quad Bank WRITE Bursts Figure 47: Interleaved READ and Quad Bank WRITE Bursts Figure 48: Basic READ Burst Figure 49: Consecutive READ Bursts BL = Figure 5: Consecutive READ Bursts BL = PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 5 2 Micron Technology, Inc. All rights reserved.

6 576Mb: x8, x36 RLDRAM 3 Features Figure 5: READ-to-WRITE BL = Figure 52: Read Data Valid Window Figure 53: Bank Address-Controlled AUTO REFRESH Cycle... 9 Figure 54: Multibank AUTO REFRESH Cycle... 9 Figure 55: READ Burst with ODT... 9 Figure 56: READ-NOP-READ with ODT Figure 57: Command Description in Multiplexed Address Mode Figure 58: Power-Up/Initialization Sequence in Multiplexed Address Mode Figure 59: MR Definition for Multiplexed Address Mode Figure 6: MR Definition for Multiplexed Address Mode Figure 6: MR2 Definition for Multiplexed Address Mode Figure 62: Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing Figure 63: Multibank AUTO REFRESH Operation with Multiplexed Addressing Figure 64: Consecutive WRITE Bursts with Multiplexed Addressing Figure 65: WRITE-to-READ with Multiplexed Addressing... Figure 66: Consecutive READ Bursts with Multiplexed Addressing... Figure 67: READ-to-WRITE with Multiplexed Addressing... Figure 68: TAP Controller State Diagram... 5 Figure 69: TAP Controller Functional Block Diagram... 5 Figure 7: JTAG Operation - Loading Instruction Code and Shifting Out Data... 8 Figure 7: TAP Timing... 9 PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 6 2 Micron Technology, Inc. All rights reserved.

7 576Mb: x8, x36 RLDRAM 3 Features List of Tables Table : 32 Meg x 8 Ball Assignments 68-Ball FBGA Top View... 2 Table 2: 6 Meg x 36 Ball Assignments 68-Ball FBGA Top View... 3 Table 3: Ball Descriptions... 4 Table 4: I DD Operating Conditions and Maximum Limits... 7 Table 5: Absolute Maximum Ratings... 2 Table 6: Input/Output Capacitance... 2 Table 7: DC Electrical Characteristics and Operating Conditions Table 8: Input AC Logic Levels Table 9: Control and Address Balls Table : Clock, Data, Strobe, and Mask Balls Table : Differential Input Operating Conditions CK, CK# and DKx, DKx# Table 2: Allowed Time Before Ringback t DVAC for CK, CK#, DKx, and DKx# Table 3: Single-Ended Input Slew Rate Definition Table 4: Differential Input Slew Rate Definition Table 5: ODT DC Electrical Characteristics... 3 Table 6: R TT Effective Impedances... 3 Table 7: ODT Sensitivity Definition Table 8: ODT Temperature and Voltage Sensitivity Table 9: Driver Pull-Up and Pull-Down Impedance Calculations Table 2: Output Driver Sensitivity Definition Table 2: Output Driver Voltage and Temperature Sensitivity Table 22: Single-Ended Output Driver Characteristics Table 23: Differential Output Driver Characteristics Table 24: Single-Ended Output Slew Rate Definition... 4 Table 25: Differential Output Slew Rate Definition... 4 Table 26: RL3 233/866 Speed Bins Table 27: RL3 6 Speed Bins Table 28: AC Electrical Characteristics Table 29: Temperature Limits Table 3: Thermal Impedance Table 3: Command and Address Setup and Hold Values Referenced at V/ns AC/DC-Based... 5 Table 32: Derating Values for t IS/ t IH AC5/DC-Based Table 33: Minimum Required Time t VAC Above V IHAC or Below V ILAC for Valid Transition Table 34: Data Setup and Hold Values at V/ns DKx, DKx# at 2V/ns AC/DC-Based Table 35: Derating Values for t DS/ t DH AC5/DC-Based Table 36: Minimum Required Time t VAC Above V IHAC or Below V ILAC for Valid Transition Table 37: Command Descriptions Table 38: Command Table Table 39: t RC_MRS values Table 4: Address Widths of Different Burst Lengths... 7 Table 4: Address Mapping in Multiplexed Address Mode Table 42: 32 Meg x 8 Ball Assignments with MF Ball Tied HIGH... 2 Table 43: TAP Input AC Logic Levels... 9 Table 44: TAP AC Electrical Characteristics... 9 Table 45: TAP DC Electrical Characteristics and Operating Conditions... Table 46: Identification Register Definitions... Table 47: Scan Register Sizes... Table 48: Instruction Codes... Table 49: Boundary Scan Exit... PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 7 2 Micron Technology, Inc. All rights reserved.

8 General Description 576Mb: x8, x36 RLDRAM 3 General Description The Micron RLDRAM 3 is a high-speed memory device designed for high-bandwidth data storage telecommunications, networking, cache applications, etc. The chip s 6- bank architecture is optimized for sustainable high-speed operation. The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output data is referenced to the READ strobes. Commands, addresses, and control signals are also registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data strobes. Read and write accesses to the RL3 device are burst-oriented. The burst length BL is programmable to 2, 4, or 8 by a setting in the mode register. The device is supplied with.35v for the core and.2v for the output drivers. The 2.5V supply is used for an internal supply. Bank-scheduled refresh is supported with the row address generated internally. The 68-ball FBGA package is used to enable ultra-high-speed data transfer rates. General Notes The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation. Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation. Nominal conditions are assumed for specifications not defined within the figures shown in this data sheet. Throughout this data sheet, the terms "RLDRAM," "DRAM, and "RLDRAM 3" are all used interchangeably and refer to the RLDRAM 3 SDRAM device. References to DQ, DK, QK, DM, and QVLD are to be interpeted as each group collectively, unless specifically stated otherwise. This includes true and complement signals of differential signals. Non-multiplexed operation is assumed if not specified as multiplexed. A X36 Device supplies four QK/QK# sets. One per 9 DQs. If a user only wants to use two QK/QK# sets, this is allowed. The user needs to use QK/QK# and QK/QK#. QK/QK# will control DQ[8:] & DQ[26:8]. QK/QK# will control DQ[7:9] & DQ[35:27]. The QK to DQ timing parameter to be used would be t QKQ2, t QKQ3. The unused QK/QK# pins should be left floating. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 8 2 Micron Technology, Inc. All rights reserved.

9 576Mb: x8, x36 RLDRAM 3 State Diagram State Diagram Figure 2: Simplified State Diagram Initialization sequence NOP WRITE READ RESET# MRS AREF Automatic sequence Command sequence PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 9 2 Micron Technology, Inc. All rights reserved.

10 PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 2 Micron Technology, Inc. All rights reserved. Functional Block Diagrams Figure 3: 32 Meg x 8 Functional Block Diagram RZQ CK CK# CS# REF# WE# MF RESET# A[9:] BA[3:] TCK TMS TDI ZQ 24 Command decode Address register Mode register JTAG Logic and Boundary Scan Register ODT control Control logic 24 Notes: ZQCL, ZQCS Refresh counter Rowaddress MUX 7 3 Bank control logic Columnaddress counter/ latch ZQ CAL Bank rowaddress latch and decoder ZQ CAL Bank Bank Bank memory array 892 x 32 x 8 x 8 2 SENSE AMPLIFIERS Sense amplifiers 892 I/O gating DQM mask logic 32 Column decoder Bank 5 Bank READ logic n n WRITE FIFO and drivers CLK in 8 8 DQ latch Input logic ODT control 8 QK/QK# generator ODT control 8 4 ODT control. Example for BL = 2; column address will be reduced with an increase in burst length = length of burst x 2^ number of column addresses to WRITE FIFO and READ logic ZQ CAL 4 RCVRS CK/CK# DLL READ Drivers V DDQ/2 R TT V DDQ/2 R TT V DDQ/2 R TT QVLD QK/QK#,QK/QK# DQ[7:] DK/DK#, DK/DK# DM[:] TDO 576Mb: x8, x36 RLDRAM 3 Functional Block Diagrams

11 PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 2 Micron Technology, Inc. All rights reserved. Functional Block Diagrams Figure 4: 6 Meg x 36 Functional Block Diagram RZQ CK CK# CS# REF# WE# MF RESET# A[8:] TCK TMS TDI ZQ 23 Command decode Address register Mode register JTAG Logic and Boundary Scan Register ODT control Control logic 23 Notes: ZQCL, ZQCS Refresh counter Rowaddress MUX 6 3 Bank control logic Columnaddress counter/ latch ZQ CAL Bank rowaddress latch and decoder ZQ CAL Bank Bank Bank memory array 892 x 32 x 4 x 36 2 SENSE AMPLIFIERS Sense amplifiers 892 I/O gating DQM mask logic 32 Column decoder Bank 5 Bank READ logic n n WRITE FIFO and drivers CLK in DQ latch Input logic ODT control 36 QK/QK# generator ODT control ODT control. Example for BL = 2; column address will be reduced with an increase in burst length = length of burst x 2^ number of column addresses to WRITE FIFO and READ logic ZQ CAL 8 CK/CK# DLL READ Drivers VDDQ/2 R TT RCVRS V DDQ/2 R TT VDDQ/2 R TT QVLD[:] QK/QK#, QK/QK# QK2/QK2#, QK3/QK3# DQ[35:] DK/DK#, DK/DK# DM[:] TDO 576Mb: x8, x36 RLDRAM 3 Functional Block Diagrams

12 576Mb: x8, x36 RLDRAM 3 Ball Assignments and Descriptions Ball Assignments and Descriptions Table : 32 Meg x 8 Ball Assignments 68-Ball FBGA Top View A V SS V DD NF V DDQ NF V REF DQ7 V DDQ DQ8 V DD V SS RESET# B V EXT V SS NF V SSQ NF V DDQ DM V DDQ DQ5 V SSQ DQ6 V SS V EXT C V DD NF V DDQ NF V SSQ NF DK# DQ2 V SSQ DQ3 V DDQ DQ4 V DD D A V SSQ NF V DDQ NF V SSQ DK V SSQ QK V DDQ DQ V SSQ A3 E V SS A V SSQ NF V DDQ NF MF QK# V DDQ DQ V SSQ CS# V SS F A7 NF CS/A2 V DD A2 A WE# ZQ REF# A3 A4 V DD A5 A9 G V 2 SSA2 A5 A6 V SS BA V SS CK# V SS BA V SS A8 A8 V 3 SS RFU H A9 V DD A4 A6 V DD BA3 CK BA2 V DD A7 A2 V DD A J V DDQ NF V SSQ NF V DDQ NF V SS QK# V DDQ DQ9 V SSQ QVLD V DDQ K NF V SSQ NF V DDQ NF V SSQ DK V SSQ QK V DDQ DQ V SSQ DQ L V DD NF V DDQ NF V SSQ NF DK# DQ2 V SSQ DQ3 V DDQ DQ4 V DD M V EXT V SS NF V SSQ NF V DDQ DM V DDQ DQ5 V SSQ DQ6 V SS V EXT N V SS TCK V DD TDO V DDQ NF V REF DQ7 V DDQ TDI V DD TMS V SS Notes:. F2 is an NF ball for both the X8 & X36 576Mb devices, but is also the Location of CS to support the Gb x8 DDP device. This same ball has been designated as the location of A2 for the future 2Gb monolithic device. F2 is Internally connected so it can mirror the A5 address signal when MF is asserted HIGH and has parasitic characteristics of an address pin. 2. G is a VSS ball for the 576Mb device, but has been designated as the location of A2 for the future X8 2Gb monolithic device. 3. G3 is a VSS ball for both X8 & X36 576Mb devices, but has been reserved for future use RFU on the Gb & 2Gb monolithic devices and will have parasitic characteristics of an address. 4. NF balls for the x8 configuration are internally connected and have parasitic characteristics of an I/O. Balls may be connected to V SSQ. 5. MF is assumed to be tied LOW for this ball assignment. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 2 2 Micron Technology, Inc. All rights reserved.

13 576Mb: x8, x36 RLDRAM 3 Ball Assignments and Descriptions Table 2: 6 Meg x 36 Ball Assignments 68-Ball FBGA Top View A V SS V DD DQ26 V DDQ DQ25 V REF DQ7 V DDQ DQ8 V DD V SS RESET# B V EXT V SS DQ24 V SSQ DQ23 V DDQ DM V DDQ DQ5 V SSQ DQ6 V SS V EXT C V DD DQ22 V DDQ DQ2 V SSQ DQ2 DK# DQ2 V SSQ DQ3 V DDQ DQ4 V DD D A V SSQ DQ8 V DDQ QK2 V SSQ DK V SSQ QK V DDQ DQ V SSQ A3 E V SS A V SSQ DQ9 V DDQ QK2# MF QK# V DDQ DQ V SSQ CS# V SS F A7 NF CS/A2 V DD A2 A WE# ZQ REF# A3 A4 V DD A5 A9 G V 2 SSNF A5 A6 V SS BA V SS CK# V SS BA V SS A8 A8 V 3 SS RFU H NF 4 A9 V DD A4 A6 V DD BA3 CK BA2 V DD A7 A2 V DD A J V DDQ QVLD V SSQ DQ27 V DDQ QK3# V SS QK# V DDQ DQ9 V SSQ QVLD V DDQ K DQ29 V SSQ DQ28 V DDQ QK3 V SSQ DK V SSQ QK V DDQ DQ V SSQ DQ L V DD DQ32 V DDQ DQ3 V SSQ DQ3 DK# DQ2 V SSQ DQ3 V DDQ DQ4 V DD M V EXT V SS DQ34 V SSQ DQ33 V DDQ DM V DDQ DQ5 V SSQ DQ6 V SS V EXT N V SS TCK V DD TDO V DDQ DQ35 V REF DQ7 V DDQ TDI V DD TMS V SS Notes:. F2 is an NF ball for both the X8 & X36 576Mb devices, but is also the Location of CS to support the Gb x8 DDP device. This same ball has been designated as the location of A2 for the future 2Gb monolithic device. F2 is Internally connected so it can mirror the A5 address signal when MF is asserted HIGH and has parasitic characteristics of an address pin. 2. G is a VSS ball for this 576Mb device, but will be an NF ball for the future X36 2Gb monolithic device. The NF ball A2 for X8 2Gb device will have parasitic characteristics of an address. 3. G3 is a VSS ball for both X8 & X36 576Mb devices, but has been reserved for future use RFU on the Gb & 2Gb monolithic devices and will have parasitic characteristics of an address. 4. NF ball for x36 configuration is internally connected and has parasitic characteristics of an address A9 for x8 configuration. Ball may be connected to V SSQ. 5. MF is assumed to be tied LOW for this ball assignment. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 3 2 Micron Technology, Inc. All rights reserved.

14 576Mb: x8, x36 RLDRAM 3 Ball Assignments and Descriptions Table 3: Ball Descriptions Symbol Type Description A[9:] Input Address inputs: A[9:] define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings along with BA[3:]. They are sampled at the rising edge of CK. BA[3:] Input Bank address inputs: Select the internal bank to which a command is being applied. CK/CK# Input Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CS# Input Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the command decoder is disabled, new commands are ignored, but internal operations continue. DQ[35:] I/O Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is referenced to both edges of QK. During WRITE commands, the data is sampled at both edges of DK. DKx, DKx# Input Input data clock: DKx and DKx# are differential input data clocks. All input data is referenced to both edges of DKx. For the x36 device, DQ[8:] and DQ[26:8] are referenced to DK and DK#, and DQ[7:9] and DQ[35:27] are referenced to DK and DK#. For the x8 device, DQ[8:] are referenced to DK and DK#, and DQ[7:9] are referenced to DK and DK#. DKx and DKx# are free-running signals and must always be supplied to the device. DM[:] Input Input data mask: DM is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH. DM is used to mask the lower byte for the x8 device and DQ[8:] and DQ[26:8] for the x36 device. DM is used to mask the upper byte for the x8 device and DQ[7:9] and DQ[35:27] for the x36 device. Tie DM[:] to V SS if not used. TCK Input IEEE 49. clock input: This ball must be tied to V SS if the JTAG function is not used. TMS, TDI Input IEEE 49. test inputs: These balls may be left as no connects if the JTAG function is not used. WE#, REF# Input Command inputs: Sampled at the positive edge of CK, WE# and REF# together with CS# define the command to be executed. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V SS. RESET# assertion and deassertion are asynchronous. RESET# is a CMOS input defined with DC HIGH.8 x V DD and DC LOW.2 x V DDQ. ZQ Input External impedance: This signal is used to tune the device s output impedance and ODT. RZQ needs to be 24Ω, where RZQ is a resistor from this signal to ground. QKx, QKx# Output Output data clocks: QK and QK# are opposite-polarity output data clocks. They are free-running signals and during READ commands are edge-aligned with the DQs. For the x36 device, QK, QK# align with DQ[8:]; QK, QK# align with DQ[7:9]; QK2, QK2# align with DQ[26:8]; QK3, QK3# align with DQ[35:27]. For the x8 device, QK, QK# align with DQ[8:]; QK, QK# align with DQ[7:9]. QVLDx Output Data valid: The QVLD ball indicates that valid output data will be available on the subsequent rising clock edge. There is a single QVLD ball for the x8 device and two, QVLD and QVLD, for the x36 device. QVLD aligns with DQ[7:]; QVLD aligns with DQ[35:8]. MF Input Mirror function: The mirror function ball is a DC input used to create mirrored ballouts for simple dual-loaded clamshell mounting. If the ball is tied to V SS, the address and command balls are in their true layout. If the ball is tied to V DDQ, they are in the complement location. MF must be tied HIGH or LOW and cannot be left floating. MF is a CMOS input defined with DC HIGH.8 x V DD and DC LOW.2 x V DDQ. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 4 2 Micron Technology, Inc. All rights reserved.

15 576Mb: x8, x36 RLDRAM 3 Ball Assignments and Descriptions Table 3: Ball Descriptions Continued Symbol Type Description TDO Output IEEE 49. test output: JTAG output. This ball may be left as no connect if the JTAG function is not used. V DD Supply Power supply:.35v nominal. See Table 7 page 22 for range. V DDQ Supply DQ power supply:.2v nominal. Isolated on the device for improved noise immunity. See Table 7 page 22 for range. V EXT Supply Power supply: 2.5V nominal. See Table 7 page 22 for range. V REF Supply Input reference voltage: V DDQ /2 nominal. Provides a reference voltage for the input buffers. V SS Supply Ground. V SSQ Supply DQ ground: Isolated on the device for improved noise immunity. NC No connect: These balls are not connected to the DRAM. NF No function: These balls are connected to the DRAM, but provide no functionality. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 5 2 Micron Technology, Inc. All rights reserved.

16 576Mb: x8, x36 RLDRAM 3 Package Dimensions Package Dimensions Figure 5: 68-Ball FBGA Seating plane A.2 A 68X Ø.55 Dimensions apply to solder balls postreflow on Ø.4 NSMD ball pads Ball A ID Ball A ID A B C 3.5 ±. 2 CTR TYP D E F G H J K L M N TYP 2 CTR 3.5 ±.. ±..325 MIN Note:. All dimensions are in millimeters. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 6 2 Micron Technology, Inc. All rights reserved.

17 PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 7 2 Micron Technology, Inc. All rights reserved. Electrical Characteristics I DD Specifications Table 4: I DD Operating Conditions and Maximum Limits Notes 6 apply to the entire table Description Condition Symbol -93E -93-7E -7-25F -25E -25 Units Notes Standby current Clock active standby current Operational current: BL2 Operational current: BL4 Operational current: BL8 Burst refresh current t CK = idle; All banks idle; No inputs toggling CS# = ; No commands; Bank address incremented and half address/ data change once every four clock cycles BL = 2; Sequential bank access; Bank transitions once every t RC; Half address transitions once every t RC; Read followed by write sequence; Continuous data during WRITE commands BL = 4; Sequential bank access; Bank transitions once every t RC; Half address transitions once every t RC; Read followed by write sequence; Continuous data during WRITE commands BL = 8; Sequential bank access; Bank transitions once every t RC; Half address transitions once every t RC; Read followed by write sequence; Continuous data during WRITE commands Sixteen bank cyclic refresh using Bank Address Control AREF protocol; Command bus remains in refresh for all sixteen banks; DQs are High-Z and at V DDQ /2; Addresses are at V DDQ /2 I SB V DD x ma 7 I SB V DD x I SB V EXT I SB2 V DD x ma I SB2 V DD x I SB2 V EXT I DD V DD x ma I DD V DD x I DD V EXT I DD2 V DD x ma I DD2 V DD x I DD2 V EXT I DD3 V DD x ma I DD3 V DD x36 NA NA NA NA N/A NA NA I DD3 V EXT I REF V DD x ma I REF V DD x I REF V EXT Mb: x8, x36 RLDRAM 3 Electrical Characteristics I DD Specifications

18 PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 8 2 Micron Technology, Inc. All rights reserved. Table 4: I DD Operating Conditions and Maximum Limits Continued Notes 6 apply to the entire table Description Condition Symbol -93E -93-7E -7-25F -25E -25 Units Notes Distributed refresh current Multibank refresh current: 4 bank refresh Operating burst write current : BL2 Operating burst write current : BL4 Operating burst write current :BL8 Multibank write current: Dual bank write Multibank write current: Quad bank write Single bank refresh using Bank Address Control AREF protocol; Sequential bank access every.489μs; DQs are High-Z and at V DDQ /2; Addresses are at V DDQ /2 Quad bank refresh using Multibank AREF protocol; BL = 4; Cyclic bank access; Subject to t SAW and t MMD specifications; DQs are High-Z and at V DDQ /2; Bank addresses are at V DDQ /2 BL = 2; Cyclic bank access; Half of address bits change every clock cycle; Continuous data; Measurement is taken during continuous WRITE BL = 4; Cyclic bank access; Half of address bits change every two clock cycles; Continuous data; Measurement is taken during continuous WRITE BL = 8; Cyclic bank access; Half of address bits change every four clock cycles; Continuous data; Measurement is taken during continuous WRITE BL = 4; Cyclic bank access using Dual Bank WRITE; Half of address bits change every two clock cycles; Continuous data; Measurement is taken during continuous WRITE BL = 4; Cyclic bank access using Quad Bank WRITE; Half of address bits change every two clock cycles; Continuous data; Measurement is taken during continuous WRITE; Subject to t SAW specification I REF2 V DD x ma I REF2 V DD x I REF2 V EXT I MBREF4 V DD x ma I MBREF4 V DD x I MBREF4 V EXT I DD2W V DD x ma I DD2W V DD x I DD2W V EXT I DD4W V DD x ma I DD4W V DD x I DD4W V EXT I DD8W V DD x ma I DD8W V DD x36 NA NA NA NA NA NA NA I DD8W V EXT I DBWR V DD x ma I DBWR V DD x I DBWR V EXT I QBWR V DD x ma I QBWR V DD x I QBWR V EXT Mb: x8, x36 RLDRAM 3 Electrical Characteristics I DD Specifications

19 PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 9 2 Micron Technology, Inc. All rights reserved. Table 4: I DD Operating Conditions and Maximum Limits Continued Notes 6 apply to the entire table Description Condition Symbol -93E -93-7E -7-25F -25E -25 Units Notes Operating burst read current example Operating burst read current example Operating burst read current example BL = 2; Cyclic bank access; Half of address bits change every clock cycle; Continuous data; Measurement is taken during continuous READ BL = 4; Cyclic bank access; Half of address bits change every two clock cycles; Continuous data; Measurement is taken during continuous READ BL = 8; Cyclic bank access; Half of address bits change every four clock cycles; Continuous data; Measurement is taken during continuous READ I DD2R V DD x ma I DD2R V DD x I DD2R V EXT I DD4R V DD x ma I DD4R V DD x I DD4R V EXT I DD8R V DD x ma I DD8R V DD x36 NA NA NA NA NA NA NA I DD8R V EXT Mb: x8, x36 RLDRAM 3 Electrical Characteristics I DD Specifications

20 576Mb: x8, x36 RLDRAM 3 Electrical Characteristics I DD Specifications Notes:. I DD specifications are tested after the device is properly initialized. C T C +95 C; +.28V V DD +.42V,+.4V V DDQ +.26V,+2.38V V EXT +2.63V,V REF = V DDQ /2. 2. I DD mesurements use t CK MIN, t RC MIN, and minimum data latency RL and WL. 3. Input slew rate is V/ns for single ended signals and 2V/ns for differential signals. 4. Definitions for I DD conditions: LOW is defined as V IN V ILACMAX. HIGH is defined as V IN V IHACMIN. Continuous data is defined as half the DQ signals changing between HIGH and LOW every half clock cycle twice per clock. Continuous address is defined as half the address signals changing between HIGH and LOW every clock cycle once per clock. Sequential bank access is defined as the bank address incrementing by one every t RC. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for BL = 8 this is every fourth clock. 5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle. 6. I DD parameters are specified with ODT disabled. 7. Upon exiting standby current conditions, at least one NOP command must be issued with stable clock prior to issuing any other valid command. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 2 2 Micron Technology, Inc. All rights reserved.

21 Electrical Specifications Absolute Ratings and I/O Capacitance Absolute Maximum Ratings Table 5: Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD V DD supply voltage relative to V SS V V DDQ Voltage on V DDQ supply relative to V SS.4.66 V V IN,V OUT Voltage on any ball relative to V SS.4.66 V V EXT Voltage on V EXT supply relative to V SS V Input/Output Capacitance 576Mb: x8, x36 RLDRAM 3 Electrical Specifications Absolute Ratings and I/O Capacitance Table 6: Input/Output Capacitance Notes and 2 apply to entire table Capacitance Parameters Symbol RL3-233 RL3-866 RL3-6 Min Max Min Max Min Max CK/CK# C CK pf ΔC: CK to CK# C DCK pf Single-ended I/O: DQ, DM C IO pf 3 Input strobe: DK/DK# C IO pf Output strobe: QK/QK#, QVLD C IO pf ΔC: DK to DK# C DDK pf ΔC: QK to QK# C DQK pf ΔC: DQ to QK or DQ to DK C DIO pf 4 Inputs CMD, ADDR C I pf 5 ΔC: CMD_ADDR to CK C DI_CMD_ADDR pf 6 JTAG balls C JTAG pf 7 RESET#, MF balls C I pf Units Notes Notes:. +.28V V DD +.42V, +.4V V DDQ.26V, +2.38V V EXT +2.63V, V REF = V SS, f = MHz, T C = 25 C, V OUTDC =.5 V DDQ, V OUT peak-to-peak =.V. 2. Capacitance is not tested on ZQ ball. 3. DM input is grouped with the I/O balls, because they are matched in loading. 4. C DIO = C IODQ -.5 C IO [QK] + C IO [QK#]. 5. Includes CS#, REF#, WE#, A[9:], and BA[3:]. 6. C DI_CMD_ADDR = C I CMD_ADDR -.5 C CK [CK] + C CK [CK#]. 7. JTAG balls are tested at 5 MHz. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 2 2 Micron Technology, Inc. All rights reserved.

22 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions AC and DC Operating Conditions Table 7: DC Electrical Characteristics and Operating Conditions Note applies to the entire table; Unless otherwise noted: C T C +95 C; +.28V V DD +.42V Description Symbol Min Max Units Notes Supply voltage V EXT V Supply voltage V DD V Isolated output buffer supply V DDQ.4.26 V Reference voltage V REF.49 V DDQ.5 V DDQ V 2, 3 Input HIGH logic voltage V IHDC V REF +. V DDQ V Input LOW logic voltage V ILDC V SS V REF -. V Input leakage current: Any input V V IN V DD, V REF ball V V IN.V All other balls not under test = V Reference voltage current All other balls not under test = V I LI 2 2 µa I REF 5 5 µa Notes:. All voltages referenced to V SS GND. 2. The nominal value of V REF is expected to be.5 V DDQ of the transmitting device. V REF is expected to track variations in V DDQ. 3. Peak-to-peak noise non-common mode on V REF may not exceed ±2% of the DC value. DC values are determined to be less than 2 MHz. Peak-to-peak AC noise on V REF should not exceed ±2% of V REFDC. Thus, from V DDQ /2, V REF is allowed ±2% V DDQ /2 for DC error and an additional ±2% V DDQ /2 for AC noise. The measurement is to be taken at the nearest V REF bypass capacitor. Table 8: Input AC Logic Levels Notes -3 apply to entire table; Unless otherwise noted: C T C +95 C; +.28V V DD +.42V Description Symbol Min Max Units Input HIGH logic voltage V IHAC V REF +.5 V Input LOW logic voltage V ILAC V REF -.5 V Notes:. All voltages referenced to V SS GND. 2. The receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above/below the DC input LOW/HIGH level. 3. Single-ended input slew rate = V/ns; maximum input voltage swing under test is 9mV peak-to-peak. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 22 2 Micron Technology, Inc. All rights reserved.

23 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions Figure 6: Single-Ended Input Signal.6V V IL and V IH levels with ringback V DDQ +.4V narrow pulse width.2v V DDQ Minimum V IL and V IH levels.75v V IHAC.75V V IHAC.7V V IHDC.7V V IHDC.624V.62V.6V.588V.576V.624V.62V.6V.588V.576V V REF + AC noise V REF + DC error V REF - DC error V REF - AC noise.5v V ILDC.5V V ILDC.45V V ILAC.45V V ILAC.V V SS.4V V SS -.4V narrow pulse width PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 23 2 Micron Technology, Inc. All rights reserved.

24 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions AC Overshoot/Undershoot Specifications Table 9: Control and Address Balls Parameter RL3-233 RL3-866 RL3-6 Maximum peak amplitude allowed for overshoot area.4v.4v.4v Maximum peak amplitude allowed for undershoot area.4v.4v.4v Maximum overshoot area above V DDQ.25 Vns.28 Vns.33 Vns Maximum undershoot area below V SS /V SSQ.25 Vns.28 Vns.33 Vns Table : Clock, Data, Strobe, and Mask Balls Parameter RL3-233 RL3-866 RL3-6 Maximum peak amplitude allowed for overshoot area.4v.4v.4v Maximum peak amplitude allowed for undershoot area.4v.4v.4v Maximum overshoot area above V DDQ. Vns. Vns.3 Vns Maximum undershoot area below V SS /V SSQ. Vns. Vns.3 Vns Figure 7: Overshoot Volts V Maximum amplitude Overshoot area V DDQ Time ns Figure 8: Undershoot V SS /V SSQ Volts V Maximum amplitude Time ns Undershoot area PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 24 2 Micron Technology, Inc. All rights reserved.

25 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions Table : Differential Input Operating Conditions CK, CK# and DKx, DKx# Notes and 2 apply to entire table Parameter/Condition Symbol Min Max Units Notes Differential input voltage logic HIGH slew V IH,diff_slew +2 n/a mv 3 Differential input voltage logic LOW slew V IL,diff_slew n/a -2 mv 3 Differential input voltage logic HIGH V IH,diffAC 2 V IHAC - V REF V DDQ mv 4 Differential input voltage logic LOW V IL,diffAC V SSQ 2 V ILAC - V REF mv 5 Differential input crossing voltage relative to V DD /2 V IX V REFDC - 5 V REFDC + 5 mv 6 Single-ended HIGH level V SEH V IHAC V DDQ mv 4 Single-ended LOW level V SEL V SSQ V ILAC mv 5 Notes:. CK/CK# and DKx/DKx# are referenced to V DDQ and V SSQ. 2. Differential input slew rate = 2 V/ns. 3. Defines slew rate reference points, relative to input crossing voltages. 4. Maximum limit is relative to single-ended signals; overshoot specifications are applicable. 5. Minimum limit is relative to single-ended signals; undershoot specifications are applicable. 6. The typical value of V IX is expected to be about.5 V DDQ of the transmitting device and V IX is expected to track variations in V DDQ. V IX indicates the voltage at which differential input signals must cross. Figure 9: V IX for Differential Signals V DDQ V DDQ CK#, DKx# CK#, DKx# X V IX V IX V DDQ /2 X X V DDQ /2 V IX X V IX CK, DKx CK, DKx V SSQ V SSQ PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 25 2 Micron Technology, Inc. All rights reserved.

26 Figure : Single-Ended Requirements for Differential Signals 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions V DDQ V SEH,min V DDQ /2 V SEH CK or DKx V SEL,max V SS V SEL Figure : Definition of Differential AC Swing and t DVAC t DVAC V IH,diffACmin V IH,diff_slew,min. CK - CK# DKx - DKx# V IL,diff_slew,max V IL,diffACmax half cycle t DVAC PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 26 2 Micron Technology, Inc. All rights reserved.

27 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions Table 2: Allowed Time Before Ringback t DVAC for CK, CK#, DKx, and DKx# Slew Rate V/ns MIN t DVAC ps at V IH /V IL,diffAC > <. 5 Slew Rate Definitions for Single-Ended Input Signals Setup t IS and t DS nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF and the first crossing of V IHACmin. Setup t IS and t DS nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF and the first crossing of V ILACmax. Hold t IH and t DH nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V ILDCmax and the first crossing of V REF. Hold t IH and t DH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IHDCmin and the first crossing of V REF see Figure 2 page 28. Table 3: Single-Ended Input Slew Rate Definition Input Slew Rates Linear Signals Measured Input Edge From To Calculation Setup Rising V REF V IHACmin [V IHACmin - V REF ]/ΔTRS Falling V REF V ILACmax [V REF - V ILACmax ]/ΔTFS Hold Rising V ILDCmax V REF [V REF - V ILDCmax ]/ΔTRH Falling V IHDCmin V REF [V IHDCmin - V REF ]/ΔTFH PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 27 2 Micron Technology, Inc. All rights reserved.

28 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions Figure 2: Nominal Slew Rate Definition for Single-Ended Input Signals ΔTRS Setup V IHACmin Single-ended input voltage DQ, CMD, ADDR V IHDCmin V REF V ILDCmax V ILACmax ΔTFS ΔTRH Hold V IHACmin Single-ended input voltage DQ, CMD, ADDR V IHDCmin V REF V ILDCmax V ILACmax ΔTFH PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 28 2 Micron Technology, Inc. All rights reserved.

29 Slew Rate Definitions for Differential Input Signals 576Mb: x8, x36 RLDRAM 3 AC and DC Operating Conditions Input slew rate for differential signals CK, CK# and DKx, DKx# are defined and measured as shown in the following two tables. The nominal slew rate for a rising signal is defined as the slew rate between V IL,diff,max and V IH,diff,min. The nominal slew rate for a falling signal is defined as the slew rate between V IH,diff,min and V IL,diff,max. Table 4: Differential Input Slew Rate Definition Differential Input Slew Rates Linear Signals Measured Input Edge From To CK and DK reference Calculation Rising V IL,diff_slew,max V IH,diff_slew,min [V IH,diff_slew,min - V IL,diff_slew,max ]/ΔTR diff Falling V IH,diff_slew,min V IL,diff_slew,max [V IH,diff_slew,min - V IL,diff_slew,max ]/ΔTF diff Figure 3: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# ΔTR diff Differential input voltage CK, CK#; DKx, DKx# V IH,diff_slew,min V IL,diff_slew,max ΔTF diff PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 29 2 Micron Technology, Inc. All rights reserved.

30 576Mb: x8, x36 RLDRAM 3 ODT Characteristics ODT Characteristics Figure 4: ODT Levels and I-V Characteristics ODT effective resistance, R TT, is defined by MR[4:2]. ODT is applied to the DQ, DM, and DKx, DKx# balls. The individual pull-up and pull-down resistors R TTPU and R TTPD are defined as follows: R TTPU =V DDQ - V OUT / I OUT, under the condition that R TTPD is turned off R TTPD = V OUT / I OUT, under the condition that R TTPU is turned off Chip in termination mode I PU ODT V DDQ To other circuitry such as RCV,... R TTPU R TTPD I PD I OUT = I PD - I PU DQ I OUT VOUT V SSQ Table 5: ODT DC Electrical Characteristics Parameter/Condition Symbol Min Nom Max Units Notes R TT effective impedance from V ILAC to V IHAC R TT_EFF See Table 6 page 3., 2 Deviation of V M with respect to V DDQ /2 ΔVm % 3 Notes:. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage. Refer to ODT Sensitivity page 32 if either the temperature or voltage changes after calibration. 2. Measurement definition for R TT : Apply V IHAC to ball under test and measure current I[V IHAC ], then apply V ILAC to ball under test and measure current I[V ILAC ]: R TT = V IHAC - V ILAC I[V IHAC ] - I[V ILAC ] 3. Measure voltage V M at the tested ball with no load: 2 VM ΔVM = - V DDQ ODT Resistors The on-die termination resistance is selected by MR[4:2]. The following table provides an overview of the ODT DC electrical characteristics. The values provided are not speci- PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 3 2 Micron Technology, Inc. All rights reserved.

31 Table 6: R TT Effective Impedances fication requirements; however, they can be used as design guidelines to indicate what R TT is targeted to provide: R TT 2Ω is made up of R TT2PD24 and R TT2PU24. R TT 6Ω is made up of R TT6PD2 and R TT6PU2. R TT 4Ω is made up of R TT4PD8 and R TT4PU8. R TT Resistor V OUT Min Nom Max Units 2Ω R TT2PD24.2 x V DDQ.6.. RZQ/ 2Ω.5 x V DDQ.9.. RZQ/.8 x V DDQ.9..4 RZQ/ R TT2PU24.2 x V DDQ.9..4 RZQ/.5 x V DDQ.9.. RZQ/.8 x V DDQ.6.. RZQ/ V ILAC to.9..6 RZQ/2 V IHAC 6Ω R TT6PD2.2 x V DDQ.6.. RZQ/2 6Ω.5 x V DDQ.9.. RZQ/2.8 x V DDQ.9..4 RZQ/2 R TT6PU2.2 x V DDQ.9..4 RZQ/2.5 x V DDQ.9.. RZQ/2.8 x V DDQ.6.. RZQ/2 V ILAC to.9..6 RZQ/4 V IHAC 4Ω R TT4PD8.2 x V DDQ.6.. RZQ/3 4Ω 576Mb: x8, x36 RLDRAM 3 ODT Characteristics.5 x V DDQ.9.. RZQ/3.8 x V DDQ.9..4 RZQ/3 R TT4PU8.2 x V DDQ.9..4 RZQ/3.5 x V DDQ.9.. RZQ/3.8 x V DDQ.6.. RZQ/3 V ILAC to.9..6 RZQ/6 V IHAC PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 3 2 Micron Technology, Inc. All rights reserved.

32 576Mb: x8, x36 RLDRAM 3 ODT Characteristics ODT Sensitivity If either temperature or voltage changes after I/O calibration, then the tolerance limits listed in Table 5 page 3 and Table 6 page 3 can be expected to widen according to Table 7 page 32 and Table 8 page 32. Table 7: ODT Sensitivity Definition Symbol Min Max Units R TT.9 - dr TT dt DT - dr TT dv DV.6 + dr TT dt DT + dr TT dv DV RZQ/2,4,6 Note:. DT = T - T@ calibration, DV = V DDQ - V calibration or V DD - V calibration. Table 8: ODT Temperature and Voltage Sensitivity Change Min Max Units dr TT dt.5 %/ C dr TT dv.5 %/mv PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 32 2 Micron Technology, Inc. All rights reserved.

33 Output Driver Impedance Figure 5: Output Driver The output driver impedance is selected by MR[:] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown below. The output driver impedance R ON is defined by the value of the external reference resistor RZQ as follows: R ON,x = RZQ/y with RZQ = 24Ω ±%; x = 4Ω or 6Ω with y = 6 or 4, respectively The individual pull-up and pull-down resistors R ONPU and R ONPD are defined as follows: R ONPU = V DDQ - V OUT / I OUT, when R ONPD is turned off R ONPD = V OUT / I OUT, when R ONPU is turned off Chip in drive mode Output Driver 576Mb: x8, x36 RLDRAM 3 Output Driver Impedance I PU V DDQ To other circuitry such as RCV,... R ONPU R ONPD I OUT DQ V OUT I PD V SSQ PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 33 2 Micron Technology, Inc. All rights reserved.

34 576Mb: x8, x36 RLDRAM 3 Output Driver Impedance Table 9: Driver Pull-Up and Pull-Down Impedance Calculations R ON Min Nom Max Units RZQ/6 = 24Ω ±%/ Ω RZQ/4 = 24Ω ±%/ Ω Driver V OUT Min Nom Max Units 4Ω pull-down.2 V DDQ Ω.5 V DDQ Ω.8 V DDQ Ω 4Ω pull-up.2 V DDQ Ω.5 V DDQ Ω.8 V DDQ Ω 6Ω pull-down.2 V DDQ Ω.5 V DDQ Ω.8 V DDQ Ω 6Ω pull-up.2 V DDQ Ω.5 V DDQ Ω.8 V DDQ Ω PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 34 2 Micron Technology, Inc. All rights reserved.

35 Output Driver Sensitivity Table 2: Output Driver Sensitivity Definition 576Mb: x8, x36 RLDRAM 3 Output Driver Impedance If either the temperature or the voltage changes after ZQ calibration, then the tolerance limits listed in Table 9 page 34 can be expected to widen according to Table 2 page 35 and Table 2 page 35. Symbol Min Max Units R V DDQ.6 - dr ON dth DT - dr ON dvh DV. + dr ON dth DT + dr ON dvh DV RZQ/6, 4 R V DDQ.9 - dr ON dtm DT - dr ON dvm DV. + dr ON dtm DT + dr ON dvm DV RZQ/6, 4 R V DDQ.9 - dr ON dtl DT - dr ON dvl DV.4 + dr ON dtl DT + dr ON dvl D RZQ/6, 4 R V DDQ.9 - dr ON dth DT - dr ON dvh DV.4 + dr ON dth DT + dr ON dvh DV RZQ/6, 4 R V DDQ.9 - dr ON dtm DT - dr ON dvm DV. + dr ON dtm DT + dr ON dvm DV RZQ/6, 4 R V DDQ.6 - dr ON dtl DT - dr ON dvl DV. + dr ON dtl DT + dr ON dvl DV RZQ/6, 4 Note:. DT = T - T@ calibration, DV = V DDQ - V calibration or V DD - V calibration. Table 2: Output Driver Voltage and Temperature Sensitivity Change Min Max Unit dr ON dtm.5 %/ C dr ON dvm.5 %/mv dr ON dtl.5 %/ C dr ON dvl.5 %/mv dr ON dth.5 %/ C dr ON dvh.5 %/mv PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 35 2 Micron Technology, Inc. All rights reserved.

36 Output Characteristics and Operating Conditions 576Mb: x8, x36 RLDRAM 3 Output Characteristics and Operating Conditions Table 22: Single-Ended Output Driver Characteristics Note and 2 apply to entire table Parameter/Condition Symbol Min Max Units Notes Output leakage current; DQ are disabled; Any output ball V V OUT V DDQ ; ODT is disabled; All other balls not under test = V Output slew rate: Single-ended; For rising and falling edges, measures between V OLAC = V REF -. V DDQ and V OHAC = V REF +. V DDQ I OZ 5 5 µa SRQ SE V/ns 4, 5 Single-ended DC high-level output voltage V OHDC.8 V DDQ V 6 Single-ended DC mid-point level output voltage V OMDC.5 V DDQ V 6 Single-ended DC low-level output voltage V OLDC.2 V DDQ V 6 Single-ended AC high-level output voltage V OHAC V TT +. V DDQ V 7, 8, 9 Single-ended AC low-level output voltage V OLAC V TT -. V DDQ V 7, 8, 9 Impedance delta between pull-up and pull-down for DQ and QVLD MM PUPD % 3 Test load for AC timing and output slew rates Output to V TT V DDQ /2 via 25Ω resistor 9 Notes:. All voltages are referenced to V SS. 2. RZQ is 24Ω ±% and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage. 3. Measurement definition for mismatch between pull-up and pull-down MM PUPD. Measure both R ONPU and R ONPD at.5 V DDQ : Ron PU - Ron PD MM PUPD = x Ron NOM 4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are either all static or switching the opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns. 5. See Table 24 page 4 for output slew rate. 6. See the Driver Pull-Up and Pull-Down Impedance Calculations table for IV curve linearity. Do not use AC test load. 7. V TT = V DDQ /2 8. See Figure 6 page 38 for an example of a single-ended output signal. 9. See Figure 8 page 39 for the test load configuration. PDF: 95aef mb_rldram3.pdf - Rev. D 3/3 EN 36 2 Micron Technology, Inc. All rights reserved.