8-Channel, 24-Bit, Simultaneous Sampling ADC AD7771

Transcription

1 Data Sheet FEATURES 8-channel, -bit simultaneous sampling ADC Single-ended or true differential inputs PGA per channel (gains of,,, and 8) Low dc input current ± na (differential)/±8 na (single-ended) Up to 8 ksps ODR per channel Programmable ODRs and bandwidth SRC for coherent sampling Sampling rate resolution up to. SPS Low latency sinc and sinc filter paths Adjustable phase synchronization Internal. V reference Two power modes High resolution mode Low power mode Optimizes power dissipation and performance Low resolution SAR ADC for system and chip diagnostics Power supply Bipolar (±. V) or unipolar (. V) supplies Digital I/O supply:.8 V to. V Performance temperature range: C to + C Functional temperature range: C to + C Performance Combined ac and dc performance db SNR/dynamic range at ksps in high resolution mode (sinc) 9 db THD ±8 ppm of FSR INL ± µv offset error ±.% FS gain error ± ppm/ C typical temperature coefficient APPLICATIONS Power quality and measurement applications General-purpose data acquisition Electroencephalography (EEG) Industrial process control GENERAL DESCRIPTION The AD is an 8-channel, simultaneous sampling analog-todigital converter (ADC). Eight full Σ-Δ ADCs are on-chip. The AD provides an ultralow input current to allow direct sensor connection. Each input channel has a programmable gain stage allowing gains of,,, and 8 to map lower amplitude sensor outputs into the full-scale ADC input range, maximizing the dynamic range of the signal chain. The AD accepts a VREF 8-Channel, -Bit, Simultaneous Sampling ADC AD voltage from V up to. V. The analog inputs accept unipolar ( V to VREF) or true bipolar (±VREF/ V) analog input signals with. V or ±. V analog supply voltages, respectively. The analog inputs can be configured to accept true differential or single-ended signals to match different sensor output configurations. Each channel contains an ADC modulator and a sinc/sinc, low latency digital filter. A sample rate converter (SRC) is provided to allow fine resolution control over the AD output data rate (ODR). This control can be used in applications where the ODR resolution is required to maintain coherency with. Hz changes in the line frequency. The SRC is programmable through the serial port interface (SPI). The AD implements two different interfaces: a data output interface and SPI control interface. The ADC data output interface is dedicated to transmitting the ADC conversion results from the AD to the processor. The SPI writes to and reads from the AD configuration registers and for the control and reading of data from the successive approximation register (SAR) ADC. The SPI can also be configured to output the Σ-Δ conversion data. The AD includes a -bit SAR ADC. This ADC can be used for AD diagnostics without having to decommission one of the Σ-Δ ADC channels dedicated to system measurement functions. With the use of an external multiplexer, which can be controlled through the three general-purpose input/output pins (GPIOs), and signal conditioning, the SAR ADC can validate the Σ-Δ ADC measurements in applications where functional safety is required. In addition, the AD SAR ADC includes an internal multiplexer to sense internal nodes. The AD contains a. V reference and reference buffer. The reference has a typical temperature coefficient of ± ppm/ C. The AD offers two modes of operation: high resolution mode and low power mode. High resolution mode provides a higher dynamic range while consuming. mw per channel; low power mode consumes only. mw per channel at a reduced dynamic range specification. The specified operating temperature range is C to + C, although the device is operational up to + C. Note that throughout this data sheet, certain terms are used to refer to either the multifunction pins or a range of pins. The multifunction pins, such as DCLK/SDO, are referred to either by the entire pin name or by a single function of the pin, for example, DCLK, when only that function is relevant. In the case of ranges of pins, AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVSS, and AVSS. This product is protected by at least U.S. Patent No. 9.,. Rev. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 8.9. Analog Devices, Inc. All rights reserved. Technical Support

2 AD TABLE OF CONTENTS Features... Applications... General Description... Revision History... Functional Block Diagram... Specifications... DOUTx Timing Characterististics... 9 SPI Timing Characterististics... Synchronization Pins and Reset Timing Characteristics... SAR ADC Timing Characterististics... GPIO SRC Update Timing Characterististics... Absolute Maximum Ratings... Thermal Resistance... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... Terminology... Theory of Operation... Analog Inputs... Transfer Function... Core Signal Chain... Capacitive PGA... Internal Reference and Reference Buffers... Integrated LDOs... Clocking and Sampling... Digital Reset and Synchronization Pins... Digital Filtering... 8 Shutdown Mode... 8 Controlling the AD... 9 Pin Control Mode... 9 SPI Control... Digital SPI... RMS Noise and Resolution... High Resolution Mode... Low Power Mode... 8 Diagnostics and Monitoring... 9 Self Diagnostics Error... 9 Monitoring Using the AD SAR ADC (SPI Control Mode)... Σ-Δ ADC Diagnostics (SPI Control Mode)... Data Sheet Σ- Output Data... ADC Conversion Output Header and Data... Sample Rate Converter (SRC) (SPI Control Mode)... Data Output Interface... Calculating the CRC Checksum... Register Summary... Register Details... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... 8 Channel Configuration Register... 8 Disable Clocks to ADC Channel Register... 9 Channel Sync Offset Register... 9 Channel Sync Offset Register... 9 Channel Sync Offset Register... 9 Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... General User Configuration Register... General User Configuration Register... General User Configuration Register... Data Output Format Register... Main ADC Meter and Reference Mux Control Register... Global Diagnostics Mux Register... GPIO Configuration Register... GPIO Data Register... Buffer Configuration Register... Buffer Configuration Register... Channel Offset Upper Byte Register... Channel Offset Middle Byte Register... Channel Offset Lower Byte Register... Channel Gain Upper Byte Register... Channel Gain Middle Byte Register... Channel Gain Lower Byte Register... 8 Rev. Page of 98

3 Data Sheet Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 9 Channel Gain Lower Byte Register... 9 Channel Offset Upper Byte Register... 9 Channel Offset Middle Byte Register... 9 Channel Offset Lower Byte Register... 9 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 AD Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Status Register... 8 Channel Status Register... 8 Channel Status Register... 8 Channel Status Register Channel Status Register Channel Status Register Channel Status Register Channel Status Register... 9 Channel /Channel DSP Errors Register... 9 Channel /Channel DSP Errors Register... 9 Channel /Channel DSP Errors Register... 9 Channel /Channel DSP Errors Register... 9 Channel to Channel Error Register Enable Register... 9 General Errors Register... 9 General Errors Register Enable... 9 General Errors Register... 9 General Errors Register Enable... 9 Error Status Register... 9 Error Status Register... 9 Error Status Register... 9 Decimation Rate (N) MSB Register... 9 Decimation Rate (N) LSB Register... 9 Decimation Rate (IF) MSB Register... 9 Decimation Rate (IF) LSB Register... 9 SRC Load Source and Load Update Register... 9 Outline Dimensions Ordering Guide REVISION HISTORY / Revision : Initial Version Rev. Page of 98

4 AD Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDDx REF_OUT REFx+ REFx AVDDx AREGxCAP IOVDD DREGCAP VCM AIN+ AIN AIN+ AIN AIN+ AIN 8mV p-p EXT_REF INT_REF REFERENCES REFERENCES COMMON- MODE VOLTAGE.V REF PGA PGA PGA Σ-Δ ADC Σ-Δ ADC Σ-Δ ADC SINC/ SINC SRC FILTER SINC/ SINC SRC FILTER SINC/ SINC SRC FILTER ANALOG LDO GAIN OFFSET GAIN OFFSET GAIN OFFSET DIGITAL LDO REGISTER MAP AND LOGIC CONTROL CLOCK MANAGER DATA OUTPUT INTERFACE XTAL XTAL/MCLK SYNC_IN SYNC_OUT START DCLK DRDY DOUT DOUT DOUT DOUT RESET AIN+ AIN AIN+ AIN REFERENCES REFERENCES PGA PGA Σ-Δ ADC Σ-Δ ADC SINC/ SINC SRC FILTER SINC/ SINC SRC FILTER GAIN OFFSET GAIN OFFSET HARDWARE MODE CONFIGURATION FORMAT FORMAT MODE/ALERT MODE/GPIO MODE/GPIO MODE/GPIO AIN+ AIN AIN+ AIN REFERENCES REFERENCES PGA PGA Σ-Δ ADC Σ-Δ ADC SINC/ SINC SRC FILTER SINC/ SINC SRC FILTER GAIN OFFSET GAIN OFFSET SPI INTERFACE ALERT/CS DCLK/SCLK DCLK/SDI DCLK/SDO AIN+ AIN REFERENCES PGA Σ-Δ ADC SINC/ SINC SRC FILTER GAIN OFFSET AUXAIN+ AUXAIN AD SAR ADC DIAGNOSTIC INPUTS AVSSx AVDD CONVST_SAR Figure. 8- Rev. Page of 98

5 Data Sheet AD SPECIFICATIONS AVDDx =. V, AVSSx =. V (dual supply operation), AVDDx =. V, AVSSx = analog ground (AGND) (single-supply operation), AVDDx AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V AVSSx (internal/external), master clock (MCLK) = 89 khz for high resolution mode and 9 khz for low power mode, ODR = 8 ksps for high resolution mode and ksps for low power mode; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUTS Differential Input Voltage Range VREF = (REFx+ REFx ) ±VREF/PGAGAIN V Single-Ended Input Voltage Range to VREF/PGAGAIN V AINx± Common-Mode Input Range AVSSx +. (AVDDx + AVDDx. V AVSSx)/ Absolute AINx± Voltage Limits AVSSx +. AVDDx. V DC Input Current Differential High resolution mode ± na Low power mode ± na Single-Ended High resolution mode ±8 na Low power mode ± na Input Current Drift pa/ C AC Input Capacitance 8 pf PROGRAMMABLE GAIN AMPLIFIER (PGA) Gain Settings (PGAGAIN),,, or 8 Bandwidth Small Signal High resolution mode MHz Low power mode khz Large Signal High resolution mode See Figure 9, Figure, and Figure Low power mode See Figure, Figure, and Figure REFERENCE Internal Initial Accuracy REF_OUT, TA = C.9.. V Temperature Coefficient ± ±8 ppm/ C Reference Load Current, IL + ma DC Power Supply Rejection Line regulation 9 db Load Regulation, VOUT/ IL µv/ma Voltage Noise, en p-p. Hz to Hz.8 µv rms Voltage Noise Density, en khz,. V reference. nv/ Hz Turn On Settling Time nf. ms External Input Voltage VREF = (REFx+ REFx ). AVDDx V Buffer Headroom AVSSx +. AVDDx. V REFx Input Voltage AVSSx AVDDx REFx+ V Average REFx± Input Current Current per channel Reference buffer disabled, 8 µa/v high resolution mode Reference buffer precharge mode na/v (pre-q), high resolution mode Reference buffer disabled,. µa/v low power mode Reference buffer pre-q, na/v low power mode Reference buffer enabled, na/v high resolution mode Reference buffer enabled, low power mode na/v Rev. Page of 98

6 AD Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit TEMPERATURE RANGE Specified Performance TMIN to TMAX + C Functional TMIN to TMAX + C TEMPERATURE SENSOR Accuracy ± C DIGITAL FILTER RESPONSE Group Delay See the SRC Group Delay section Settling Time See the Settling Time section Pass Band. db See the SRC Bandwidth section db See the SRC Bandwidth section Decimation Rate Sinc 9.99 Sinc 8 CLOCK SOURCE Frequency High resolution mode. 8.9 MHz Low power mode..9 MHz Duty Cycle : : : % Σ-Δ ADC Speed and Performance Resolution Bits ODR High resolution mode 8 ksps Low power mode ksps No Missing Codes Sinc, up to ksps Bits Sinc Bits AC Accuracy Dynamic Range Shorted inputs, PGAGAIN = 8 ksps High resolution mode (sinc) 9 db ksps High resolution mode (sinc) db ksps High resolution mode (sinc).9 db ksps High resolution mode (sinc) db ksps Low power mode (sinc) 9. db 8 ksps Low power mode (sinc). db 8 ksps Low power mode (sinc) 9.8 db ksps Low power mode (sinc).8 db Total Harmonic Distortion (THD). dbfs, high resolution mode 9 db. dbfs, low power mode db Signal-to-Noise-and-Distortion Ratio fin = Hz db (SINAD) Spurious-Free Dynamic Range High resolution mode, ksps, db (SFDR) PGAGAIN = Intermodulation Distortion (IMD) fa = Hz, fb = Hz, db high resolution mode fa = Hz, fb = Hz, db low power mode DC Power Supply Rejection AVDDx =. V 9 db DC Common-Mode Rejection Ratio 8 db Crosstalk db DC ACCURACY Integral Nonlinearity (INL) Endpoint method High Resolution PGAGAIN = ±8 ± ppm of FSR Other PGA gains ± ± ppm of FSR Rev. Page of 98

7 Data Sheet AD Parameter Test Conditions/Comments Min Typ Max Unit Low Power PGAGAIN = ±9 ± ppm of FSR Other PGA gains ± ± ppm of FSR Offset Error ± ±9 µv Offset Error Drift. µv/ C Over time µv/ hours Offset Matching µv Gain Error ±. % FS Gain Error Drift vs. Temperature PGAGAIN = ±. ppm/ C Gain Matching ±. % SAR ADC Speed and Performance Resolution Bits Analog Input Range AVSS +. AVDD. V Analog Input Common-Mode Range AVSS +. (AVDD + AVDD. V AVSS)/ Analog Input Current ± na Throughput ksps DC Accuracy Differential mode INL ±. LSB Differential Nonlinearity (DNL) No missing codes (-bit).99 LSB Offset ± LSB Gain LSB AC Performance Signal-to-Noise Ratio (SNR) khz db THD khz 8 db VCM PIN Output (VCM) (AVDDx + V AVSSx)/ Load Current, IL ma Load Regulation, VOUT/ IL mv/ma Short-Circuit Current ma LOGIC INPUTS Input Voltage High, VIH. IOVDD V Low, VIL. V Hysteresis. V Input Currents + µa LOGIC OUTPUTS Output Voltage High, VOH IOVDD V, ISOURCE = ma.8 IOVDD V. V IOVDD < V,.8 IOVDD V ISOURCE = µa IOVDD <. V, ISOURCE = µa.8 IOVDD V Low, VOL IOVDD V, ISINK = ma. V. V IOVDD < V, ISINK = ma. V IOVDD <. V, ISINK = µa. V Leakage Current Floating state + µa Output Capacitance Floating state pf Σ-Δ ADC Data Output Coding Twos complement SAR ADC Data Output Coding Binary Rev. Page of 98

8 AD Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLIES All Σ-Δ channels enabled AVDDx AVSSx.. V IAVDDx, Reference buffer pre-q, VCM enabled, internal reference enabled High resolution mode 8.. ma Low power mode. ma Reference buffer enabled, VCM enabled, internal reference enabled High resolution mode.. ma Low power mode.. ma Reference buffer disabled, VCM disabled, internal reference disabled High resolution mode. 8.8 ma Low power mode.9. ma AVDDx AVSSx.. V IAVDDx High resolution mode.. ma Low power mode.8 ma AVDD AVSSx. V IAVDD SAR enabled. ma SAR disabled µa AVSSx DGND.8 V IOVDD DGND.8. V IIOVDD High resolution mode (sinc). ma Low power mode (sinc).. ma High resolution mode (sinc).. ma Low power mode (sinc)..9 ma Power Dissipation Internal buffers bypassed, internal reference disabled, internal oscillator disabled, SAR disabled High Resolution Mode 8 ksps mw Low Power Mode ksps 8. mw Power-Down All ADCs disabled µw AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVDD, and AVSS. This term is used throughout the data sheet. At temperatures higher than C, the device can be operated normally, though slight degradation on the maximum/minimum specifications is expected because these specifications are only guaranteed up to C. See the Typical Performance Characteristics section for plots showing the typical performance of the device at high temperatures. The SDO pin and the DOUTx pin are configured in the default mode of strength. AVDDx =. V, AVSSx = GND = ground, IOVDD =.8 V, CMOS clock. Disabling either the VCM pin or the internal reference results in a µa typical current consumption reduction. Power dissipation is calculated using the maximum supply voltage,. V. Rev. Page 8 of 98

9 Data Sheet AD DOUTx TIMING CHARACTERISTISTICS AVDDx =. V, AVSSx =. V (dual supply operation), AVDDx =. V, AVSSx = AGND (single-supply operation), AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V internal/external, MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Test Conditions/Comments Min Typ Max Unit t MCLK frequency :. 8.9 MHz t MCLK low time ns t MCLK high time ns t DCLK high time MCLK/ ns t DCLK low time MCLK/ ns t MCLK falling edge to DCLK rising edge ns t MCLK falling edge to DCLK falling edge ns t8 DCLK rising edge to DRDY rising edge ns t9 DCLK rising edge to DRDY falling edge ns t DOUTx setup time ns t DOUTx hold time ns AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVSS, and AVSS. This term is used throughout the data sheet. All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. t t t MCLK DCLK t t t t t 8 t 9 DRDY DOUTx LSB MSB MSB LSB + LSB t t Figure. Data Interface Timing Diagram 8- Rev. Page 9 of 98

10 AD Data Sheet SPI TIMING CHARACTERISTISTICS AVDDx =. V, AVSSx =. V (dual supply operation), AVDDx =. V, AVSSx = AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Test Conditions/Comments Min Typ Max Unit t SCLK period : MHz t SCLK low time ns t SCLK high time ns t SCLK rising edge to CS falling edge ns t CS falling edge to SCLK rising edge ns t SCLK rising edge to CS rising edge ns t8 CS rising edge to SCLK rising edge ns t9 Minimum CS high time ns t SDI setup time ns t SDI hold time ns ta CS falling edge to SDO enable (SPI = Mode ) ns tb SCLK falling edge to SDO enable (SPI = Mode ) 9 ns t SDO setup time ns t SDO hold time ns t CS rising edge to SDO disable ns AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVSS, and AVSS. This term is used throughout the data sheet. All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. t 9 CS t t t t t t 8 SCLK t t SDI MSB MSB LSB + LSB t A t SDO MSB MSB LSB + LSB t B t t t 8- Figure. SPI Control Interface Timing Diagram Rev. Page of 98

11 Data Sheet AD SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS AVDDx =. V, AVSSx =. V (dual supply operation), AVDDx =. V, AVSSx = AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Test Conditions/Comments Min Typ Max Unit t START setup time ns t START hold time MCLK ns t8 MCLK falling edge to SYNC_OUT falling edge MCLK ns t9 SYNC_IN setup time ns t SYNC_IN hold time MCLK ns tinit_sync_in SYNC_IN rising edge to first DRDY ksps, high resolution mode µs tinit_reset RESET rising edge to first DRDY ksps, high resolution mode µs t RESET hold time MCLK ns tpower_up Start time tpower_up is not shown in Figure ms AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVSS, and AVSS. This term is used throughout the data sheet. All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. MCLK START t t SYNC_OUT SYNC_IN t 8 DRDY t 9 t t INIT_SYNC_IN RESET t t INIT_RESET 8- Figure. Synchronization Pins and Reset Control Interface Timing Diagram Rev. Page of 98

12 AD Data Sheet SAR ADC TIMING CHARACTERISTISTICS AVDDx =. V, AVSSx =. V (dual supply operation), AVDDx =. V, AVSSx = AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Min Typ Max Unit t Conversion time. µs t Acquisition time ns t Delay time ns t Throughput data rate ksps AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVSS and AVSS. This term is used throughout the data sheet. All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. Direct mode enabled. If deglitch mode is enabled, add./mclk as described in Table 9. CS t t t CONVST_SAR t Figure. SAR ADC Timing Diagram 8- GPIO SRC UPDATE TIMING CHARACTERISTISTICS AVDDx =. V, AVSSx =. V (dual supply operation), AVDDx =. V, AVSSx = AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications TMIN to TMAX, unless otherwise noted. Table. Parameter Description Min Typ Max Unit t GPIO setup time ns t GPIO hold time high resolution mode MCLK ns GPIO hold time low power mode MCLK ns t8 MCLK rising edge to GPIO rising edge time ns t9 GPIO setup time ns t GPIO hold time MCLK ns AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVSS and AVSS. This term is used throughout the data sheet. All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. MCLK GPIO t t GPIO GPIO t 8 t t 9 Figure. GPIOs for SRC Update Timing Diagram 8- Rev. Page of 98

13 Data Sheet ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Any Supply Pin to AVSSx. V to +.9 V AVSSx to DGND.98 V to +. V AREGxCAP to AVSSx. V to +.98 V DREGCAP to DGND. V to +.98 V IOVDD to DGND. V to +.9 V IOVDD to AVSSx. V to +.9 V AVDD to AVSSx. V to +.9 V Analog Input Voltage AVSSx. V to AVDDx +. V or.9 V (whichever is less) REFx± Input Voltage AVSSx. V to AVDDx +. V or.9 V (whichever is less) AUXAIN± AVSSx. V to AVDD +. V or.9 V (whichever is less) Digital Input Voltage to DGND DGND. V to IOVDD +. V or.9 V (whichever is less) Digital Output Voltage to DGND DGND. V to IOVDD +. V or.9 V (whichever is less) XTAL to DGND DGND. V to DREGCAP +. V or.98 V (whichever is less) AINx±, AUXAIN±, and ± ma Digital Input Current Operating Temperature C to + C Range Junction Temperature, C TJ Maximum Storage Temperature Range C to + C Reflow Soldering C ESD kv Field Induced Charged V Device Model (FICDM) AD Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 8. Thermal Resistance Package Type θja θjb ΨJT ΨJB Unit CP-- No Thermal Vias. N/A..9 C/W 9 Thermal Vias C/W Thermal impedance simulated values are based on a JEDEC SP thermal test board. See JEDEC JESD. N/A means not applicable. ESD CAUTION Rev. Page of 98

14 AD Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD TOP VIEW (Not to Scale) CONVST_SAR ALERT/CS DCLK/SCLK DCLK/SDI DCLK/SDO DGND DREGCAP IOVDD DOUT DOUT DOUT DOUT DCLK DRDY XTAL XTAL/MCLK AUXAIN AUXAIN+ AVDD AVSS AVSSA AREGCAP AVDDA VCM CLK_SEL FORMAT FORMAT AVSS AVDDB AREGCAP AVSSB REF_OUT AIN AIN+ AIN AIN+ AVSSA AVDDA REF REF+ 8 AIN 9 AIN+ AIN AIN+ MODE/GPIO MODE/GPIO MODE/GPIO MODE/ALERT 8 AIN AIN+ AIN AIN+ AVSSB AVDDB REF REF+ AIN 9 AIN+ 8 AIN AIN+ RESET SYNC_IN SYNC_OUT START NOTES. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AVSSx. Figure. Pin Configuration 8- Table 9. Pin Function Descriptions Pin No. Mnemonic Type Direction Description AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. AVSSA Supply Supply Negative Front-End Analog Supply for Channel to Channel, Typical at. V (Dual Supply) and AGND (Single Supply). Connect all the AVSSx pins to the same potential. AVDDA Supply Supply Positive Front-End Analog Supply for Channel to Channel, Typical at AVSSx +. V. Connect this pin to AVDDB. REF Reference Input Negative Reference Input for Channel to Channel, Typical at AVSSx. Connect all the REFx pins to the same potential. 8 REF+ Reference Input Positive Reference Input for Channel to Channel, Typical at REF +. V. 9 AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. MODE/GPIO Digital I/O I/O Mode Input in Pin Control Mode (MODE). See Table for more details. Configurable General-Purpose Input/Output in SPI Control Mode (GPIO). If not in use, connect this pin to DGND or IOVDD. MODE/GPIO Digital I/O I/O Mode Input in Pin Control Mode (MODE). See Table for more details. Configurable General-Purpose Input/Output in SPI Control Mode (GPIO). If not in use, connect this pin to DGND or IOVDD. MODE/GPIO Digital I/O I/O Mode Input in Pin Control Mode (MODE). See Table for more details. Configurable General-Purpose Input/Output in SPI Control Mode (GPIO). If not in use, connect this pin to DGND or IOVDD. MODE/ALERT Digital I/O I/O Mode Input in Pin Control Mode (MODE). See Table for more details. Alert Output in SPI Control Mode (ALERT). Rev. Page of 98

15 Data Sheet AD Pin No. Mnemonic Type Direction Description CONVST_SAR Digital input Input Σ-Δ Output Interface Selection Pin in Pin Control Mode. See Table for more details. This pin also functions as the start for the SAR conversion in SPI control mode. 8 ALERT/CS Digital input Input Alert Output in Pin Control Mode (ALERT). Chip Select in SPI Control Mode (CS). 9 DCLK/SCLK Digital input Input Data Clock Frequency Selection Pin in Pin Control Mode (DCLK). See Table for more details. SPI Clock in SPI Control Mode (SCLK). DCLK/SDI Digital input Input Data Clock Frequency Selection Pin in Pin Control Mode (DCLK). See Table for more details. SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the device is configured in pin control mode with the SPI as the data output interface. DCLK/SDO Digital output Output Data Clock Frequency Selection Pin in Pin Control Mode (DCLK). See Table for more details. SPI Data Output in SPI Control Mode (SDO). DGND Supply Supply Digital Ground. DREGCAP Supply Output Digital Low Dropout (LDO) Output. Decouple this pin to DGND with a µf capacitor. IOVDD Supply Supply Digital Levels Input/Output and Digital LDO (DLDO) Supply from.8 V to. V. IOVDD must not be lower than DREGCAP. DOUT Digital output I/O Data Output Pin. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. DOUT Digital output I/O Data Output Pin. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. DOUT Digital output Output Data Output Pin. 8 DOUT Digital output Output Data Output Pin. 9 DCLK Digital output Output Data Output Clock. DRDY Digital output Output Data Output Ready Pin. XTAL Clock Input Crystal Input Connection. If CMOS is used as a clock source, tie this pin to DGND. See Table for more details. XTAL/MCLK Clock Input Crystal Input Connection (XTAL). See Table for more details. CMOS Clock (MCLK). See Table for more details. START Digital input Input Synchronization Pulse. This pin internally synchronizes an external START asynchronous pulse with MCLK. The synchronize signal is shifted out by the SYNC_OUT pin. If not in use, tie this pin to DGND. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details. SYNC_OUT Digital output Input Synchronization Signal. This pin generates a synchronous pulse generated and driven by hardware (via the START pin) or by software (GENERAL_USER_ CONFIG_, Bit ). If this pin is in use, it must be wired to the SYNC_IN pin. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details. SYNC_IN Digital input Input Reset for the Internal Digital Block and Synchronize for Multiple Devices. See the Digital Reset and Synchronization Pins section for more details. RESET Digital input Input Asynchronous Reset Pin. This pin resets all registers to their default value. It is recommended to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block. AIN+ Analog input Input Analog Input Channel, Positive. 8 AIN Analog input Input Analog Input Channel, Negative. 9 AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. REF+ Reference Input Positive Reference Input for Channel to Channel, Typical at REF +. V. REF Reference Input Negative Reference Input for Channel to Channel, Typical at AVSSx. Connect all the REFx pins to the same potential. AVDDB Supply Supply Positive Front-End Analog Supply for Channel to Channel. Connect this pin to AVDDA. Rev. Page of 98

16 AD Data Sheet Pin No. Mnemonic Type Direction Description AVSSB Supply Supply Negative Front-End Analog Supply for Channel to Channel, Typical at. V (Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins to the same potential. AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. 8 AIN Analog input Input Analog Input Channel, Negative. 9 REF_OUT Reference Output. V Reference Output. Connect a nf capacitor on this pin if using the internal reference. AVSSB Supply Supply Negative Analog Supply. Connect all the AVSSx pins together. AREGCAP Supply Output Analog LDO Output. Decouple this pin to AVSSB with a µf capacitor. AVDDB Supply Supply Positive Analog Supply. Connect this pin to AVDDA. AVSS Supply Supply Negative Analog Ground. Connect all the AVSSx to the same potential. FORMAT Digital input Input Output Data Frame. See Table for more details. FORMAT Digital input Input Output Data Frame. See Table for more details. CLK_SEL Digital input Input Select Clock Source. See Table for more details. VCM Analog output Output Common-Mode Voltage Output, Typical at (AVDDx + AVSSx)/. 8 AVDDA Supply Input Analog Supply from. V to. V. AVSSx must not be lower than AREGxCAP. Connect this pin to AVDDB. 9 AREGCAP Supply Output Analog LDO Output. Decouple this pin to AVSSx with a µf capacitor. AVSSA Supply Input Negative Analog supply. Connect all the AVSSx pins to the same potential. AVSS Supply Supply Negative SAR Analog Supply and Reference. Connect all AVSSx pins to the same potential. AVDD Supply Supply Positive SAR Analog Supply and Reference Source. AUXAIN+ Analog input Input Positive SAR Analog Input Channel. AUXAIN Analog input Input Negative SAR Analog Input Channel. EPAD Supply Input Exposed Pad. Connect the exposed pad to AVSSx. Rev. Page of 98

17 Data Sheet AD TYPICAL PERFORMANCE CHARACTERISTICS INL (ppm) T A = C GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) INPUT VOLTAGE (V)... CH CH CH CH CH CH CH CH INL (ppm).8 T A = C GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) INPUT VOLTAGE (V). CH CH CH CH CH CH CH CH Figure 8. INL vs. Input Voltage and Channel at ksps, High Resolution Mode Figure. INL vs. Input Voltage and Channel at ksps, Low Power Mode 8 GAIN = GAIN = GAIN = GAIN = 8 8 GAIN = GAIN = GAIN = GAIN = 8 INL (ppm) INL (ppm) T A = C DIFFERENTIAL V IN GAIN V REF =.V V CM = (AVDDx + AVSSx).. INPUT VOLTAGE (V) T A = C DIFFERENTIAL V IN GAIN V REF =.V V CM = (AVDDx + AVSSx).. INPUT VOLTAGE (V) Figure 9. INL vs. Input Voltage and PGA Gain at ksps, High Resolution Mode Figure. INL vs. Input Voltage and PGA Gain at ksps, Low Power Mode 8 T A = C T A = + C T A = + C T A = + C T A = C T A = + C T A = + C T A = + C INL (ppm) INL (ppm) 8 GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and Temperature at ksps, High Resolution Mode 8- GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and Temperature at ksps, Low Power Mode 8- Rev. Page of 98

18 AD Data Sheet V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V INL (ppm) T A = C GAIN = DIFFERENTIAL INPUT SIGNAL V CM = (AVDDx + AVSSx) INPUT VOLTAGE (V) 8- INL (ppm) T A = C GAIN = DIFFERENTIAL INPUT SIGNAL V CM = (AVDDx + AVSSx) V REF =.V INPUT VOLTAGE (V) 8- Figure. INL vs. Input Voltage and Reference Voltage (VREF) at ksps, High Resolution Mode Figure. INL vs. Input Voltage and Reference Voltage (VREF) at ksps, Low Power Mode 8 V CM =.9V V CM =.V V CM =.V V CM =.9V V CM =.V V CM =.V INL (ppm) INL (ppm) INPUT VOLTAGE (V) T A = C GAIN = DIFFERENTIAL V IN GAIN V REF =.V T A = C GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and VCM at ksps, High Resolution Mode Figure 8. INL vs. Input Voltage and VCM at ksps, Low Power Mode SAMPLE COUNT 9 8 V REF =.V V CM = (AVDDx + AVSSx) T A = C GAIN = GAIN = GAIN = GAIN = 8 SAMPLE COUNT 9 8 V REF =.V V CM = (AVDDx + AVSSx) T A = C GAIN = GAIN = GAIN = GAIN = ADC CODE ADC CODE Figure. Noise Histogram at ksps, High Resolution Mode, Sinc Filter Enabled Figure 9. Noise Histogram at ksps, Low Power Mode, Sinc Filter Enabled Rev. Page 8 of 98

19 Data Sheet AD SAMPLE COUNT V REF =.V V CM = (AVDDx + AVSSx) T A = C GAIN = GAIN = GAIN = GAIN = 8 SAMPLE COUNT V REF =.V V CM = (AVDDx + AVSSx) T A = C GAIN = GAIN = GAIN = GAIN = ADC CODE ADC CODE Figure. Noise Histogram at ksps, High Resolution Mode, Sinc Filter Enabled Figure. Noise Histogram at ksps, Low Power Mode, Sinc Filter Enabled V REF =.V V CM = (AVDDx + AVSSx) V REF =.V V CM = (AVDDx + AVSSx) NOISE (µv rms) 8 GAIN = GAIN = GAIN = GAIN = 8 NOISE (µv rms) 8 GAIN = GAIN = GAIN = GAIN = 8 TEMPERATURE ( C) Figure. Noise vs. Temperature at ksps, High Resolution Mode, Sinc Filter Enabled 8- TEMPERATURE ( C) Figure. Noise vs. Temperature at ksps, Low Power Mode, Sinc Filter Enabled 8- NOISE (µv rms) 8 8 GAIN = GAIN = GAIN = GAIN = 8 V REF =.V V CM = (AVDDx + AVSSx) TEMPERATURE ( C) Figure. Noise vs. Temperature at ksps, High Resolution Mode, Sinc Filter Enabled 8- NOISE (µv rms) 8 8 V REF =.V V CM = (AVDDx + AVSSx) GAIN = GAIN = GAIN = GAIN = 8 TEMPERATURE ( C) Figure. Noise vs. Temperature at ksps, Low Power Mode, Sinc Filter Enabled 8- Rev. Page 9 of 98

20 AD Data Sheet NOISE (µv rms) V REF =.V V CM = (AVDDx + AVSSx) T A = C DECIMATION = GAIN = GAIN = GAIN = GAIN = 8 NOISE (µv rms) V REF =.V V CM = (AVDDx + AVSSx) T A = C DECIMATION = GAIN = GAIN = GAIN = GAIN = CLOCK FREQUENCY (Hz) CLOCK FREQUENCY (Hz) Figure. Noise vs. Clock Frequency, High Resolution Mode Figure 9. Noise vs. Clock Frequency, Low Power Mode GAIN = GAIN = GAIN = GAIN = 8 GAIN = GAIN = GAIN = GAIN = 8 NOISE (nv/ Hz) 8 NOISE (nv/ Hz) 8 ODR (SPS) Figure. Noise vs. ODR, High Resolution Mode, Sinc Filter Enabled 8-8 ODR (SPS) Figure. Noise vs. ODR, Low Power Mode, Sinc Filter Enabled 8-8 GAIN = GAIN = GAIN = GAIN = 8 GAIN = GAIN = GAIN = GAIN = 8 NOISE (nv/ Hz) 8 NOISE (nv/ Hz) 8 8 ODR (SPS) Figure 8. Noise vs. ODR, High Resolution Mode, Sinc Filter Enabled ODR (SPS) Figure. Noise vs. ODR, Low Power Mode, Sinc Filter Enabled 8- Rev. Page of 98

21 Data Sheet AD AMPLITUDE (db) GAIN = GAIN = GAIN = GAIN = T A = C V REF =.V V CM = (AVDDx + AVSSx) INPUT FREQUENCY = Hz AMPLITUDE (db) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V CM = (AVDDx + AVSSx) INPUT FREQUENCY = Hz FREQUENCY (Hz) FREQUENCY (Hz) Figure. FFT Plot, High Resolution Mode at ksps, Input Frequency (fin) = Hz, Sinc Filter Enabled Figure. FFT Plot, Low Power Mode at ksps, Input Frequency (fin) = Hz, Sinc Filter Enabled AMPLITUDE (db) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V CM = (AVDDx + AVSSx) ODR = 8kSPS 8 INPUT FREQUENCY = Hz 9 8 AMPLITUDE (db) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V CM = (AVDDx + AVSSx) ODR = ksps INPUT FREQUENCY = Hz FREQUENCY (Hz) Figure. FFT Plot, High Resolution Mode at 8 ksps, Input Frequency (fin) = Hz, Sinc Filter Enabled FREQUENCY (Hz) Figure. FFT Plot, Low Power Mode at ksps, Input Frequency (fin) = Hz, Sinc Filter Enabled. 8- AMPLITUDE (db) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V CM = (AVDDx + AVSSx) INPUT FREQUENCY = khz FREQUENCY (Hz) AMPLITUDE (db) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V CM = (AVDDx + AVSSx) INPUT FREQUENCY = khz FREQUENCY (Hz) 8- Figure. FFT Plot, High Resolution Mode at ksps, Input Frequency (fin) = khz, Sinc Filter Enabled Figure. FFT Plot, Low Power Mode at ksps, Input Frequency (fin) = khz, Sinc Filter Enabled Rev. Page of 98

22 AD Data Sheet AMPLITUDE (db) FREQUENCY (Hz) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V CM = (AVDDx + AVSSx) ODR = 8kSPS INPUT FREQUENCY = khz AMPLITUDE (db) FREQUENCY (Hz) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V CM = (AVDDx + AVSSx) ODR = ksps INPUT FREQUENCY = khz Figure 8. FFT Plot, High Resolution Mode at 8 ksps, Input Frequency (fin) = khz, Sinc Filter Enabled Figure. FFT Plot, Low Power Mode at ksps, Input Frequency (fin) = khz, Sinc Filter Enabled GAIN = GAIN = GAIN = GAIN = 8 GAIN = GAIN = GAIN = GAIN = 8 THD (db) THD (db). T A = C GAIN = V REF =.V V CM = (AVDDx + AVSSx) V IN =.dbfs INPUT FREQUENCY (Hz) Figure 9. THD vs. Input Frequency at ksps, High Resolution Mode, Sinc Filter Enabled THD (db) INPUT FREQUENCY (Hz) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V IN =.dbfs Figure. THD vs. Input Frequency at ksps, High Resolution Mode, Sinc Filter Enabled THD (db). T A = C V REF =.V V IN =.dbfs INPUT FREQUENCY (Hz) Figure. THD vs. Input Frequency at ksps, Low Power Mode, Sinc Filter Enabled. INPUT FREQUENCY (Hz) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V IN =.dbfs Figure. THD vs. Input Frequency at ksps, Low Power Mode, Sinc Filter Enabled 8-8- Rev. Page of 98

23 Data Sheet AD GAIN = GAIN = GAIN = GAIN = 8 GAIN = GAIN = GAIN = GAIN = 8 THD (db) THD (db). T A = C V REF =.V INPUT FREQUENCY = Hz INPUT VOLTAGE (V) Figure. THD vs. Input Voltage at ksps, High Resolution Mode. 8-. T A = C V REF =.V INPUT FREQUENCY = Hz INPUT VOLTAGE (V) Figure. THD vs. Input Voltage at ksps, Low Power Mode GAIN = GAIN = GAIN = GAIN = GAIN = GAIN = GAIN = GAIN = 8 T A = C ±V REF INPUT FREQUENCY = Hz THD (db) THD (db). T A = C ±V REF INPUT FREQUENCY = Hz REFERENCE VOLTAGE (V) Figure. THD vs. Reference Voltage at ksps, High Resolution Mode REFERENCE VOLTAGE (V) Figure 8. THD vs. Reference Voltage at ksps, Low Power Mode. 8-8 GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V INPUT FREQUENCY = Hz THD (db) 8 THD (db) MCLK FREQUENCY (Hz) Figure. THD vs. Master Clock Frequency, High Resolution Mode 8- GAIN = GAIN = GAIN = GAIN = MCLK FREQUENCY (Hz) T A = C V REF =.V INPUT FREQUENCY = Hz Figure 9. THD vs. Master Clock Frequency, Low Power Mode 8-9 Rev. Page of 98

24 AD Data Sheet SNR (db) 9 SNR (db) GAIN = T GAIN = A = C V GAIN = REF =.V GAIN = 8 V IN = dbfs 8 8 ODR (SPS) GAIN = T GAIN = A = C V GAIN = REF =.V GAIN = 8 V IN = dbfs 8 8 ODR (SPS) 8- Figure. SNR vs. ODR at ksps, High Resolution Mode (AVDDx =. V, IOVDD =. V) Figure. SNR vs. ODR at ksps, Low Power Mode (AVDDx =. V, IOVDD =. V) T A = C V REF =.V V IN = dbfs GAIN = GAIN = GAIN = GAIN = 8 SNR (db) 9 SNR (db) 9 T A = C V REF =.V V IN = dbfs GAIN = GAIN = GAIN = GAIN = ODR (SPS) ODR (SPS) 8- Figure. SNR vs. ODR at ksps, High Resolution Mode (AVDDx =. V, IOVDD =. V) Figure. SNR vs. ODR at ksps, Low Power Mode (AVDDx =. V, IOVDD =. V) 8 T A = C ODR = ksps 8 T A = C ODR = ksps DYNAMIC RANGE (db) DYNAMIC RANGE (db) PGA GAIN PGA GAIN 8- Figure. Dynamic Range vs. PGA Gain at ksps, High Resolution Mode Figure. Dynamic Range vs. PGA Gain at ksps, Low Power Mode Rev. Page of 98

25 Data Sheet AD T A = C ODR = ksps T A = C ODR = ksps DYNAMIC RANGE (db) DYNAMIC RANGE (db) PGA GAIN PGA GAIN 8-9 Figure. Dynamic Range vs. PGA Gain at ksps, High Resolution Mode Figure 9. Dynamic Range vs. PGA Gain at ksps, Low Power Mode OFFSET ERROR (µv) T A = C V REF =.V V IN = V SUPPLY = AVDDx =.V CH CH CH CH CH CH CH CH 8 PGA GAIN 8- OFFSET ERROR (µv) T A = C V REF =.V V IN = V SUPPLY = AVDDx =.V CH CH CH CH CH CH CH CH 8 PGA GAIN 8- Figure. Offset Error vs. PGA Gain at ksps, High Resolution Mode Figure. Offset Error vs. PGA Gain at ksps, Low Power Mode OFFSET ERROR (µv) GAIN = T A = C GAIN = V GAIN = REF =.V GAIN = 8 V IN = V... AVDDx SUPPLY 8-8 OFFSET ERROR (µv) GAIN = GAIN = GAIN = GAIN = 8 T A = C V REF =.V V IN = V... AVDDx SUPPLY 8- Figure 8. Offset Error vs. AVDDx Supply, High Resolution Mode Figure. Offset Error vs. AVDDx Supply, Low Power Mode Rev. Page of 98

26 AD Data Sheet OFFSET DRIFT (µv) AVDDx =.V CH CH CH CH CH CH CH CH 8 TEMPERATURE ( C) Figure. Offset Drift vs. Temperature 8- GAIN ERROR DRIFT (ppm) 8 TIME (Hours) Figure. Gain Error Drift vs. Time 8- GAIN ERROR (%) CH CH CH CH CH CH CH CH TEMPERATURE = C GAIN = V REF =.V V IN = dbfs GAIN ERROR (%) CH CH CH CH CH CH CH CH TEMPERATURE = C GAIN = V REF =.V V IN = dbfs AVDDx SUPPLY (V) AVDDx SUPPLY (V) 8- Figure. Gain Error vs. AVDDx Supply, High Resolution Mode Figure. Gain Error vs. AVDDx Supply, Low Power Mode GAIN ERROR (%) AVDDx =.V V REF =.V V IN = dbfs CH CH CH CH CH CH CH CH GAIN ERROR (%) AVDDx =.V V REF =.V V IN = dbfs CH CH CH CH CH CH CH CH TEMPERATURE ( C) Figure. Gain Error vs. Temperature, High Resolution Mode 8-. TEMPERATURE ( C) Figure. Gain Error vs. Temperature, Low Power Mode 8- Rev. Page of 98

27 Data Sheet AD GAIN ERROR (%) TEMPERATURE = C AVDDx =.V V REF =.V V IN = dbfs HIGH RESOLUTION LOW POWER REFERENCE VOLTAGE DRIFT (mv). 8 PGA GAIN Figure 8. Channel Gain Mismatch 8-8 TEMPERATURE ( C) Figure. Internal Reference Voltage Drift 8- TUE AS % OF INPUT CH CH.8 CH CH CH CH CH CH. 8 9 TEMPERATURE ( C) V REF =.V V IN =.dbfs SUPPLY = AVDDx =.V Figure 9. Total Unadjusted Error (TUE) (as Percent of Input) vs. Temperature, High Resolution Mode 8-9 TUE AS % OF INPUT V CH CH REF =.V V CH CH IN =.dbfs CH CH SUPPLY = AVDDx =.V CH CH TEMPERATURE ( C) Figure. Total Unadjusted Error (TUE) (as Percent of Input) vs. Temperature, Low Power Mode 8- AINx+, V CM =.9V AINx, V CM =.9V AINx+; V CM =.V AINx, V CM =.V..8. AINx+, V CM =.9V AINx, V CM =.9V AINx+; V CM =.V AINx, V CM =.V INPUT CURRENT (na) INPUT CURRENT (na).... V REF =.V SUPPLY = AVDDx =.V DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) 8-. V REF =.V SUPPLY = AVDDx =.V DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) 8- Figure. Input Current vs. Differential Input Voltage, High Resolution Mode Figure. Input Current vs. Differential Input Voltage, Low Power Mode Rev. Page of 98

28 AD Data Sheet ABSOLUTE INPUT CURRENT (na) AIN+ AIN AIN+ AIN V REF =.V V IN =.V SUPPLY = AVDDx =.V 8 TEMPERATURE ( C) Figure. Absolute Input Current vs. Temperature, High Resolution Mode 8- ABSOLUTE INPUT CURRENT (na) AIN+ AIN AIN+ AIN V REF =.V V IN =.V SUPPLY = AVDDx =.V 8 8 TEMPERATURE ( C) Figure. Absolute Input Current vs. Temperature, Low Power Mode 8- DIFFERENTIAL INPUT CURRENT (na) AINx+ AINx, V CM =.9V AINx+ AINx, V CM =.V V REF =.V SUPPLY = AVDDx =.V DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) Figure. Differential Input Current vs. Differential Input Voltage, High Resolution Mode 8- DIFFERENTIAL INPUT CURRENT (na) AINx+ AINx, V CM =.9V AINx+ AINx, V CM =.V.8 V REF =.V SUPPLY = AVDDx =.V DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) Figure 8. Differential Input Current vs. Differential Input Voltage, Low Power Mode 8-8 DIFFERENTIAL INPUT CURRENT (na) 8 V REF =.V V IN =.V SUPPLY = AVDDx =.V DIFFERENTIAL INPUT CURRENT (na) 8 V REF =.V V IN =.V SUPPLY = AVDDx =.V 8 TEMPERATURE ( C) Figure. Differential Input Current vs. Temperature, High Resolution Mode 8-8 TEMPERATURE ( C) Figure 9. Differential Input Current vs. Temperature, Low Power Mode 8-9 Rev. Page 8 of 98

29 Data Sheet AD GAIN = GAIN = GAIN = GAIN = 8 V CM =.V + mv p-p SUPPLY = AVDDx =.V + mv p-p GAIN = GAIN = GAIN = GAIN = 8 V CM =.V + mv p-p SUPPLY = AVDDx =.V + mv p-p CMRR (db) 8 CMRR (db) INPUT FREQUENCY (Hz) Figure 8. CMRR vs. Input Frequency at 8 ksps, High Resolution Mode INPUT FREQUENCY (Hz) Figure 8. CMRR vs. Input Frequency at ksps, Low Power Mode 8-8 AC PSR (db) GAIN = GAIN = GAIN = GAIN = 8 T A = C SUPPLY = AVDDx =.V+mVpp INPUT FREQUENCY(Hz) Figure 8. AC PSRR vs. Input Frequency at 8 ksps, High Resolution Mode 8-8 AC PSR (db) GAIN = GAIN = GAIN = GAIN = T A = C SUPPLY = AVDDx =.V + mv p-p INPUT FREQUENCY(Hz) Figure 8. AC PSRR vs. Input Frequency at ksps, Low Power Mode 8-8 ATTENUATION (db) 8 9 GAIN = GAIN = GAIN = GAIN = 8 ATTENUATION (db) 8 9 GAIN = GAIN = GAIN = GAIN = FREQUENCY (Hz) Figure 8. Filter Profiles at ksps, High Resolution Mode FREQUENCY (Hz) Figure 8. Filter Profiles at ksps, Low Power Mode 8-8 Rev. Page 9 of 98

30 AD Data Sheet 8 AVDDx AVDDx AVDD IOVDD AVDDx AVDDx AVDD IOVDD SUPPLY CURRENT (ma) 8 SUPPLY CURRENT (ma) SUPPLY VOLTAGE (V) Figure 8. Supply Current vs. Supply Voltage, High Resolution Mode SUPPLY VOLTAGE (V) Figure 89. Supply Current vs. Supply Voltage, Low Power Mode 8-89 AVDDx AVDDx AVDD IOVDD AVDDx AVDDx AVDD IOVDD SUPPLY CURRENT (ma) SUPPLY CURRENT (ma) 8 TEMPERATURE ( C) Figure 8. Supply Current vs. Temperature High Resolution Mode TEMPERATURE ( C) Figure 9. Supply Current vs. Temperature Low Power Mode 8-9 REFERENCE INPUT CURRENT (na) 8 8 REF REF+ REF REF TEMPERATURE ( C) Figure 88. Reference Input Current vs. Temperature, High Resolution Mode 8-88 REFERENCE INPUT CURRENT (na) REF REF+ REF REF TEMPERATURE ( C) Figure 9. Reference Input Current vs. Temperature, Low Power Mode 8-9 Rev. Page of 98

31 Data Sheet AD SHUTDOWN SUPPLY CURRENT (µa) 8 AVDDx AVDDx AVDD IOVDD SUPPLY VOLTAGE (V) Figure 9. Shutdown Supply Current vs. Supply Voltage 8-9 SHUTDOWN SUPPLY CURRENT (µa) AVDDx AVDDx AVDD IOVDD 8 TEMPERATURE ( C) Figure 9. Shutdown Supply Current vs. Temperature 8-9 POWER CONSUMPTION (mw) AVDDx AVDDx AVDD IOVDD POWER CONSUMPTION (mw) 8 8 AVDDx AVDDx AVDD IOVDD SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 8-9 Figure 9. Power Consumption per Channel vs. Supply Voltage, High Resolution Mode Figure 9. Power Consumption per Channel vs. Supply Voltage, Low Power Mode POWER DISSIPATION (mw) 9 8 AVDDx AVDDx AVDD IOVDD POWER DISSIPATION (mw) AVDDx AVDDx AVDD IOVDD 8 TEMPERATURE ( C) Figure 9. Power Dissipation vs. Temperature, High Resolution Mode TEMPERATURE ( C) Figure 9. Power Dissipation vs. Temperature, Low Power Mode 8-9 Rev. Page of 98