8-Channel, 24-Bit, Simultaneous Sampling ADC AD7779

Transcription

1 FEATURES 8-channel, -bit simultaneous sampling analog-to-digital converter (ADC) Single-ended or true differential inputs Programmable gain amplifier (PGA) per channel (gains of,,, and 8) Low dc input current: ± na Up to ksps output data rate (ODR) per channel Programmable ODRs and bandwidth Sample rate converter (SRC) for coherent sampling Sampling rate resolution up to. μsps Low latency sinc filter path Adjustable phase synchronization Internal. V reference Two power modes High resolution mode Low power mode Optimizes power dissipation and performance Low resolution successive approximation (SAR) ADC for system and chip diagnostics Power supply Bipolar (±. V) or unipolar (. V) supplies Digital input/output (I/O) supply:.8 V to. V Performance temperature range: C to + C Functional temperature range: C to + C Performance Combined ac and dc performance 8 db signal-to-noise ratio (SNR)/dynamic range at ksps in high resolution mode 9 db total harmonic distortion (THD) ± ppm integral nonlinearity (INL) ± μv offset error ±.% gain error ± ppm/ C typical temperature coefficient APPLICATIONS Circuit breakers General-purpose data acquisition Electroencephalography (EEG) Industrial process control GENERAL DESCRIPTION The AD9 is an 8-channel, simultaneous sampling ADC. There are eight full sigma-delta (Σ-Δ) ADCs on chip. The AD9 provides an ultralow input current to allow direct sensor connection. Each input channel has a programmable gain stage allowing gains of,,, and 8 to map lower amplitude sensor outputs into the full-scale ADC input range, maximizing the Rev. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 8-Channel, -Bit, Simultaneous Sampling ADC AD9 dynamic range of the signal chain. The AD9 accepts VREF from V up to. V. The analog inputs accept unipolar ( V to VREF) or true bipolar (±VREF/ V) analog input signals with. V or ±. V analog supply voltages, respectively. The analog inputs can be configured to accept true differential or single-ended signals to match different sensor output configurations. Each channel contains an ADC modulator and a sinc, low latency digital filter. An SRC is provided to allow fine resolution control over the AD9 ODR. This control can be used in applications where the ODR resolution is required to maintain coherency with. Hz changes in the line frequency. The SRC is programmable through the serial port interface (SPI). The AD9 implements two different interfaces: a data output interface and SPI control interface. The ADC data output interface is dedicated to transmitting the ADC conversion results from the AD9 to the processor. The SPI interface is used to write to and read from the AD9 configuration registers and for the control and reading of data from the SAR ADC. The SPI interface can also be configured to output the Σ-Δ conversion data. The AD9 includes a -bit SAR ADC. This ADC can be used for AD9 diagnostics without having to decommission one of the Σ-Δ ADC channels dedicated to system measurement functions. With the use of an external multiplexer, which can be controlled through the three general-purpose inputs/outputs pins (GPIOs), and signal conditioning, the SAR ADC can be used to validate the Σ-Δ ADC measurements in applications where functional safety is required. In addition, the AD9 SAR ADC includes as an internal multiplexer to sense internal nodes. The AD9 contains a. V reference and reference buffer. The reference has a typical temperature coefficient of ppm/ C. The AD9 offers two modes of operation: high resolution mode and low power mode. High resolution mode provides a higher dynamic range while consuming. mw per channel; low power mode consumes just. mw per channel at a reduced dynamic range specification. The specified operating temperature range is C to + C, although the device is operational up to + C. Note that throughout this data sheet, certain terms are used to refer to either the multifunction pins or a range of pins. The multifunction pins, such as DCLK/SDO, are referred to either by the entire pin name or by a single function of the pin, for example, DCLK, when only that function is relevant. In the case of ranges of pins, AVSSx refers to the following pins: AVSSA, AVSSB, AVSSA, AVSSB, AVSS, and AVSS. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 8.9. Analog Devices, Inc. All rights reserved. Technical Support

2 AD9 TABLE OF CONTENTS Features... Applications... General Description... Revision History... Functional Block Diagram... Specifications... DOUTx Timing Characterististics... 9 SPI Timing Characterististics... Synchronization Pins and Reset Timing Characteristics... SAR ADC Timing Characterististics... GPIO SRC Update Timing Characterististics... Absolute Maximum Ratings... Thermal Resistance... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... Terminology... RMS Noise and Resolution... High Resolution Mode... Low Power Mode... Theory of Operation... Analog Inputs... Transfer Function... Core Signal Chain... Capacitive PGA... Internal Reference and Reference Buffers... Integrated LDOs... Clocking and Sampling... Digital Reset and Synchronization Pins... Digital Filtering... Shutdown Mode... Controlling the AD9... Pin Control Mode... SPI Control... 9 Digital SPI Interface... Diagnostics and Monitoring... Self Diagnostics Error... Monitoring Using the AD9 SAR ADC (SPI Control Mode)... Σ-Δ ADC Diagnostics (SPI Control Mode)... 8 Data Sheet -Δ Output Data... 9 ADC Conversion Output Header and Data... 9 Sample Rate Converter (SRC) (SPI COntrol MOde)... Data Output Interface... Calculating the CRC Checksum... Register Summary... Register Details... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Channel Configuration Register... Disable Clocks to ADC Channel Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... Channel Sync Offset Register... General User Configuration Register... General User Configuration Register... 8 General User Configuration Register... 9 Data Output Format Register... 9 Main ADC Meter and Reference Mux Control Register... Global Diagnostics Mux Register... GPIO Configuration Register... GPIO Data Register... Buffer Configuration Register... Buffer Configuration Register... Channel Offset Upper Byte Register... Channel Offset Middle Byte Register... Channel Offset Lower Byte Register... Channel Gain Upper Byte Register... Channel Gain Middle Byte Register... Channel Gain Lower Byte Register... Rev. Page of 9

3 Channel Offset Upper Byte Register... Channel Offset Middle Byte Register... Channel Offset Lower Byte Register... Channel Gain Upper Byte Register... Channel Gain Middle Byte Register... Channel Gain Lower Byte Register... Channel Offset Upper Byte Register... Channel Offset Middle Byte Register... Channel Offset Lower Byte Register... Channel Gain Upper Byte Register... Channel Gain Middle Byte Register... Channel Gain Lower Byte Register... Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 9 Channel Gain Lower Byte Register... 9 Channel Offset Upper Byte Register... 9 Channel Offset Middle Byte Register... 9 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 AD9 Channel Gain Lower Byte Register... 8 Channel Offset Upper Byte Register... 8 Channel Offset Middle Byte Register... 8 Channel Offset Lower Byte Register... 8 Channel Gain Upper Byte Register... 8 Channel Gain Middle Byte Register... 8 Channel Gain Lower Byte Register... 8 Channel Status Register... 8 Channel Status Register... 8 Channel Status Register... 8 Channel Status Register... 8 Channel Status Register... 8 Channel Status Register Channel Status Register Channel Status Register Channel /Channel DSP Errors Register Channel /Channel DSP Errors Register... 9 Channel /Channel DSP Errors Register... 9 Channel /Channel DSP Errors Register... 9 Channel to Channel Error Register Enable Register... 9 General Errors Register... 9 General Errors Register Enable... 9 General Errors Register... 9 General Errors Register Enable... 9 Error Status Register... 9 Error Status Register... 9 Error Status Register... 9 Decimation Rate (N) MSB Register... 9 Decimation Rate (N) LSB Register... 9 Decimation Rate (IF) MSB Register... 9 Decimation Rate (IF) LSB Register... 9 SRC Load Source and Load Update Register... 9 Outline Dimensions... 9 Ordering Guide... 9 REVISION HISTORY / Revision : Initial Version Rev. Page of 9

4 AD9 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDDx REF_OUT REFx+ REFx AVDD AREGxCAP IOVDD DREGCAP VCM AIN+ AIN AIN+ AIN AIN+ AIN 8mV p-p EXT_REF INT_REF REFERENCES REFERENCES COMMON- MODE VOLTAGE.V REF PGA PGA PGA Σ- ADC Σ- ADC Σ- ADC SINC/ SRC FILTER SINC/ SRC FILTER SINC/ SRC FILTER ANALOG LDO GAIN OFFSET GAIN OFFSET GAIN OFFSET DIGITAL LDO REGISTER MAP AND LOGIC CONTROL CLOCK MANAGER DATA OUTPUT INTERFACE XTAL XTAL/MCLK SYNC_IN SYNC_OUT START DCLK DRDY DOUT DOUT DOUT DOUT RESET AIN+ AIN AIN+ AIN REFERENCES REFERENCES PGA PGA Σ- ADC Σ- ADC SINC/ SRC FILTER SINC/ SRC FILTER GAIN OFFSET GAIN OFFSET HARDWARE MODE CONFIGURATION FORMAT FORMAT MODE/ALERT MODE/GPIO MODE/GPIO MODE/GPIO AIN+ AIN AIN+ AIN REFERENCES REFERENCES PGA PGA Σ- ADC Σ- ADC SINC/ SRC FILTER SINC/ SRC FILTER GAIN OFFSET GAIN OFFSET SPI INTERFACE ALERT/CS DCLK/SCLK DCLK/SDI DCLK/SDO AIN+ AIN REFERENCES PGA Σ- ADC SINC/ SRC FILTER GAIN OFFSET AUXAIN+ AUXAIN AD9 SAR ADC DIAGNOSTIC INPUTS AVSSx AVDD CONVST_SAR Figure. 9- Rev. Page of 9

5 AD9 SPECIFICATIONS AVDDx = +. V, AVSSx =. V (dual supply operation), AVDDx =. V, AVSSx = AGND (single-supply operation), AVDDx AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V AVSSx (internal/external), master clock (MCLK) = 89 khz for high resolution mode and 9 khz for low power mode, ODR = khz for high resolution mode and khz for low power mode; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUTS Differential Input Voltage Range VREF = (REFx+ REFx ) ±VREF/PGAGAIN V Single-Ended Input Voltage Range to VREF/PGAGAIN V AINx± Common-Mode Input AVSSx +. (AVDDx + AVDDx. V Range AVSSx)/ Absolute AINx± Voltage Limits AVSSx +. AVDDx. DC Input Current Single-Ended HP, MCLK = 89 khz ± na Low power mode, MCLK = ±. na 9 khz Differential HP, MCLK = 89 khz ±. na Low power mode, MCLK = ±. na 9 khz Input Current Drift pa/ C AC Input Capacitance 8 pf PGA Gain Settings,,, or 8 Bandwidth Small signal, high resolution MHz mode Small signal, low power mode khz Large signal, high resolution khz mode Large signal, low power mode. khz REFERENCE Internal Initial Accuracy REF_OUT, TA = C..%.. +.% V Temperature Coefficient ± ppm/ C Reference Load Current, IL + ma DC Power Supply Rejection Line regulation 9 db Load Regulation, VOUT/ IL μv/ma Voltage Noise en p-p,. Hz to Hz.8 μv rms Voltage Noise Density en, khz,. V reference. nv/ Hz Turn On Settling Time nf. ms External Input Voltage VREF = (REFx+ REFx ). AVDDx V Buffer Headroom AVSSx +. AVDDx. REFx Input Voltage AVSSx AVDDx REFx+ V Average REFx± Input Current Current per channel Reference buffer disabled, 8 μa/v high resolution mode Reference buffer precharge na/v mode (pre-q), high resolution mode Reference buffer disabled,. μa/v low power mode Reference buffer pre-q, low power mode na/v Rev. Page of 9

6 AD9 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Reference buffer enabled, na/v high resolution mode Reference buffer enabled, na/v low power mode TEMPERATURE RANGE Specified Performance TMIN to TMAX + C Functional TMIN to TMAX + C TEMPERATURE SENSOR Accuracy ± C DIGITAL FILTER RESPONSE (SINC) Group Delay See the SRC Group Delay section Settling Time See the Settling Time section Pass Band. db See the SRC Bandwidth section db See the SRC Bandwidth section Decimation Rate High resolution mode Low power mode 9.99 CLOCK SOURCE Frequency High resolution mode. 8.9 MHz Low power mode..9 MHz Duty Cycle : : : % Σ-Δ ADC Speed and Performance Resolution Bits Output Data Rate (ODR) High resolution mode ksps Low power mode 8 ksps No Missing Codes Bits AC Accuracy Dynamic Range Shorted inputs, PGAGAIN = ksps High resolution mode 8 db ksps High resolution mode db Low power mode db ksps Low power mode db THD. dbfs, high resolution mode 9 db. dbfs, low power mode db SINAD fin = Hz db SFDR High resolution mode, ksps, db PGAGAIN = Intermodulation Distortion fa = Hz, fb = Hz, high db (IMD) resolution mode fa = Hz, fb = Hz, low power db mode DC Power Supply Rejection AVDDx =. V 9 db DC Common-Mode Rejection Ratio 8 db Crosstalk db Rev. Page of 9

7 AD9 Parameter Test Conditions/Comments Min Typ Max Unit DC ACCURACY INL Endpoint method, PGAGAIN = ± ± ppm of FSR Other PGA gains ± ± ppm of FSR Offset Error ± ± μv Offset Error Drift ±. μv/ C vs. time μv/ hrs Offset Matching μv Gain Error ±. % FS Gain Drift vs. Temperature PGAGAIN = ± ppm/ C Gain Matching ±. % SAR ADC Speed and Performance Resolution Bits Analog Input Range AVSS +. AVDD. V Analog Input Common-Mode AVSS +. (AVDD + AVDD. V Range AVSS)/ Analog Input Leakage Current ± na Throughput ksps DC Accuracy Differential mode INL. LSB DNL No missing codes (-bit).99 + LSB Offset LSB Gain LSB AC Performance SNR khz db THD khz 8 db VCM PIN Output (AVDDx + V AVSSx)/ Load Current, IL ma Load Regulation, VOUT/ IL mv/ma Short-Circuit Current ma LOGIC INPUTS Input High Voltage, VIH. IOVDD V Input Low Voltage, VIL. V Hysteresis. V Input Currents + μa LOGIC OUTPUTS Output High Voltage, VOH IOVDD V, ISOURCE = ma.8 IOVDD V. IOVDD < V, ISOURCE = μa.8 IOVDD V IOVDD <. V, ISOURCE = μa.8 IOVDD V Output Low Voltage, VOL IOVDD V, ISINK = ma. V. IOVDD < V, ISINK = ma. V IOVDD <. V, ISINK = μa. V Leakage Current Floating state + μa Output Capacitance Floating state pf Σ-Δ ADC Data Output Coding Twos complement SAR ADC Data Output Coding Binary Rev. Page of 9

8 AD9 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLIES All Σ-Δ channels enabled AVDDx AVSSx.. V IAVDDx, Reference buffer pre-q, VCM enabled, internal reference enabled High resolution mode. ma Low power mode.. ma Reference buffer enabled, VCM enabled, internal reference enabled High resolution mode 9. ma Low power mode.8 ma Reference buffer disabled, VCM disabled, internal reference disabled High resolution mode.8 ma Low power mode..8 ma AVDDx AVSSx.. V IAVDDx High resolution mode 9 9. ma Low power mode.. ma AVDD AVSSx AVDDx AVDDx V. IAVDD SAR enabled. ma SAR disabled μa AVSSxv DGND.8 V IOVDD DGND.8. V IIOVDD High resolution mode 8. ma Low power mode. ma Power Dissipation Internal buffers bypassed, internal reference disabled, internal oscillator disabled, SAR disabled High Resolution Mode ksps 8 mw Low Power Mode ksps mw Power-Down All ADCs disabled μw AVSSx is used to refer to the following pins: AVSSA, AVSSB, AVSSB, and AVSSA. This term is used throughout the data sheet. At temperatures higher than C, the device can be operated normally, though slight degradation on the maximum/minimum specifications is expected because these specifications are only guaranteed up to C. See the Typical Performance Characteristics section for plots showing the typical performance of the device at high temperatures. The SDO pin and the DOUTx pin are configured in the default mode of strength. AVDDx =. V, AVSSx = GND = ground, IOVDD =.8 V, CMOS clock. Disabling either the VCM pin or the internal reference results in a μa typical current consumption reduction. Power dissipation is calculated using the maximum supply voltage,. V. Rev. Page 8 of 9

9 AD9 DOUTx TIMING CHARACTERISTISTICS AVDDx/AVSSx = ±. V,. V/AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V internal/external, MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Test Conditions/Comments Min Typ Max Unit t MCLK Frequency :. 8.9 MHz t MCLK Low Time ns t MCLK High Time ns t DCLKx High Time MCLK/ ns t DCLKx Low Time MCLK/ ns t MCLK Falling Edge to DCLK Rising Edge ns t MCLK Falling Edge to DCLK Falling Edge ns t8 DCLKx Rising Edge to DRDY Rising Edge ns t9 DCLKx Rising Edge to DRDY Falling Edge ns t DOUTx Setup Time ns t DOUTx Hold Time ns All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. t t t MCLK DCLK t t t t t 8 t 9 DRDY DOUTx LSB MSB MSB LSB + LSB t t 9- Figure. Data Interface Timing Diagram Rev. Page 9 of 9

10 AD9 Data Sheet SPI TIMING CHARACTERISTISTICS AVDDx/AVSSx = ±. V,. V/AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Test Conditions/Comments Min Typ Max Unit t SCLK Period : MHz t SCLK Low Time ns t SCLK High Time ns t SCLK Rising Edge to CS Falling Edge ns t CS Falling Edge to SCLK Rising Edge ns t SCLK Rising Edge to CS Rising Edge ns t8 CS Rising Edge to SCLK Rising Edge ns t9 Minimum CS High Time ns t SDI Setup Time ns t SDI Hold Time ns ta CS Falling Edge to SDO Enable (SPI = Mode ) ns tb SCLK Falling Edge to SDO Enable (SPI = Mode ) 9 ns t SDO Setup Time ns t SDO Hold Time ns t CS Rising Edge to SDO Disable ns All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. t 9 CS t t t t t t 8 SCLK t t SDI MSB MSB LSB + LSB t A t SDO MSB MSB LSB + LSB t B t t Figure. SPI Control Interface Timing Diagram t 9- Rev. Page of 9

11 AD9 SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS AVDDx/AVSSx = ±. V,. V/AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Test Conditions/Comments Min Typ Max Unit t START Setup Time ns t START Hold Time MCLK ns t8 MCLK Falling Edge to SYNC_OUT Falling Edge MCLK ns t9 SYNC_IN Setup Time ns t SYNC_IN Hold Time MCLK ns tinit_sync_in SYNC_IN Rising Edge to First DRDY ksps, HP mode μs tinit_reset RESET Rising Edge to First DRDY ksps, HP mode μs t RESET Hold Time MCLK ns tpower_up Start Time tpower_up is not shown in Figure ms All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. MCLK START t t SYNC_OUT SYNC_IN t 8 DRDY t 9 t t INIT_SYNC_IN RESET t t INIT_RESET 9- Figure. Synchronization Pins and Reset Control Interface Timing Diagram Rev. Page of 9

12 AD9 Data Sheet SAR ADC TIMING CHARACTERISTISTICS AVDDx/AVSSx = ±. V,. V/AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications at TMIN to TMAX, unless otherwise noted. Table. Parameter Description Min Typ Max Unit t Conversion Time. μs t Acquisition Time ns t Delay Time ns t Throughput Data ksps All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. Direct mode enabled. If deglitch mode is enabled, add./mclk. CS t t t CONVST_SAR t Figure. SAR ADC Timing Diagram 9- GPIO SRC UPDATE TIMING CHARACTERISTISTICS AVDDx/AVSSx = ±. V,. V/AGND, AVDD AVSSx =. V to. V; IOVDD =.8 V to. V; DGND = V, REFx+/REFx =. V (internal/external), MCLK = 89 khz; all specifications TMIN to TMAX, unless otherwise noted. Table. Parameter Description Min Typ Max Unit t GPIO Setup Time ns GPIO Hold Time t High Resolution Mode MCLK ns t Low Power Mode MCLK t8 MCLK Rising Edge to GPIO Rising Edge Time ns t9 GPIO Setup Time ns t GPIO Hold Time MCLK ns All input signals are specified with tr = tf = ns/v (% to 9% of IOVDD) and timed from a voltage level of (VIL + VIH)/. MCLK GPIO t t GPIO GPIO t 8 t 9 t Figure. GPIOs for SRC Update Timing Diagram 9- Rev. Page of 9

13 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Any Supply Pin to AVSSx. V to +.9 V AVSSx to DGND.98 V to +. V AREGxCAP to AVSSx. V to +.98 V DREGCAP to DGND. V to +.98 V IOVDD to DGND. V to +.9 V IOVDD to AVSSx. V to +.9 V AVDD to AVSSx AVDDx. V to.9 V Analog Input Voltage AVSSx. V to AVDDx +. V or.9 V (whichever is less) REFx± Input Voltage AVSSx. V to AVDDx +. V or.9 V (whichever is less) AUXAIN± AVSSx. V to AVDD +. V or.9v (whichever is less) Digital Input Voltage to DGND DGND. V to IOVDD +. V or.9 V (whichever is less) Digital Output Voltage to DGND DGND. V to IOVDD +. V or.9 V (whichever is less) XTAL to DGND DGND. V to DREGCAP +. V or.98 V (whichever is less) AINx±, AUXAIN±, and ± ma Digital Input Current Operating Temperature C to + C Range Junction Temperature, C TJ Maximum Storage Temperature Range C to + C Reflow Soldering C ESD kv Field Induced Charged V Device Model (FICDM) AD9 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 8. Thermal Resistance Package Type θja θjb ΨJT ΨJB Unit -Lead LFCSP No Thermal Vias. N/A..9 C/W 9 Thermal Vias C/W Thermal impedance simulated values are based on a JEDEC SP thermal test board. See JEDEC JESD. N/A means not applicable. ESD CAUTION Rev. Page of 9

14 AD9 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9 TOP VIEW (Not to Scale) CONVST_SAR ALERT/CS DCLK/SCLK DCLK/SDI DCLK/SDO DGND DREGCAP IOVDD DOUT DOUT DOUT DOUT DCLK DRDY XTAL XTAL/MCLK AUXAIN AUXAIN+ AVDD AVSS AVSSA AREGCAP AVDDA VCM CLK_SEL FORMAT FORMAT AVSS AVDDB AREGCAP AVSSB REF_OUT AIN AIN+ AIN AIN+ AVSSA AVDDA REF REF+ 8 9 AIN AIN+ AIN AIN+ MODE/GPIO MODE/GPIO MODE/GPIO MODE/ALERT 8 AIN AIN+ AIN AIN+ AVSSB AVDDB REF REF+ AIN 9 AIN+ 8 AIN AIN+ RESET SYNC_IN SYNC_OUT START NOTES. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AVSSx. Figure. Pin Configuration 9- Table 9. Pin Function Descriptions Pin No. Mnemonic Type Direction Description AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. AVSSA Supply Supply Negative Front-End Analog Supply for Channel to Channel, Typical at. V (Dual Supply) and AGND (Single Supply). Connect all the AVSSx pins to the same potential. AVDDA Supply Supply Positive Front-End Analog Supply for Channel to Channel, Typical at AVSSx +. V. Connect this pin to AVDDB. REF Reference Input Negative Reference Input for Channel to Channel, Typical at AVSSx. Connect all the REFx pins to the same potential. 8 REF+ Reference Input Positive Reference Input for Channel to Channel, Typical at REF +. V. 9 AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. MODE/GPIO Digital I/O I/O Mode Input Pin in Pin Control Mode (MODE). See Table 8 for more details. Configurable General-Purpose Input/Output in SPI Control Mode (GPIO). If not in use, connect this pin to DGND or IOVDD. MODE/GPIO Digital I/O I/O Mode Input Pin in Pin Control Mode (MODE). See Table 8 for more details. Configurable General-Purpose Input/Output in SPI Control Mode (GPIO). If not in use, connect this pin to DGND or IOVDD. MODE/GPIO Digital I/O I/O Mode Input Pin in Pin Control Mode (MODE). See Table 8 for more details. Configurable General-Purpose Input/Output in SPI Control Mode (GPIO). If not in use, connect this pin to DGND or IOVDD. MODE/ALERT Digital I/O I/O Mode Input Pin in Pin Control Mode (MODE). See Table 8 for more details. Alert Output Pin in SPI Control Mode (ALERT). CONVST_SAR Digital input Input Σ-Δ Output Interface Selection Pin in Pin Control Mode. See Table for more details. This pin also functions as the start for the SAR conversion in SPI control mode. Rev. Page of 9

15 AD9 Pin No. Mnemonic Type Direction Description 8 ALERT/CS Digital input Input Alert Output Pin in Pin Control Mode (ALERT). Chip Select Pin in SPI Control Mode (CS). 9 DCLK/SCLK Digital input Input DCLK Frequency Selection Pin in Pin Control Mode (DCLK). See Table 9 for more details. SPI Clock in SPI Control Mode (SCLK). DCLK/SDI Digital input Input DCLK Frequency Selection Pin in Pin Control Mode (DCLK). See Table 9 for more details. SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the device is configured in pin control mode with the SPI as the data output interface. DCLK/SDO Digital output Output DCLK Frequency Selection Pin in Pin Control Mode (DCLK). See Table 9 for more details. SPI Data Output in SPI Control Mode (SDO). DGND Supply Supply Digital Ground. DREGCAP Supply Output Digital LDO Output. Decouple this pin to DGND with a μf capacitor. IOVDD Supply Supply Digital Levels Input/Output and Digital LDO (DLDO) Supply from.8 V to. V. IOVDD must not be lower than DREGCAP. DOUT Digital output I/O Data Output Pin. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. DOUT Digital output I/O Data Output Pin. If the device is configured in daisy-chain mode, this pin acts as an input pin. See the Daisy-Chain Mode section for more details. DOUT Digital output Output Data Output Pin. 8 DOUT Digital output Output Data Output Pin. 9 DCLK Digital output Output Data Output Clock. DRDY Digital output Output Data Output Ready Pin. XTAL Clock Input Crystal Input Connection. If CMOS is used as a clock source, tie this pin to DGND. See Table for more details. XTAL/MCLK Clock Input Crystal Input Connection (XTAL). See Table for more details. CMOS Clock (MCLK). See Table for more details. START Digital input Input Synchronization Pulse. This pin is used to synchronize internally an external START asynchronous pulse with MCLK. The synchronize signal is shift out by the SYNC_OUT pin. If not in use, tie this pin to DGND. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details. SYNC_OUT Digital output Input Synchronization Signal. This pin generates a synchronous pulse generated and driven by hardware (via the START pin) or by software (GENERAL_USER_ CONFIG_, Bit ). If this pin is in use, it must be wired to the SYNC_IN pin. See the Phase Adjustment and the Digital Reset and Synchronization Pins section for more details. SYNC_IN Digital input Input Reset for the Internal Digital Block and Synchronize for Multiple Devices. See the Digital Reset and Synchronization Pins section for more details. RESET Digital input Input Asynchronous Reset Pin. This pin resets all registers to their default value. It is recommended to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block. AIN+ Analog input Input Analog Input Channel, Positive. 8 AIN Analog input Input Analog Input Channel, Negative. 9 AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. REF+ Reference Input Positive Reference Input for Channel to Channel, Typical at REF +. V. REF Reference Input Negative Reference Input for Channel to Channel, Typical at AVSSx. Connect all the REFx pins to the same potential. AVDDB Supply Supply Positive Front-End Analog Supply for Channel to Channel. Connect this pin to AVDDA. AVSSB Supply Supply Negative Front-End Analog Supply for Channel to Channel, typical at. V (Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins together. AIN+ Analog input Input Analog Input Channel, Positive. AIN Analog input Input Analog Input Channel, Negative. AIN+ Analog input Input Analog Input Channel, Positive. 8 AIN Analog input Input Analog Input Channel, Negative. Rev. Page of 9

16 AD9 Data Sheet Pin No. Mnemonic Type Direction Description 9 REF_OUT Reference Output. V Reference Output. Connect a nf capacitor on this pin if using the internal reference. AVSSB Supply Supply Negative Analog Supply. Connect all the AVSSx pins together. AREGCAP Supply Output Analog LDO Output. Decouple this pin to AVSSB with a μf capacitor. AVDDB Supply Supply Positive Analog Supply. Connect this pin to AVDDA. AVSS Supply Supply Negative Analog Ground. Connect all the AVSSx pins together. FORMAT Digital input Input Output Data Frame. See Table for more details. FORMAT Digital input Input Output Data Frame. See Table for more details. CLK_SEL Digital input Input Select Clock Source. See Table for more details. VCM Analog Output Common-Mode Voltage Output, Typical at (AVDD + AVSSx)/. output 8 AVDDA Supply Input Analog Supply from. V to. V. AVSSx must not be lower than AREGxCAP. Connect this pin to AVDDB. 9 AREGCAP Supply Output Analog LDO Output. Decouple this pin to AVSS with a μf capacitor. AVSSA Supply Input Negative Analog supply. Connect all the AVSSx pins together. AVSS Supply Supply Negative SAR Analog Supply and Reference. Connect all AVSSx pins together. AVDD Supply Supply Positive SAR Analog Supply and Reference Source. AUXAIN+ Analog input Input Positive SAR Analog Input Channel. AUXAIN Analog input Input Negative SAR Analog Input Channel. EPAD Supply Input Exposed Pad. Connect the exposed pad to AVSSx. Rev. Page of 9

17 AD9 TYPICAL PERFORMANCE CHARACTERISTICS 8 TEMPERATURE = C GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) 8 TEMPERATURE = C GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) INL (ppm) CH CH CH CH CH CH CH CH INL (ppm) CH CH CH CH CH CH CH CH INPUT VOLTAGE (V) Figure 8. INL vs. Input Voltage and Channel at 8 ksps, High Resolution Mode, AVSSx (VCM is the Voltage on the VCM Pin) INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and Channel at ksps, Low Power Mode, AVSSx 9-9 TEMPERATURE = C V REF =.V DIFFERENTIAL V IN GAIN V CM = (AVDDx + AVSSx) 8 TEMPERATURE = C DIFFERENTIAL V IN GAIN V REF =.V V CM = (AVDDx + AVSSx) INL (ppm) GAIN = GAIN = GAIN = GAIN = 8 INL (ppm) GAIN = GAIN = GAIN = GAIN = INPUT VOLTAGE (V) Figure 9. INL vs. Input Voltage and PGA Gain at 8 ksps, High Resolution Mode, AVSSx INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and PGA Gain at ksps, Low Power Mode, AVSSx 9- INL (ppm) GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) T A = C T A = + C T A = + C T A = + C INL (ppm) 8 8 GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V V CM = (AVDDx + AVSSx) T A = C T A = + C T A = + C T A = + C INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and Temperature at 8 ksps, High Resolution Mode, AVSSx INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and Temperature at ksps, High Resolution Mode, AVSSx 9- Rev. Page of 9

18 AD9 Data Sheet TEMPERATURE = C GAIN = DIFFERENTIAL INPUT SIGNAL V CM = (AVDDx + AVSSx) TEMPERATURE = C GAIN = DIFFERENTIAL INPUT SIGNAL V CM = (AVDDx + AVSSx) INL (ppm) V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V INL (ppm) V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V V REF =.V INPUT VOLTAGE (V) INPUT VOLTAGE (V) 9- Figure. INL vs. Input Voltage and Reference Voltage (VREF) at 8 ksps, High Resolution Mode, AVSSx Figure. INL vs. Input Voltage and Reference Voltage (VREF) at ksps, Low Power Mode, AVSSx 8 TEMPERATURE = C GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V 8 TEMPERATURE = C GAIN = DIFFERENTIAL INPUT SIGNAL V REF =.V INL (ppm) V CM =.V V CM =.V V CM =.9V INL (ppm) V CM =.V V CM =.V V CM =.9V INPUT VOLTAGE (V) Figure. INL vs. Input Voltage and VCM at 8 ksps, High Resolution Mode INPUT VOLTAGE (V) Figure 8. INL vs. Input Voltage and VCM at ksps, Low Power Mode 9-8 SAMPLE COUNT 8 8 V REF =.V V CM = (AVDDx + AVSSx) TEMPERATURE = C GAIN = GAIN = GAIN = GAIN = 8 SAMPLE CODE 8 8 V REF =.V V CM = (AVDDx + AVSSx) TEMPERATURE = C GAIN = GAIN = GAIN = GAIN = ADC CODE Figure. Noise Histogram at 8 ksps, High Resolution Mode ADC CODE Figure 9. Noise Histogram at ksps, Low Power Mode 9- Rev. Page 8 of 9

19 AD V REF =.V V CM = (AVDDx + AVSSx) 8 V REF =.V V CM = (AVDDx + AVSSx) NOISE (µv rms)... NOISE (µv rms)... GAIN = GAIN = GAIN = GAIN = 8 GAIN = GAIN = GAIN = GAIN = 8 TEMPERATURE ( C) Figure. Noise vs. Temperature at 8 ksps, High Resolution Mode 9- TEMPERATURE ( C) Figure. Noise vs Temperature at ksps, Low Power Mode 9-9. NOISE (µv rms) GAIN = GAIN = GAIN = GAIN = 8 V REF =.V V CM =(AVDDx+AVSSx) TEMPERATURE = C DECIMATION = CLOCK FREQUENCY (Hz) Figure. Noise vs. Clock Frequency, High Resolution Mode, Decimation = 9- NOISE (µv rms) GAIN = GAIN = GAIN = GAIN = 8 V REF =.V V CM =(AVDDx+AVSSx) TEMPERATURE = C DECIMATION = CLOCK FREQUENCY (Hz) Figure. Noise vs. Clock Frequency at ksps, Low Power Mode, Decimation = 9- NOISE (nv/ Hz) 8 GAIN = GAIN = GAIN = GAIN = 8 NOISE (nv/ Hz) GAIN = GAIN = GAIN = GAIN = 8 8 ODR (Hz) ODR (Hz) 9-98 Figure. Noise vs. ODR, High Resolution Mode Figure. Noise vs. ODR, Low Power Mode Rev. Page 9 of 9

20 AD9 Data Sheet AMPLITUDE (db) V REF =.V TEMPERATURE = C DIFFERENTIAL INPUT =.dbfs V CM = (AVDDx + AVSSx) INPUT FREQUENCY = Hz 8 SAMPLES ksps GAIN = GAIN = GAIN = GAIN = FREQUENCY (Hz) Figure. FFT Plot at ksps, High Resolution Mode, Input Frequency (fin) = Hz, AVSSx (This Plot is a Close Up Perspective of the Original Data) AMPLITUDE (db) V REF =.V TEMPERATURE = C DIFFERENTIAL INPUT =.dbfs V CM = (AVDDx + AVSSx) INPUT FREQUENCY = khz 8 SAMPLES ksps GAIN = GAIN = GAIN = GAIN = FREQUENCY (Hz) Figure. FFT Plot, High Resolution Mode, Input Frequency (fin) = khz, AVSSx V IN =.dbfs V REF =.V TEMPERATURE = C 9-9- AMPLITUDE (db) V REF =.V TEMPERATURE = C DIFFERENTIAL INPUT =.dbfs V CM = (AVDDx + AVSSx) INPUT FREQUENCY = Hz 89 SAMPLES ksps GAIN = GAIN = GAIN = GAIN = FREQUENCY (Hz) Figure 9. FFT Plot, Low Power Mode, Input Frequency (fin) = Hz, 89 Samples, AVSSx (This Plot is a Close Up Perspective of the Original Data) AMPLITUDE (db) FREQUENCY (Hz) V REF =.V TEMPERATURE = C DIFFERENTIAL INPUT =.dbfs V CM = (AVDDx + AVSSx) INPUT FREQUENCY = khz 89 SAMPLES ksps GAIN = GAIN = GAIN = GAIN = 8 Figure. FFT Plot, Low Power Mode, Input Frequency (fin) = khz, 89 Samples, AVSSx V IN =.dbfs V REF =.V TEMPERATURE = C 9-9- THD (db) GAIN = GAIN = GAIN = GAIN = 8 THD (db) GAIN = GAIN = GAIN = GAIN = INPUT FREQUENCY (Hz) Figure 8. THD vs. Input Frequency at 8 ksps, High Resolution Mode INPUT FREQUENCY (Hz) Figure. THD vs. Input Frequency at ksps, Low Power Mode 9- Rev. Page of 9

21 AD9 THD (db) GAIN = GAIN = GAIN = GAIN = 8 INPUT FREQUENCY = Hz V REF =.V TEMPERATURE = C THD (db) INPUT FREQUENCY = Hz V REF =.V TEMPERATURE = C GAIN = GAIN = GAIN = GAIN = INPUT VOLTAGE (V) Figure. THD vs. Input Voltage at ksps, High Resolution Mode (Input Frequency = Hz) INPUT VOLTAGE (V) Figure. THD vs. Input Voltage at SPS, Low Power Mode 9 9- THD (db) 9 INPUT FREQUENCY = Hz INPUT VOLTAGE = ±V REF TEMPERATURE = C GAIN = GAIN = GAIN = GAIN = 8 THD (db) 9 INPUT FREQUENCY = Hz INPUT VOLTAGE = V p-p TEMPERATURE = C GAIN = GAIN = GAIN = GAIN = REFERENCE VOLTAGE (V) Figure. THD vs. Reference Voltage at 8 ksps, High Resolution Mode (Input Frequency = Hz) REFERENCE VOLTAGE (V) Figure. THD vs. Reference Voltage at ksps, Low Power Mode (Input Frequency = Hz) 9- THD (db) 8 INPUT FREQUENCY = Hz V REF =.V INPUT VOLTAGE =.dbfs TEMPERATURE = C DECIMATION = GAIN = GAIN = GAIN = GAIN = 8 THD (db) 8 INPUT FREQUENCY = Hz V REF =.V INPUT VOLTAGE = V p-p TEMPERATURE = C DECIMATION = GAIN = GAIN = GAIN = GAIN = MCLK FREQUENCY (Hz) Figure. THD vs. MCLK Frequency, High Resolution Mode, Input Frequency (fin) = Hz, Decimation = FREQUENCY (Hz) Figure. THD vs. MCLK Frequency, Low Power Mode, Input Frequency (fin) = Hz, Decimation = 9- Rev. Page of 9

22 AD9 Data Sheet GAIN = GAIN = GAIN = GAIN = 8 INPUT FREQUENCY = Hz V IN = dbfs V REF =.V INPUT VOLTAGE = V p-p TEMPERATURE = C SNR (db) 9 9 V IN =dbfs V REF =.V TEMPERATURE = C SNR (db) 9 9 GAIN = GAIN = GAIN = GAIN = ODR (khz) Figure 8. SNR vs. ODR at 8 ksps, High Resolution Mode (AVDDx =. V, AVSS =.8 V, IOVDD =. V) ODR (khz) Figure. SNR vs. ODR at ksps, Low Power Mode (AVDDx =. V, AVSS =.8 V, IOVDD =. V) 9- GAIN = GAIN = GAIN = GAIN = 8 GAIN = GAIN = GAIN = GAIN = 8 DYNAMIC RANGE (db) 9 8 DYNAMIC RANGE (db) PGA GAIN Figure 9. Dynamic Range vs. PGA Gain, High Resolution Mode, ODR = 8 ksps 9-89 PGA GAIN Figure. Dynamic Range vs. PGA Gain, Low Power Mode, ODR = ksps 9-9 OFFSET ERROR (µv) TEMPERATURE = C V IN =V V REF =.V AVDDx =.V CH CH CH CH CH CH CH CH 8 PGA GAIN Figure. Offset Error vs. PGA Gain, High Resolution Mode, AVDDx =. V 9- OFFSET ERROR (µv) TEMPERATURE = C V IN =V V REF =.V AVDDx =.V CH CH CH CH CH CH CH CH 8 PGA GAIN Figure. Offset Error vs. PGA Gain, Low Power Mode, AVDDx =. V 9- Rev. Page of 9

23 AD9 OFFSET ERROR (µv) GAIN = GAIN = GAIN = GAIN = 8 TEMPERATURE = C V IN =V V REF =.V OFFSET ERROR (µv) TEMPERATURE = C V IN = V V REF =.V GAIN = GAIN = GAIN = GAIN = 8... SUPPLY SETTING Figure. Offset Error vs. Supply Setting, High Resolution Mode SUPPLY SETTING Figure. Offset Error vs. Supply Setting, Low Power Mode 9- AVDDx =.V OFFSET DRIFT (µv) CH CH CH CH CH CH CH CH GAIN ERROR DRIFT (ppm) TEMPERATURE ( C) Figure. Offset Drift vs. Temperature, AVDDx =. V 9- TIME (Hours) Figure 8. Gain Error Drift vs. Time 9-8 GAIN ERROR (%) CH CH CH CH CH CH CH CH TEMPERATURE = C GAIN = GAIN ERROR (%) CH CH CH CH CH CH CH CH TEMPERATURE = C GAIN = AVDDx SUPPLY (V) Figure. Gain Error vs. AVDDx Supply, High Resolution Mode AVDDx SUPPLY (V) Figure 9. Gain Error vs. AVDDx Supply, Low Power Mode 9-9 Rev. Page of 9

24 AD9 Data Sheet GAIN ERROR (%) AVDDx =.V CH CH CH CH CH CH CH CH GAIN ERROR (%) AVDDx =.V CH CH CH CH CH CH CH CH TEMPERATURE ( C) Figure. Gain Error vs Temperature, High Resolution Mode, AVDDx =. V 9-. TEMPERATURE ( C) Figure. Gain Error vs. Temperature, Low Power Mode, AVDDx =. V 9- GAIN ERROR (%) TEMPERATURE = C AVDDx =.V HIGH RESOLUTION LOW POWER REFERENCE VOLTAGE DRIFT (mv)..... UNIT UNIT UNIT UNIT UNIT UNIT UNIT 8 PGA GAIN Figure. Channel Gain Mismatch, High Resolution Mode, AVDDx =. V TEMPERATURE ( C) Figure. Internal Reference Voltage Drift TUE (% OF INPUT)... V REF =.V V IN =.dbfs GAIN = AVDDx =.V TUE (% OF INPUT).8... V REF =.V V IN =.dbfs GAIN = AVDDx =.V TEMPERATURE ( C) Figure. Total Unadjusted Error (TUE) (as % of Input) vs. Temperature, High Resolution Mode, AVDDx =. V TEMPERATURE ( C) Figure. TUE (as % of Input) vs. Temperature, Low Power Mode, AVDDx =. V 9-8 Rev. Page of 9

25 AD9 INPUT CURRFENT (na) AINx+ V CM =.9V AINx V CM =.9V AINx+ V CM =.V AINx V CM =.V. V REF =.V V IN =.V AVDD =.V DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) Figure. Input Current vs. Differential Input Voltage, High Resolution Mode 9- INPUT CURRENT (na) V REF =.V V IN =.V AVDDx =.V AINx+ V CM =.9V AINx V CM =.9V AINx+ V CM =.V AINx V CM =.V DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) Figure 9. Input Current vs. Differential Input Voltage, Low Power Mode 9-9 ABSOLUTE INPUT CURRENT (na) V REF =.V V IN =.V AVDDx =.V AIN+ AIN AIN+ AIN ABSOLUTE INPUT CURRENT (na) V REF =.V V IN =.V AVDDx =.V AIN+ AIN AIN+ AIN TEMPERATURE ( C) Figure. Absolute Input Current vs. Temperature, High Resolution Mode TEMPERATURE ( C) Figure. Absolute Input Current vs. Temperature, Low Power Mode DIFFERENTIAL INPUT CURRENT (na) AINx+ AINx V CM =.9V AINx+ AINx V CM =.V V REF =.V V IN =.V AVDDx =.V DIFFERENTIAL INPUT CURRENT (na) AINx+ AINx V CM =.9V AINx+ AINx V CM =.V DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) Figure 8. Differential Input Current vs. Differential Input Voltage, High Resolution Mode DIFFERENTIAL INPUT VOLTAGE ((AINx+) (AINx )) Figure. Differential Input Current vs. Differential Input Voltage, Low Power Mode 9-9 Rev. Page of 9

26 AD9 Data Sheet 8 DIFFERENTIAL INPUT CURRENT (na) 9 8 CH CH CH CH CH CH CH CH V REF =.V V IN =.V AVDDx =.V DIFFERENTIAL INPUT CURRENT (na) CH CH CH CH CH CH CH CH V REF =.V V IN =.V AVDDx =.V TEMPERATURE ( C) Figure. Differential Input Current vs. Temperature, High Resolution Mode TEMPERATURE ( C) Figure. Differential Input Current vs. Temperature, Low Power Mode 9-9 CMRR (db) 8 9. GAIN GAIN GAIN GAIN INPUT FREQUENCY (Hz) AVDDx =.V V CM =.V + mv p-p Figure. CMRR vs. Input Frequency at 8 ksps, High Resolution Mode, AVDDx =. V, VCM =. V + mv p-p 9- CMRR (db) 8 9 GAIN GAIN GAIN GAIN INPUT FREQUENCY (Hz) AVDDx =.V V CM =.V + mv p-p Figure. CMRR vs. Input Frequency at ksps, Low Power Mode, AVDDx =. V, VCM =. V + mv p-p GAIN GAIN GAIN GAIN 8 TEMPERATURE = C AVDDx =.V + mv p-p GAIN GAIN GAIN GAIN 8 TEMPERATURE = C AVDDx =.V + mv p-p AC PSRR (db) 8 AC PSRR (db) 8 V CM =.V + mv p-p INPUT FREQUENCY (Hz) Figure. AC PSRR vs. Input Frequency at 8 ksps, High Resolution Mode, AVDDx =. V + mv p-p INPUT FREQUENCY (Hz) Figure. AC PSRR vs. Input Frequency at ksps, Low Power Mode, AVDDx =. V + mv p-p Rev. Page of 9

27 AD9 ATTENUATION (db) 8 GAIN = GAIN = GAIN = GAIN = 8 ATTENUATION (db) GAIN = GAIN = GAIN = GAIN = FREQUENCY (Hz) Figure 8. Filter Profiles at 8 ksps, High Resolution Mode FREQUENCY (Hz) Figure. Filter Profiles at ksps, Low Power Mode 9-8 SUPPLY CURRENT (ma) 8 8 AVDD AVDD AVDD IOVDD ALL CHANNELS ENABLED SUPPLY CURRENT (ma) AVDD AVDD AVDD IOVDD ALL CHANNELS ENABLED SUPPLY VOLTAGE (V) Figure 9. Supply Current vs. Supply Voltage at 8 ksps, High Resolution Mode SUPPLY VOLTAGE (V) Figure. Supply Current vs. Supply Voltage at ksps, Low Power Mode 9- AVDD AVDD AVDD IOVDD ALL CHANNELS ENABLED AVDD AVDD AVDD IOVDD ALL CHANNELS ENABLED SUPPLY CURRENT (ma) SUPPLY CURRENT (ma) 8 TEMPERATURE ( C) Figure. Supply Current vs. Temperature at 8 ksps, High Resolution Mode TEMPERATURE ( C) Figure. Supply Current vs. Temperature at ksps, Low Power Mode 9- Rev. Page of 9

28 AD9 Data Sheet 8 REFERENCE INPUT CURRENT (na) REF REF+ REF REF+ REFERENCE INPUT CURRENT (na) REF REF+ REF REF TEMPERATURE ( C) Figure. Reference Input Current vs. Temperature, High Resolution Mode TEMPERATURE ( C) Figure. Reference Input Current vs. Temperature, Low Power Mode SHUTDOWN SUPPLY CURRENT (µa) AVDD AVDD AVDD IOVDD SHUTDOWN SUPPLY CURRENT (µa) AVDD AVDD AVDD IOVDD SUPPLY VOLATGE (V) Figure. Shutdown Supply Current vs. Supply Voltage 9-8 TEMPERATURE ( C) Figure 8. Shutdown Supply Current vs. Temperature 9-8 AVDD AVDD AVDD AVDD AVDD AVDD POWER CONSUMPTION (mw) POWER CONSUMPTION (mw) SUPPLY VOLTAGE (V) Figure. Power Consumption per Channel vs. Supply Voltage at 8 ksps, High Resolution Mode SUPPLY VOLTAGE (V) Figure 9. Power Consumption per Channel vs. Supply Voltage at ksps, Low Power Mode 9- Rev. Page 8 of 9

29 AD9 POWER DISSIPATION (mw) 9 8 AVDD AVDD AVDD POWER DISSIPATION (mw) AVDD AVDD AVDD 8 TEMPERATURE ( C) Figure 8. Power Dissipation vs. Temperature at 8 ksps, High Resolution Mode 9-8 TEMPERATURE ( C) Figure 8. Power Dissipation vs. Temperature at ksps, Low Power Mode 9- Rev. Page 9 of 9

30 AD9 TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at fullscale frequency, f, to the power of a mv p-p sine wave applied to the common-mode voltage of VIN+ and VIN at frequency, fs. CMRR (db) = log(pf/pfs) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fs, in the ADC output. Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. DNL error is often specified in terms of resolution for which no missing codes are guaranteed. Integral Nonlinearity (INL) Error Integral noninearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is a level ½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Dynamic Range Dynamic range is the ratio of the rms value of the full-scale input signal to the rms noise measured for an input. The value for dynamic range is expressed in decibels. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale frequency sweep sine wave signal to all seven nonselected input channels and determining how much that signal is attenuated in the selected channel. The figure is given for worst case scenarios across all eight channels of the AD9. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa and nfb, where m, n =,,,, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to. For example, the second-order terms include (fa + fb) and (fa fb), and the third-order terms include (fa + fb), (fa fb), (fa + fb), and (fa fb). The AD9 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the secondorder terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels. Gain Error The first transition (from to ) occurs at a level ½ LSB above nominal negative full scale (.9999 V for Data Sheet the ±. V range). The last transition (from to ) occurs for an analog voltage ½ LSB below the nominal full scale (.9999 V for the ±.V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain Error Drift Gain error drift is the ratio of the gain error change due to a temperature change of C and the full-scale range ( N ). It is expressed in parts per million. Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is V REF LSB (V) = N The LSB referred to the input is VREF PGA LSB (VIN) = GAIN N Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in the power supply voltage from the nominal value. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal (including harmonics). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Offset Error Offset error is the difference between the ideal midscale input voltage ( V) and the actual voltage producing the midscale output code. Offset Error Drift Offset error drift is the ratio of the offset error change due to a temperature change of C and the full-scale code range ( N ). It is expressed in μv/ C. Rev. Page of 9