12-/14-/16-Bit, 2Msps, Dual Simultaneous Sampling SAR ADCs with Internal Reference MAX11192/MAX11195/ MAX General Description

Transcription

1 EALUATION KIT AAILABLE MAX9/MAX95/ General Description The MAX9/MAX95/ is a dual-channel SAR ADCs with simultaneous sampling at Msps, -/4- /6-bit resolution, and differential inputs. Available in a tiny 6-pin, 3mm x mm ultra TDFN package, this ADC delivers excellent static and dynamic performance while operating from a supply voltage over the range of 3. to 5.5. An integrated reference further reduces board area and component count. The MAX9/MAX95/ output conversion data using an SPI-compatible serial interface with a dual DOUT bus. Specifications apply over the extended industrial temperature range of -4 C to +5 C. Applications Encoders Resolvers LDT Current Sensing in Motors PLC Benefits and Features Tiny 6-Pin, 3mm x mm, TDFN Package Up to Msps Throughput Rate Two Simultaneous-Sampling ADC Cores.5 Integrated Reference and Reference Buffers Two Data Outputs for the Two Simultaneous- Sampling ADCs No Overhead Clock Cycles; /4/6 Clock Cycles for -/4-/6-Bit Result Balanced, Differential Input Range of ± REF Ordering Information appears at end of data sheet. Application Diagram 3.3 TO TO 3.6 MAX9 MAX95 μ F μ F REF.5 x REF REF.5 x REF REF.5 x REF REF.5 x REF Ω 7.5Ω 7.5Ω 7.5Ω nf CG nf CG ADD AIN+ AIN- AIN+ AIN- REFIN/OUT ODD AGND OGND SAR ADC DOUT CNST SCLK SAR ADC DOUT REF REF REFGND DUAL SPI INTERFACE μ F μ F μ F 9-8; Rev ; 9/7

2 Absolute Maximum Ratings ADD to GND, REFGND, OGND to +5.5 ODD to GND, REFGND, OGND to +5.5 AINn+, AINn- to GND, REFGND, OGND to The lower of ( ADD +.3) and +5.5 REFIN, REF, REF to GND, REFGND, OGND to The lower of ( ADD +.3) and +5.5 CNST, SCLK, DOUT, DOUT to OGND to The lower of ( ODD +.3) and +5.5 GND to REFGND to OGND to +.3 Maximum Current Into Any Pin... -5mA to +5mA Continuous Power Dissipation (6 TDFN; T A = +7 C; derate 6.7mW/ C above +7 C) ( )...333mW Operating Temperature Range...-4 C to 5 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)... +3ºC Soldering Temperature (reflow)...+6 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information 6 TDFN PACKAGE CODE Outline Number -3 Land Pattern Number Thermal Resistance, Four-Layer Board: Junction to Ambient (θ JA ) 6 Junction to Case (θ JC ) T63CN+ For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package thermal resistances were obtained using the method described in JEDEC specification JESD5-7, using a four-layer board. For detailed information on package thermal considerations, refer to Electrical Characteristics MAX9 (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) ANALOG INPUTS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input oltage Range IN(DIFF) AINn+ AINn- ± REF Absolute Input oltage Range IN(RNG) AINn+/AINn- relative to GND -. Common-Mode Input oltage Range CMI RNG (AINn+ + AINn-)/ REF / -. ADD +. REF / +. Input Leakage Current I IN_LEAK Acquisition phase μa Input Capacitance C IN pf Maxim Integrated

3 Electrical Characteristics MAX9 (continued) (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (REFIN/OUT =.5, INTERNAL REFERENCE) Resolution N Bits No Missing Codes Bits Offset Error OE - + LSB Offset Error TC. mlsb/ C Gain Error GE (Note ) - + LSB Gain Error TC (Note ). mlsb/ C Integral Nonlinearity INL LSB Differential Nonlinearity DNL LSB Analog Input CMR CMRR Common Mode Range; REF / - m to REF / + m 75 db Power-Supply Rejection PSRR ADD 85 db Power Supply Rejection PSRR ODD 9 db INTERNAL REFERENCE Initial Accuracy T A = +5 C Temperature Drift 5 ppm EXTERNAL REFERENCE Input oltage Range REFERENCE BUFFERS External reference applied to REFIN.5 External reference applied to REF or REF.5 ADD -.5 ADD +. Bypass Capacitor. μf DYNAMIC PERFORMANCE (REFIN/OUT =.5, INTERNAL REFERENCE) Signal-to-Noise Ratio SNR khz input db Signal-to-Noise And Distortion Ratio SINAD khz input 73.5 db Spurious-Free Dynamic Range SFDR khz input db Total Harmonic Distortion khz input -8 db Crossalk khz input - db DYNAMIC PERFORMANCE (REFIN/OUT = 4.96, EXTERNAL REFERENCE) Signal-to-Noise Ratio SNR khz input db Signal-to-Noise And Distortion Ratio SINAD khz input 73.5 db Spurious-Free Dynamic Range SFDR khz input db Total Harmonic Distortion khz input -8 db Crossalk khz input - db SAMPLING DYNAMICS Throughput Msps Aperture Delay Match 5 ps Input -3db Bandwidth f -3dB 5 MHz Maxim Integrated 3

4 Electrical Characteristics MAX9 (continued) (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) POWER SUPPLIES PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Analog Supply oltage ADD Interface Supply oltage ODD Analog Supply Current I(ADD) ma Interface Supply Current I(ODD) DOUT load: C LOAD = pf.75 ma Analog Standby Current I S (ADD) (Note 3) ma Interface Standby Current I S (ODD) (Note 3) μa DIGITAL INPUTS Input oltage High IH.8 x ODD Input oltage Low IL. x ODD Input Capacitance pf Input Leakage μa DIGITAL OUTPUTS Output oltage High OH I SOURCE = ma ODD -.4 Output oltage Low OL I SINK = ma TIMING OGND +.4 Conversion Period t 5 ns SCLK to DOUT Hold t ns SCLK to DOUT alid t 3 4 ns SCLK High t 4 8 ns SCLK Period t 5 ns SCLK low t 6 8 ns CNST Rising Edge to SCLK Rising Edge SCLK Rising Edge to CNST Rising Edge t 7 5 ns t 8 5 ns CNST High t 9 6 ns CNST Falling Edge to SCLK Rising Edge SCLK Falling Edge to CNST Falling Edge t ns t ns CNST Low Time for alid Sample t 4 ns Maxim Integrated 4

5 Electrical Characteristics MAX95 (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) ANALOG INPUTS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input oltage Range IN(DIFF) AINn+ AINn- ± REF Absolute Input oltage Range IN(RNG) AINn+/AINn- relative to GND -. Common-Mode Input oltage Range CMI RNG (AINn+ + AINn-)/ REF / -. ADD +. REF / +. Input Leakage Current I IN_LEAK Acquisition phase μa Input Capacitance C IN pf STATIC PERFORMANCE (REFIN/OUT =.5, INTERNAL REFERENCE) Resolution N 4 Bits No Missing Codes 4 Bits Offset Error OE LSB Offset Error TC 4 mlsb/ C Gain Error GE (Note ) LSB Gain Error TC (Note ) mlsb/ C Integral Nonlinearity INL LSB Differential Nonlinearity DNL LSB Analog Input CMR CMRR Common Mode Range; REF / - m to REF / + m 8 db Power-Supply Rejection PSRR ADD 85 db Power Supply Rejection PSRR ODD 9 db INTERNAL REFERENCE Initial Accuracy T A = +5 C Temperature Drift 5 ppm EXTERNAL REFERENCE Input oltage Range REFERENCE BUFFERS External reference applied to REFIN.5 External reference applied to REF or REF.5 ADD -.5 ADD +. Bypass Capacitor. μf DYNAMIC PERFORMANCE (REFIN/OUT =.5, INTERNAL REFERENCE) Signal-to-Noise Ratio SNR khz input db Signal-to-Noise And Distortion Ratio SINAD khz input 83.7 db Spurious-Free Dynamic Range SFDR khz input 5 db Total Harmonic Distortion khz input -7 db Crossalk khz input - db Maxim Integrated 5

6 Electrical Characteristics MAX95 (continued) (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (REFIN/OUT = 4.96, EXTERNAL REFERENCE) Signal-to-Noise Ratio SNR khz input db Signal-to-Noise And Distortion Ratio SINAD khz input 84.7 db Spurious-Free Dynamic Range SFDR khz input db Total Harmonic Distortion khz input - db Crossalk khz input - db SAMPLING DYNAMICS Throughput Msps Aperture Delay Match 5 ps Input -3db Bandwidth f -3dB 5 MHz POWER SUPPLIES Analog Supply oltage ADD Interface Supply oltage ODD Analog Supply Current I(ADD) ma Interface Supply Current I(ODD) DOUT load: C LOAD = pf.75. ma Analog Standby Current I S (ADD) (Note 3) ma Interface Standby Current I S (ODD) (Note 3) μa DIGITAL INPUTS Input oltage High IH.8 x ODD Input oltage Low IL. x ODD Input Capacitance pf Input Leakage μa DIGITAL OUTPUTS Output oltage High OH I SOURCE = ma ODD -.4 Output oltage Low OL I SINK = ma TIMING OGND +.4 Conversion Period t 5 ns SCLK to DOUT Hold t ns SCLK to DOUT alid t 3 4 ns SCLK High t 4 8 ns SCLK Period t 5 ns SCLK low t 6 8 ns CNST Rising Edge to SCLK Rising Edge t 7 5 ns Maxim Integrated 6

7 Electrical Characteristics MAX95 (continued) (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Rising Edge to CNST Rising Edge t 8 5 ns CNST High t 9 6 ns CNST Falling Edge to SCLK Rising Edge SCLK Falling Edge to CNST Falling Edge t ns t ns CNST Low Time for alid Sample t 4 ns Electrical Characteristics (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) ANALOG INPUTS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input oltage Range IN(DIFF) AINn+ AINn- ± REF Absolute Input oltage Range IN(RNG) AINn+/AINn- relative to GND -. Common-Mode Input oltage Range CMI RNG (AINn+ + AINn-)/ REF / -. ADD +. REF / +. Input Leakage Current I IN_LEAK Acquisition phase μa Input Capacitance C IN pf STATIC PERFORMANCE (REFIN/OUT =.5, INTERNAL REFERENCE) Resolution N 6 Bits No Missing Codes 6 Bits Offset Error OE LSB Offset Error TC mlsb/ C Gain Error GE (Note ) LSB Gain Error TC (Note ) 5 mlsb/ C Integral Nonlinearity INL LSB Differential Nonlinearity DNL LSB Analog Input CMR CMRR Common Mode Range; REF / - m to REF / + m 8.5 db Power-Supply Rejection PSRR ADD 85 db Power Supply Rejection PSRR ODD 9 db INTERNAL REFERENCE Initial Accuracy T A = +5 C Temperature Drift 5 ppm Maxim Integrated 7

8 Electrical Characteristics (continued) (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EXTERNAL REFERENCE Input oltage Range REFERENCE BUFFERS External reference applied to REFIN.5 External reference applied to REF or REF.5 ADD -.5 ADD +. Bypass Capacitor. μf DYNAMIC PERFORMANCE (REFIN/OUT =.5, INTERNAL REFERENCE) Signal-to-Noise Ratio SNR khz input db Signal-to-Noise And Distortion Ratio SINAD khz input 88.8 db Spurious-Free Dynamic Range SFDR khz input 5 db Total Harmonic Distortion khz input -7 db Crossalk khz input - db DYNAMIC PERFORMANCE (REFIN/OUT = 4.96, EXTERNAL REFERENCE) Signal-to-Noise Ratio SNR khz input db Signal-to-Noise And Distortion Ratio SINAD khz input 9.6 db Spurious-Free Dynamic Range SFDR khz input 4 db Total Harmonic Distortion khz input - db Crossalk khz input - db SAMPLING DYNAMICS Throughput Msps Aperture Delay Match 5 ps Input -3db Bandwidth f -3dB 5 MHz POWER SUPPLIES Analog Supply oltage ADD Interface Supply oltage ODD Analog Supply Current I(ADD) ma Interface Supply Current I(ODD) DOUT load: C LOAD = pf.75. ma Analog Standby Current I S (ADD) (Note 3) ma Interface Standby Current I S (ODD) (Note 3) μa DIGITAL INPUTS Input oltage High IH.8 x ODD. x Input oltage Low IL ODD Input Capacitance pf Input Leakage μa Maxim Integrated 8

9 Electrical Characteristics (continued) (f Sample = MSPS; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX (Note ). Typical values are at T A = +5 C, unless otherwise noted.) DIGITAL OUTPUTS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output oltage High OH I SOURCE = ma ODD -.4 Output oltage Low OL I SINK = ma TIMING OGND +.4 Conversion Period t 5 ns SCLK to DOUT Hold t ns SCLK to DOUT alid t 3 4 ns SCLK High t 4 8 ns SCLK Period t 5 ns SCLK low t 6 8 ns CNST Rising Edge to SCLK Rising Edge SCLK Rising Edge to CNST Rising Edge t 7 5 ns t 8 5 ns CNST High t 9 6 ns CNST Falling Edge to SCLK Rising Edge SCLK Falling Edge to CNST Falling Edge t ns t ns CNST Low Time for alid Sample t 4 ns Note : Units are % production tested at TA = +5 C and are guaranteed by design and characterization from T A = T MIN to T MAX. Note : Exclude the reference drift and offset error. Note 3: This current is drawn when the device has completed conversion and SCLK is idle. Maxim Integrated 9

10 Typical Operating Characteristics MAX9 (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) AND GAIN ERROR vs. TEMPERATURE toca AND GAIN ERROR vs. TEMPERATURE tocb AND GAIN ERROR vs. SUPPLY OLTAGE toca ERROR (LSB) GAIN ERROR ERROR (LSB) GAIN ERROR ERROR (LSB) GAIN ERROR SUPPLY OLTAGE() ERROR (LSB) AND GAIN ERROR vs. SUPPLY OLTAGE GAIN ERROR SUPPLY OLTAGE() tocb ERROR (LSB) AND GAIN ERROR vs. REFERENCE OLTAGE GAIN ERROR REFERENCE OLTAGE() toc3a ERROR (LSB) AND GAIN ERROR vs. REFERENCE OLTAGE GAIN ERROR REFERENCE OLTAGE() toc3b NUMBER OF OCCURRENCES OUTPUT NOISE HISTOGRAM toc4a STDEA= LSB NUMBER OF OCCURRENCES OUTPUT NOISE HISTOGRAM toc4b STDEB = LSB DNL (LSB) DNL vs. CODE toc5a OUTPUT CODE (DECIMAL) OUTPUT CODE (DECIMAL) OUTPUT CODE (DECIMAL) Maxim Integrated

11 Typical Operating Characteristics MAX9 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.). DNL vs. TEMPERATURE. DNL vs. TEMPERATURE. INL vs. TEMPERATURE MAX DNL.6.4 MAX DNL.6.4 MAX INL DNL (LSB) MIN DNL DNL (LSB) MIN DNL INL (LSB) MIN INL TEMPERATURE ( o C) TEMPERATURE ( o C) TEMPERATURE ( o C) INL vs. TEMPERATURE DNL vs. ADD SUPPLY OLTAGE DNL vs. ADD SUPPLY OLTAGE MAX INL.6.4 MAX DNL.6.4 MAX DNL INL (LSB) MIN INL DNL (LSB) MIN DNL DNL (LSB) MIN DNL TEMPERATURE ( o C) ADD SUPPLY OLTAGE () ADD SUPPLY OLTAGE () Maxim Integrated

12 Typical Operating Characteristics MAX9 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) INL (LSB) INL vs. ADD SUPPLY OLTAGE MAX INL MIN INL ADD SUPPLY OLTAGE () INL (LSB) INL vs. ADD SUPPLY OLTAGE MAX INL MIN INL ADD SUPPLY OLTAGE () (db) vs. INPUT IMPEDANCE toc CHB CHA INPUT IMPEDANCE (Ω )

13 Typical Operating Characteristics MAX9 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) SNR AND SINAD vs. FREQUENCY SNR AND SINAD vs. FREQUENCY AND SFDR vs. FREQUENCY 75 toc5a 75 toc5b 4 toc6a 74 SNR 74 SNR 3 SNR AND SINAD (db) SINAD SNR AND SINAD (db) SINAD AND SFDR (db) SFDR FREQUENCY (khz) FREQUENCY (khz) FREQUENCY (khz) AND SFDR vs. FREQUENCY SNR AND SINAD vs. TEMPERATURE SNR AND SINAD vs. TEMPERATURE 4 toc6b 75 toc7a 75 toc7b AND SFDR (db) SFDR SNR AND SINAD (db) SNR SINAD SNR AND SINAD (db) SNR SINAD FREQUENCY (khz) 7 7 AND SFDR vs. TEMPERATURE AND SFDR vs. TEMPERATURE SNR AND SINAD vs. REFERENCE OLTAGE 4 toc8a 4 toc8b 75 toc9a SNR AND SFDR (db) SFDR AND SFDR (db) SFDR SNR AND SINAD (db) SINAD REFERENCE OLTAGE () Maxim Integrated 3

14 Typical Operating Characteristics MAX9 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) SNR AND SINAD vs. REFERENCE OLTAGE AND SFDR vs. REFERENCE OLTAGE AND SFDR vs. REFERENCE OLTAGE 75 toc9b 4 toca 4 tocb SNR AND SINAD (db) SNR SINAD AND SFDR (db) SFDR AND SFDR (db) SFDR REFERENCE OLTAGE () OLTAGE REFERENCE () REFERENCE OLTAGE () PSR vs. INPUT FREQUENCY CURRENT vs. TEMPERATURE CURRENT vs. SAMPLING RATE toc 8 toc 6 toc3 PSR (db) CHA CHB INPUT FREQUENCY (khz) CURRENT (ma) 7 IADD IODD CURRENT (ma) 5 4 IADD 3 IODD.5.5 SAMPLING RATE (Msps) CURRENT (ma) ADD STANDBY CURRENT vs. TEMPERATURE IADD.6 toc4 CURRENT (ua) ODD STANDBY CURRENT vs. TEMPERATURE -.5 IODD toc5 REFERENCE OLTAGE () REFERENCE OLTAGE vs. TEMPERATURE.495 toc6 Maxim Integrated 4

15 Typical Operating Characteristics MAX95 (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) 5 AND GAIN ERROR vs. TEMPERATURE toca 5 AND GAIN ERROR vs. TEMPERATURE tocb 5 AND GAIN ERROR vs. SUPPLY OLTAGE toca ERROR (LSB) GAIN ERROR ERROR (LSB) GAIN ERROR ERROR (LSB) GAIN ERROR SUPPLY OLTAGE() 5 AND GAIN ERROR vs. SUPPLY OLTAGE tocb 5. AND GAIN ERROR vs. REFERENCE OLTAGE toc3a 5 AND GAIN ERROR vs. REFERENCE OLTAGE toc3b ERROR (LSB) GAIN ERROR ERROR (LSB) GAIN ERROR ERROR (LSB) GAIN ERROR SUPPLY OLTAGE () REFERENCE OLTAGE() REFERENCE OLTAGE() NUMBER OF OCCURRENCES OUTPUT NOISE HISTOGRAM toc4a STDEA =.3LSB NUMBER OF OCCURRENCES OUTPUT NOISE HISTOGRAM toc4b STDEB =. LSB DNL (LSB) DNL vs. CODE toc5a OUTPUT CODE (DECIMAL) OUTPUT CODE (DECIMAL) OUTPUT CODE (DECIMAL) Maxim Integrated 5

16 Typical Operating Characteristics MAX95 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) DNL (LSB) DNL vs. CODE OUTPUT CODE (DECIMAL) INL (LSB) INL vs. CODE OUTPUT CODE (DECIMAL) INL (LSB) INL vs. CODE OUTPUT CODE (DECIMAL).4 DNL vs. TEMPERATURE.4 DNL vs. TEMPERATURE toc7b.8 INL vs. TEMPERATURE DNL (LSB)... MAX DNL DNL (LSB)... MAX DNL INL (LSB).4.. MAX INL MIN DNL MIN DNL MIN INL TEMPERATURE ( o C) -.4 TEMPERATURE ( o C) -.8 TEMPERATURE ( o C).8 INL vs. TEMPERATURE.4 DNL vs. ADD SUPPLY OLTAGE.4 DNL vs. ADD SUPPLY OLTAGE toc9b MAX INL. MAX DNL. MAX DNL INL (LSB).. DNL (LSB).. DNL (LSB) MIN INL MIN DNL MIN DNL TEMPERATURE ( o C) ADD SUPPLY OLTAGE () ADD SUPPLY OLTAGE () Maxim Integrated 6

17 Typical Operating Characteristics MAX95 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.).8.6 INL vs. ADD SUPPLY OLTAGE toca.8.6 INL vs. ADD SUPPLY OLTAGE tocb 5 vs. INPUT IMPEDANCE toc CHA INL (LSB) MAX INL MIN INL INL (LSB) MAX INL MIN INL (db) CHB ADD SUPPLY OLTAGE () ADD SUPPLY OLTAGE () INPUT IMPEDANCE (Ω ) Maxim Integrated 7

18 Typical Operating Characteristics MAX95 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) SNR AND SINAD vs. FREQUENCY SNR AND SINAD vs. FREQUENCY AND SFDR vs. FREQUENCY 86 toc5a 86 toc5b 4 toc6a SNR AND SINAD (db) SNR SINAD SNR AND SINAD (db) SNR SINAD AND SFDR (db) SFDR FREQUENCY (khz) FREQUENCY (khz) FREQUENCY (khz) AND SFDR vs. FREQUENCY SNR AND SINAD vs. TEMPERATURE SNR AND SINAD vs. TEMPERATURE 4 toc6b 86 toc7a 86 toc7b AND SFDR (db) SFDR SNR AND SINAD (db) SNR SINAD SNR AND SINAD (db) SNR SINAD FREQUENCY (khz) 8 8 AND SFDR vs. TEMPERATURE AND SFDR vs. TEMPERATURE SNR AND SINAD vs. REFERENCE OLTAGE 4 toc8a 4 toc8b 86 toc9a AND SFDR (db) SFDR AND SFDR (db) SFDR SNR AND SINAD (db) SNR SINAD REFERENCE OLTAGE () Maxim Integrated 8

19 Typical Operating Characteristics MAX95 (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) SNR AND SINAD vs. REFERENCE OLTAGE AND SFDR vs. REFERENCE OLTAGE AND SFDR vs. REFERENCE OLTAGE 86 toc9b 4 toca 4 tocb SNR AND SINAD (db) SNR SINAD AND SFDR (db) SFDR AND SFDR (db) SFDR REFERENCE OLTAGE () OLTAGE REFERENCE () REFERENCE OLTAGE () PSR vs. INPUT FREQUENCY CURRENT vs. TEMPERATURE CURRENT vs. SAMPLING RATE toc 8 toc 6 toc3 PSR (db) CHA CHB INPUT FREQUENCY (khz) CURRENT (ma) 7 IADD IODD CURRENT (ma) 5 4 IADD 3 IODD.5.5 SAMPLING RATE (Msps) CURRENT (ma) ADD STANDBY CURRENT vs. TEMPERATURE IADD.6 toc4 CURRENT (µa) ODD STANDBY CURRENT vs. TEMPERATURE -.5 IODD toc5 REFERENCE OLTAGE () REFERENCE OLTAGE vs. TEMPERATURE.495 toc6 Maxim Integrated 9

20 Typical Operating Characteristics (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) AND GAIN ERROR vs. TEMPERATURE AND GAIN ERROR vs. TEMPERATURE AND GAIN ERROR vs. SUPPLY OLTAGE 5 toca 5 tocb 5 toca ERROR (LSB) 3 - GAIN ERROR ERROR (LSB) 3 - GAIN ERROR ERROR (LSB) 3 - GAIN ERROR SUPPLY OLTAGE () 5 AND GAIN ERROR vs. SUPPLY OLTAGE tocb 5. AND GAIN ERROR vs. REFERENCE OLTAGE toc3a 5 AND GAIN ERROR vs. REFERENCE OLTAGE toc3b ERROR (LSB) 3 - GAIN ERROR ERROR (LSB) ERROR (LSB) 3 - GAIN ERROR GAIN ERROR SUPPLY OLTAGE () REFERENCE OLTAGE () REFERENCE OLTAGE () NUMBER OF OCCURRENCES OUTPUT NOISE HISTOGRAM toc4a STDEA=.8 LSB NUMBER OF OCCURRENCES OUTPUT NOISE HISTOGRAM toc4b STDEB =.9LSB OUTPUT CODE (DECIMAL) OUTPUT CODE (DECIMAL) Maxim Integrated

21 Typical Operating Characteristics (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) Maxim

22 Typical Operating Characteristics (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.).8 INL vs. ADD SUPPLY OLTAGE toca.8 INL vs. ADD SUPPLY OLTAGE tocb 5 vs. INPUT IMPEDANCE toc INL (LSB) MIN INL MAX INL INL (LSB) MIN INL MAX INL (db) CHB CHA ADD SUPPLY OLTAGE () ADD SUPPLY OLTAGE () INPUT IMPEDANCE (Ω ) Maxim Integrated

23 Typical Operating Characteristics (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) SNR AND SINAD vs. FREQUENCY SNR AND SINAD vs. FREQUENCY AND SFDR vs. FREQUENCY 9 toc5a 9 toc5b 4 toc6a SNR AND SINAD (db) SNR SINAD SNR AND SINAD (db) SNR SINAD AND SFDR (db) SFDR FREQUENCY (khz) FREQUENCY (khz) FREQUENCY (khz) AND SFDR vs. FREQUENCY SNR AND SINAD vs. TEMPERATURE SNR AND SINAD vs. TEMPERATURE 4 toc6b 9 toc7a 9 toc7b AND SFDR (db) SFDR SNR AND SINAD (db) SNR SINAD SNR AND SINAD (db) SNR SINAD FREQUENCY (khz) AND SFDR vs. TEMPERATURE AND SFDR vs. TEMPERATURE SNR AND SINAD vs. REFERENCE OLTAGE 4 toc8a 4 toc8b 95 toc9a AND SFDR (db) SFDR AND SFDR (db) SFDR SNR AND SINAD (db) SNR SINAD REFERENCE OLTAGE () Maxim Integrated 3

24 Typical Operating Characteristics (continued) (f SAMPLE = Msps; ADD = 5., ODD =.8; REFIN/OUT =.5 (Internal Reference); T A = T MIN to T MAX. Typical values are at T A = +5ºC, unless otherwise noted.) 95 SNR AND SINAD vs. REFERENCE OLTAGE toc9b 4 AND SFDR vs. REFERENCE OLTAGE toca 4 AND SFDR vs. REFERENCE OLTAGE tocb SNR AND SINAD (db) SNR SINAD REFERENCE OLTAGE () AND SFDR (db) SFDR OLTAGE REFERENCE () AND SFDR (db) SFDR REFERENCE OLTAGE() PSR vs. INPUT FREQUENCY CURRENT vs. TEMPERATURE CURRENT vs. SAMPLING RATE PSR (db) CHB CHA toc CURRENT (ma) IADD toc CURRENT (ma) IADD toc3 6 5 INPUT FREQUENCY (khz) IODD IODD.5.5 SAMPLING RATE (Msps) CURRENT (ma) ADD STANDBY CURRENT vs. TEMPERATURE IADD.6 toc4 CURRENT (ua) ODD STANDBY CURRENT vs. TEMPERATURE -.5 IODD toc5 REFERENCE OLTAGE () REFERENCE OLTAGE vs. TEMPERATURE.495 toc6 Maxim Integrated 4

25 Pin Configuration TOP IEW AGND ADD AIN REFIN/OUT AIN- 3 REF AIN+ 3 REFGND MAX9 MAX95 AIN- 4 REF CNST 5 SCLK OGND ODD DOUT DOUT TDFN mm x 3mm EXPOSED PAD IS CONNECTED TO AGND Maxim Integrated 5

26 Pin Description PIN NAME FUNCTION AIN+ ADC Positive (+) Analog Input AIN- ADC Negative (-) Analog Input 3 AIN+ ADC Positive (+) Analog Input 4 AIN- ADC Negative (-) Analog Input 5 CNST Conversion Start Input 6 OGND Ground (IO Ground) 7 DOUT Serial Interface Data Out for ADC 8 DOUT Serial Interface Data Out for ADC 9 ODD IO Supply. Bypass with a μf capacitor to ground SCLK Serial Interface Clock REF REF Bypass Pin. Bypass with a μf capacitor to ground REFGND Ground (Reference Ground) 3 REF REF Bypass Pin. Bypass with a μf capacitor to ground 4 REFIN/OUT External Reference Input or Internal Reference Decoupling. Bypass with μf capacitor to ground 5 ADD Analog Supply Pin. Bypass with a μf capacitor to ground 6 AGND Ground Functional Diagram REF REF REFIN/OUT REF- BUFFER ADD +5. MAX9 MAX95 REF- BUFFER OLTAGE REFERENCE ODD +.8 AIN+ AIN- + SAR ADC Interface DOUT CNST AIN+ AIN- + SAR ADC Interface SCLK DOUT REFGND AGND OGND Maxim Integrated 6

27 Detailed Description The MAX9/MAX95/ are a family of -/4-/6-bit, -channel, Msps, SAR ADCS with simultaneous sampling, balanced differential inputs, and a separate data output for each channel. These ADCs feature best-in-class sample rate and resolution in a tiny mm x 3mm package. An integrated voltage reference and reference buffers help to minimize board space, component count, and system cost. An internal oscillator sets conversion time, thereby simplifying external timing requirements. For fast throughput, the SPI-compatible digital interface includes two data out pins (DOUT and DOUT). DOUT provides conversion data from ADC, while DOUT provides conversion data from ADC. Data bits are clocked out on the rising edge of SCLK. Analog Inputs The analog inputs of the MAX9/MAX95/, AINn+ and AINn-, should be driven with balanced differential signals. The input signals can range from to REF. Thus, the differential input interval DIFF = (AINn+) - (AINn-) ranges from REF to + REF, and the full-scale range is: FSR = REF The nominal resolution step width of the least significant bit (LSB) is: LSB = FSR N = REF N, N = /4/6 The differential analog input must be centered with respect to a common mode signal of REF /, with a tolerance of ±m. The reference voltage can range from.5 to 5m below the reference supply ADD. This will guarantee adequate headroom for the internal reference buffers. Figure illustrates signal ranges for AINn+/AINn-, reference voltage REF and reference supply voltage ADD. Figure shows the analog input equivalent circuit of MAX9/MAX95/. The ADC samples both inputs, AINn+ and AINn-, with a differential on-chip track-and-hold exhibiting no pipeline delay or latency. Each analog input (see Figure ) has dedicated input clamps to protect from overranging. Diodes D and D provide ESD protection and act as a clamp for the input voltages. Diodes D/D can sustain a maximum forward current of ma. The sampling switches connect the inputs to the sampling capacitors. ADD ADD REF + 5m ADD 5.5 AINn+ D RON 5Ω REF 5m REF 5 D CIN 7pF AINn+ ADD DC.5REF AINn- AINn- D RON 5Ω TIME D CIN 7pF Figure. Input Signal Ranges Figure. Simplified Model of Input Sampling Circuit Maxim Integrated 7

28 Input Settling Figure 3 shows the timing of the conversion cycle's track, SAR conversion, and read data operations. In the track phase, starting with the rising edge of CNST, the sample switches are closed and the analog inputs are directly connected to the sample capacitors. The source resistance determines the charging of the sample capacitor to the input voltage. The falling edge of CNST is the sampling instant for the ADCs. At this instant, the track phase ends, the sample switches open, and the ADC enters into the successive approximation (SAR) conversion phase. In the conversion phase, a comparator compares the voltage on the sample capacitor against the internal DAC value, which cycles through values of binary-weighted fractions of REF using the successive approximation technique. The final result is read through the SPI bus. Note that ADC and ADC operate in parallel and conversion data is available simultaneously through DOUT and DOUT. The ADCs go back into track phase on the rising edge of CNST. To achieve accurate conversion results, each ADC should track its input signal for an interval longer than the input signal's settling time. If the signal cannot settle within the allocated track time due to excessive source resistance, external ADC drivers are recommended to achieve faster settling. Note that, since the MAX9/ MAX95/ has a fixed conversion time set by an internal oscillator, reducing the sample rate can increase the track time. The settling behavior is determined by the time constant in the sampling network. The time constant depends upon the total resistance (source resistance + switch resistance, R ON ) and total capacitance (sampling capacitor C IN, external input capacitor, PCB parasitic capacitors, etc). Modeling the input circuit with a single pole network, the time constant, R TOTAL C LOAD, of the input should not exceed t TRACK /, where R TOTAL is the total resistance (source resistance + switch resistance), C LOAD is the total capacitance (sampling capacitor, external input capacitor, PCB parasitic capacitor), and t TRACK is the track time. When an ADC driver amplifier is used, it is recommended to use a series resistance (typically 5Ω to 5Ω) between the amplifier and the ADC inputs, as shown in the Application Diagram. The following are some of the requirements for the ADC driver amplifier. ) Fast settling time: For a multichannel multiplexed circuit,the ADC driver amplifier must be able to settle with an error less than.5 LSB during the minimum track time when a full-scale step is applied. ) Low noise: It is important to ensure that the ADC driver has a sufficiently low noise density in the bandwidth of interest. When the MAX9/MAX95/ is used with its full bandwidth of 5MHz, it is preferable to use an amplifier with an output noise spectral density of less than 6n Hz, to ensure that the overall SNR is not degraded significantly. It is recommended to insert an external RC filter at the ADC input to attenuate out-of-band input noise. 3) To take full advantage of the ADC s excellent dynamic performance, we recommend the use of ADC drivers with equal or even better performance. This will ensure that the ADC drivers do not limit distortion performance in the signal path. The ADC drivers listed in Table are all excellent choices. / SAMPLE RATE / SAMPLE RATE / SAMPLE RATE TRACK SAR CONERSION TRACK SAR CONERSION TRACK 3 SAR CONERSION 3 CNST SAMPLE SAMPLE SAMPLE 3 CLK CLK CLK CLK 3 CLK N- CLK N- CLK N CLK CLK CLK 3 CLK N- CLK N- CLK N DOUT/ MSB MSB- MSB- LSB+ LSB+ LSB MSB MSB- MSB- LSB+ LSB+ LSB READ DATA (SAMPLE ) READ DATA (SAMPLE ) Figure 3. Conversion Timing: Track, SAR Conversion, and Read Operations Maxim Integrated 8

29 Table. ADC Driver Amplifier Recommendations AMPLIFIER INPUT-NOISE DENSITY (N/ Hz) SMALL-SIGNAL BANDWIDTH (MHZ) SLEW RATE (/ΜS) (DB) ICC (MA) MAX (M) MAX MAX MAX COMMENTS Low current, low at khz High voltage.7 to, low at khz Low noise, low at khz REF REF REFIN/OUT ADD +3.3 to +5.5 REF- BUFFER REF- BUFFER OLTAGE REFERENCE ODD +.8 MAX9 MAX95 Figure 4. Internal Reference Input Filtering Noisy input signals should be filtered prior to the ADC driver amplifier input with an appropriate filter to minimize noise. The RC network shown in the Application Diagram is mainly designed to reduce the load transient seen by the amplifier when the ADC starts the track phase. This network has to satisfy the settling time requirement and provides the benefit of limiting the noise bandwidth. oltage Reference Configurations Using An Internal Reference The MAX9/MAX95/ feature a.5 integrated reference with built-in reference buffers that help to reduce component count and board space. When using internal reference, only bypass capacitors are required on the REF, REF, and REFIN/OUT pins (see Figure 4). The REF/REF pins require external bypass capacitors of at least μf. Using An External Reference To use an external reference (see Figure 5), drive the REFIN/OUT pin directly with an external reference voltage source, ensuring that the reference voltage is no greater than ADD - 5m. This will allow the on-chip reference buffers to operate with sufficient supply headroom. The REF/REF pins require external bypass capacitors of at least μf. Table lists excellent choices for low-noise, low-temperature drift external references. Transfer Function Figure 6 shows the ideal transfer characteristics for the MAX9/MAX95/. Maxim Integrated 9

30 +REF +REF +REF OLTAGE REFERENCE REF REF REFIN/OUT ADD REF +.5 TO 5.5 REF- BUFFER REF- BUFFER OLTAGE REFERENCE ODD +.8 MAX9 MAX95 Figure 5. External Reference Table. External Reference Recommendations REFERENCE INITIAL ACCURACY (%) TEMPERATURE DRIFT MAX (PPM/ C) NOISE (ΜP-P) MAX67 ± Low noise COMMENTS MAX633 ± ery low drift MAX67 ± Dual reference OUTPUT CODE (TWO S COMPLEMENT) FS -.5 x LSB LSB= x REF N N = /4/ N- - N- + - N- + N- - N- - N- IN = (AIN+)-(AIN-) DIFFERENTIAL ANALOG INPUT (LSB) x REF ZERO SCALE IN = -REF FULL SCALE (FS) IN = +REF Figure 6. Ideal ADC Transfer Characteristics Maxim Integrated 3

31 Digital Interface Conversion data may be read in the track phase, the conversion phase, or both. Outlined below are the specifics of the various ways to read conversion data. The input signals of the two ADC channels are sampled simultaneously on the falling edge of CNST and the conversion is initiated. At the end of the conversion, the ADCs go idle until the next rising edge of CNST, at which point the ADCs enter track mode. To complete a conversion, the time between CNST falling and rising edge must be at least the minimum of the conversion time t (see Figure ). The conversion data can then be read immediately after the rising edge of the next CNST pulse, which should not occur before the minimum conversion time value (t ) has elapsed. guard against digital noise from the data bus, corrupting the sample. INITIATE READ RIGHT AFTER CNST RISING EDGE / SAMPLE RATE / SAMPLE RATE / SAMPLE RATE TRACK SAR CONERSION TRACK SAR CONERSION TRACK 3 SAR CONERSION 3 CNST SAMPLE SAMPLE SAMPLE 3 CLK CLK CLK CLK 3 CLK N- CLK N- CLK N CLK CLK CLK 3 CLK N- CLK N- CLK N DOUT / MSB MSB-MSB- LSB+ LSB+ LSB MSB MSB- MSB- LSB+ LSB+ LSB READ DATA (SAMPLE ) READ DATA (SAMPLE ) Figure 7. Convert and Data Read INITIATE READ RIGHT AFTER CNST FALLING EDGE / SAMPLE RATE / SAMPLE RATE / SAMPLE RATE TRACK SAR CONERSION TRACK SAR CONERSION TRACK 3 SAR CONERSION 3 CNST SAMPLE SAMPLE SAMPLE 3 CLK CLK CLK CLK 3 CLK N- CLK N CLK CLK CLK 3 CLK N- CLK N DOUT / MSB MSB- MSB- LSB+ LSB MSB MSB- MSB- LSB+ LSB READ DATA (SAMPLE ) READ DATA (SAMPLE ) Figure 8. Reading Data After Falling Edge of CNST Maxim Integrated 3

32 / SAMPLE RATE t t CNST SAMPLE CLK CLK CLK CLK 3 CLK N- CLK N- CLK N DOUT / MSB MSB- MSB- LSB+ LSB+ LSB READ DATA (SAMPLE ) Figure 9. Convert and Data Read in a Single Conversion Period TRACK SAR CONERSION t < t / SAMPLE RATE / SAMPLE RATE TRACK CONERSION ABORTED TRACK 3 SAR CONERSION 3 CNST SAMPLE SAMPLE SAMPLE 3 CLK CLK CLK CLK 3 CLK N- CLK N- CLK N CLK CLK CLK 3 DOUT / MSB MSB- MSB- LSB+ LSB+ LSB MSB MSB- MSB- READ DATA (SAMPLE ) Figure. Conversion Abort Data Read t t9 t 7% ODD SAMPLE EDGE 7% ODD CNST t8 t7 t t t4 t6 t5 SCLK t3 7% ODD 3% ODD t DOUT/ 7% ODD Figure. Interface Timing Specifications Maxim Integrated 3

33 Applications Information Interfacing to Common Input Signals Real-world signals typically require conditioning before they can be digitized by an ADC. The following outlines common examples of analog signal processing circuits. The ADCs in the MAX9/MAX95/ accept differential input signals with unipolar common mode. Refer to vs. Input Impedance to use buffers to minimize distortion. The three following examples show input signal conditioning approaches to common signal path configurations. Differential Unipolar Input The circuit in Figure shows how amplifiers can be configured to buffer a differential unipolar input signal. Single-Ended Unipolar Input The circuit in Figure 3 shows how a single-ended, unipolar signal can interface with the MAX9/MAX95/. This signal conditioning circuit transforms a to + REF single-ended input signal to a fully differential output signal with a signal peak-to-peak amplitude of x REF and common-mode voltage of REF /. In this case, the single-ended signal source drives the high-impedance input of the first amplifier. This amplifier drives the AIN+ input, and the second stage amplifier with a peak-to-peak amplitude of REF and a common-mode output voltage of REF /. The second amplifier inverts this signal to generate AIN-, the inverted version of AIN+. Single-Ended Bipolar Input Figure 4 shows a signal conditioning circuit that transforms a - x REF to + x REF single-ended bipolar input signal to a balanced differential output signal with a peakto-peak amplitude of x REF and a common-mode voltage REF /. The single-ended bipolar input signal drives the inverting input of the first amplifier. This amplifier inverts and adds an offset to the input signal. It also drives the AIN- input and the second stage amplifier with a peak-to-peak amplitude of REF and a common-mode output voltage of REF /. The second amplifier is also in inverting configuration and drives the AIN+ input. This amplifier adds an offset to generate a signal with a peak-to-peak amplitude of REF and a common-mode output voltage of REF /. The input impedance, seen by the signal source, is determined by the input resistor of the first-stage inverting amplifier. The input impedance must be chosen carefully based on the output impedance of the signal source. 3.3 TO TO 3.6 REF - RS TO REF ADD AGND OGND ODD.5 x REF + AIN+ REF - CS COG RS AIN- SAR ADC DOUT CNST DSP.5 x REF + REF TO AIN+ AIN- SAR ADC SCLK DOUT SPI INTERFACE MAX9 MAX95 REFIN/OUT REF REF REFGND Figure. Unipolar Differential Input Maxim Integrated 33

34 3.3 TO TO 3.6 REF.5 x REF - + R - R RS CS COG RS TO REF AIN+ AIN- ADD AGND SAR ADC OGND ODD DOUT CNST DSP REF MAX9 MAX95 REF TO AIN+ AIN- REFIN/OUT SAR ADC REF REF SCLK DOUT REFGND SPI INTERFACE Figure 3. Unipolar Single-Ended Input 3.3 TO TO 3.6 R R MAX9 + x REF R - RS TO REF ADD AGND OGND ODD - x REF x REF + - 4R 4R R - + REF CS COG RS MAX9 MAX95 REF TO AIN+ AIN- AIN+ AIN- SAR ADC SAR ADC DOUT CNST SCLK DOUT DSP SPI INTERFACE REFIN/OUT REF REF REFGND Figure 4. Bipolar Single-Ended Input Maxim Integrated 34

35 Layout, Grounding, and Bypassing For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect the GND pins of the MAX9/MAX95/ to this ground plane. Keep the ground return path to the power supply low impedance and as short as possible. A nf CG ceramic chip capacitor should be placed between AINn+ and AINn- as close as possible to the MAX9/MAX95/. This capacitor reduces the voltage transient seen by the driving stage of the ADC input. For best performance, connect the REF/ output to the ground plane with a 6, μf ceramic chip capacitor with a X5R dielectric in a or smaller case size. Ensure that all bypass capacitors are connected directly into the ground plane with an independent via. Bypass ADD and ODD to the ground plane with μf ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. For best performance, bring the ADD power plane in from the analog interface side of the MAX9/MAX95/ and the ODD power plane from the digital interface side of the device. Figure 5 shows the PCB top layer of a sample layout with optimal placement of passive components. REF GND REF REFIN/ OUT ODD ADD 5 8 DOUT 6 7 DOUT GND GND AINP AINN AINP AINN Figure 5. PCB Layout Example for MAX9/MAX95/ Maxim Integrated 35

36 Ordering Information PART NUMBER RESOLUTION TEMP RANGE PIN-PACKAGE INTERNAL REFERENCE MAX9ATE+ -4 C to +5 C 6 TDFN-EP*.5 MAX9ATE+T -4 C to +5 C 6 TDFN-EP*.5 MAX95ATE+ 4-4 C to +5 C 6 TDFN-EP*.5 MAX95ATE+T 4-4 C to +5 C 6 TDFN-EP*.5 ATE+ 6-4 C to +5 C 6 TDFN-EP*.5 ATE+T 6-4 C to +5 C 6 TDFN-EP*.5 Denotes a lead(pb)-free/rohs-compliant package. T = tape and reel. *EP = Exposed Pad Maxim Integrated 36

37 Revision History REISION NUMBER REISION DATE DESCRIPTION PAGES CHANGED 4/7 Initial release 9/7 Added MAX95 and part numbers to data sheet 37 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim Integrated s website at Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 7 Maxim Integrated Products, Inc. 37