Digital Cell Macro-model with Regular Substrate Template and EKV Based MOSFET Model

Transcription

1 Digital Cell Maco-model wit Regula Substate Template and EKV Based MOSFET Model ABSTRACT Tis pape pesents substate noise maco-models fo standad digital cells like INV, NAND and BUFFER. Te macomodels ae based on a scalable substate netwok template and a simple stuctual MOSFET model equivalent to EKV model. Symbolic expessions ae deived fo te substate voltage, injection cuent and output voltage of eac pimay digital cells. Poposed models contain pysical detail of te device and pocess, teefoe tey ae valid fo diffeent pocessing tecnology and input tansition, and ae moe accuate as compaed to te maco-model geneated fom Spice simulation and cuve fitting. Ou maco-models ae accuate witin 5-% fom SPICE simulation wit te full cicuit and MOSFET model, and te simulations ae at least 4 times faste. Wit tis model we can pedict spatially and tempoally te occuence of substate noise peaks in a digital design.. INTRODUCTION Seious noise coupling poblems ae emeging in mixedsignal systems-on cip, because of te noisy natue of te digital cicuits and te low noise toleance of analog cicuits [6]. Te switcing noise geneated by digital blocks popagates toug te substate to te sensitive pats of te SOC, e.g., RF and analog cicuits, dynamic logic and memoy cicuits. Te supply and substate connection netwoks also contibute to noise geneation toug inductances of bond wies. Many otogonal factos, suc as layout geomety and pocess tecnology contibutes to te substate noise caacteistics of a design. Te tempoal (time beavio) and spacial (position of noise souces) dependencies ae bot impotant factos in noise modeling of SOC. Substate modeling tecniques based on device simulato [], Finite Diffeential Metods (FDM tat solves Poisson equations), and Bounday Element Metods (BEM tat solve Geen s functions) [8, 9] geneally acieves ig accuacy. Howeve, tey equie tedious computation and lage memoy spaces, wic ae unsuitable fo cicuit and system syntesis. As an altenative, it is beneficial to geneate substate macomodels [, 6] fo digital cells using RC elements to descibe te substate beavio. Many substate maco-models use equivalent cuent souces, called noise signatue [], to model te noise injection [4, 5, Pemission to make digital o ad copies of all o pat of tis wok fo pesonal o classoom use is ganted witout fee povided tat copies ae not made o distibuted fo pofit o commecial advantage and tat copies bea tis notice and te full citation on te fist page. To copy otewise, to epublis, to post on seves o to edistibute to lists, equies pio specific pemission and/o a fee. Copyigt X ACM X-XXXXX-XX-X/XX/XX...$5.. ]. Te noise signatue is geneated fom SPICE simulation of te digital cell and stoed as a look-up table[]. Te main disadvantage of tese metods is te equiement of cuent souce tuning to get te accuate model fo diffeent tansition time and device tecnology. Howeve, tee is no suggestion fo a geneal algoitm to contol te tuning pocess, and also tee is not muc insigt povided into te device pysics toug adjustment of te equivalent noise souces. In ode to solve te poblem, we popose noise macomodels tat pysically descibe powe/gound coupling, substate coupling, and MOSFET coupling. Te substate netwok model is based on te BEM substate extaction, but in a compact and egula topology so tat it can be easily applied to all te digital cell in te standad libay. Te MOSFET maco-model is deived symbolically fom EKV model []. Te model maintains te pysical infomation on te digital cell and is valid ove diffeent pocessing tecnology and input tansitions. Te speed of te symbolic simulation is at least 4 times ige tan SPICE simulation. Te accuacy of ou model is muc ige compaed wit digital cell macomodel witout MOSFET, and is witin 5-% fom SPICE simulation wit full digital cell model (including MOSFET). Fo compeensive cells, te maco-model can be composed of pimay cells maco-model. Te pape as te following stuctue. Section discusses te modeling and noise simulation flow. Section pesents te substate and MOSFET maco-model. Section 4 intoduces digital cell maco-model example digital cell macomodel suc as invete, nand, and buffe. Section 5 discusses simulation esults. Finally, conclusions ae povided.. MODELING AND SIMULATION FLOW A lage digital design is geneally composed of digital libay cells. To analysis te switcing noise caacteistics of a digital design, it is beneficial to setup noise maco-models fo libay cells and use te composition to get noise model of te wole design. Accuate composition is difficult to acieve, because bot te tempoal and spacial dependencies of noise injection at diffeent point of te layout needs to be undestood. In ou modeling metods, te substate netwok template povides noise spacial dependency infomation. Te tempoal noise dependency infomation is povided by te tansient analysis of te pimay cells and te composed cells. Te modeling and design flow is sown in Figue. We used standad libay cells TSMC5µm and TSMC5µm digital cell libaies []. Te substate maco-model is geneated based on te BEM layout extaction in SPACE[7]. It as a egula topology because of te same layout style and contact patten in te digital cell. Te MOSFET maco-model is deived fom EKV tansisto model. Te digital-cell macomodel is obtained toug symbolic deivation of te electical popety of te MOSFET connection, substate netwok, and powe/gound paasitics.

2 Substate Pofile Layout GDS file SPACE layout to cicuit extaction (BEM) Piece wise lineaization Piece wise Quadatic appoximation Digitalell Noise Modeling & Simulation Metodology Input Vin(t) Regulaity Based Substate Netwok Template Constuction Symbolic Digital Cell Maco modeling Tansient symbolic Simulation Output (t) Substate (t) Injection Iinj(t) Figue : Digital cell substate netwok extaction and noise simulation flow substate. Gm n = I injn = I injn I injn.. I injnn I injnn () V injn = v bnn v bnn.. v bn v bnsub () n,... ( n,n n, n ) n,..., (,,, ) P n ( i= i, ), n,n... n,n n, n B. Substate model fo pull-up netwok (p substate, n well and p diffusion): (4) We popose to implement symbolic simulation [] instead of SPICE numeical simulation in ode to educe te simulation time, memoy stoage and avoid convegency poblems by optimizing te symbolic expessions. It also povides insigt into te noise dependencies and simulation eo contol, wic is elpful fo noise modeling and noise model composition fo lage cicuits.. SUBSTRATE AND MOSFET MODELS Geneally te substate paasitic of andom cicuit design is difficult to pedict. Howeve, fo digital libay cells, te same layout style can be obseved, wic leads to a fixed substate contact patten and egula paasitic netwok topology. As an example, Figue sows te egula substate paasitic extacted fom Nand in TSMC5 digital cell libay. Tis section pesents geneal substate netwok template and extaction steps. Moe detailed infomation ae offeed in [4].. Substate netwok template Te substate template was sown in Figue. c n is te capacitance between te tansisto body to te substate node, n is te esistance between te tansisto body to te substate node, n, is te esistance between te tansisto body and te gound line substate contact. n,n is te esistance between two tansisto body nodes. We caacteized te electical beavio of tis template, and deived te following symbolic model: A. Substate model fo pull-down netwok (p substate, n diffusion): I T injn = Gm n V T injn () Wee I injn, V injn ae te substate injection cuent and voltage aays. Gm n is te geneal admittance matix fo VDD VDD I T injp = Gm pv T injp + Gm pv T injp (5) Wee I injp, V injp ae te substate injection cuent and voltage aays. Gm p, Gm p ae state vaiable admittance matix fo paasitics. Gm p = I injp = I injp I injp.. I injpn I injpn (6) V injp = v bpn v bpn.. v bp v bpsub (7) V injp = v bpn v bpn.. v bp v bpsub (8) n,... ( n,n......,, (,, + C ) P n ( i= i, + C ), n,n n, n n, + Cn ) and [Gm p] = C n C... n n... Cn (9) () C. Extaction steps: Based on te SPACE extaction esults, we concluded te following pocedues fo extacting substate paasitics of a standad digital cell: Step : Set VDD/VSS line as node in te substate netwok. Step : Numbe te NMOS/PMOS tansisto fom left to igt as to n. Iinjn, Iinjn, Iinjn, Iinjn(n), Iinjnn, Iinjpn, Iinjp(n), Iinjp, Iinjp, Iinjp, Vbp Vbp Vin Vin Vbn Figue : Nand substate netwok mapped to layout style Vbn,, n,n n n cn n,n cn,, c c c Figue : Substate noise injection netwok template

3 Gate Intinsic EKV model elemetns Souce Cgsov Cgbov Cgbi Cgsi I DS Cgdi Cdbj Cgdov Dain Vin Vin Vin Vin Vin R Seff Csbj Cdbi Cdbi R Deff Vin Vin Vin Vin Bulk G Vin Vin Vin S I D (Vg,Vs,Vd,Vb) D Vin Vin Vin Vin B Ceq(Vg,Vs,Vd,Vb) Figue 4: MOSFET maco-model deived fom EKV tansisto model[] Step : Intoduce a paasitic esistance n,n between tansisto NMOS n,nmos n o P MOS n,p MOS n. Step4 : Intoduce a paasitic esistance n, between NMOS n /P MOS n and VSS/VDD. Step5 : Intoduce a paasitic esistance n between tansisto NMOS n /P MOS n and substate node V sub.. MOSFET maco-model Te MOSFET maco-model is deived based on te EKV model [], as sown in Figue 4, and included in te deivation of te noise injection model fo eac digital cell. As compaed to SPICE -, and BSIM - [], tis model symmetically teats te souce and dain wit te substate node as te voltage efeence point, and offes invesion cage model close to device pysics. Te model uses compact fom to teat weak invesion-stong invesion tansition and te linea egion-satuation egion tansition at te same time. In ode to geneate compact digital cell noise maco-model, we deived a simplified stuctue to epesent te EKV tansisto model, wic decouples te cuent flow of te MOS- FET cannel wit te injection cuent into te body node based on MOSFET cage consevation. Figue 4 sows te EKV tansisto model and ou maco-model. Te macomodel peseves te same electical caacteistics by using compeensive expession fo te equivalent capacito. Te MOSFET cuent model I D is expessed as: I D = I S (i f i ) () I S = nβu T () vp vs i f = [ln( + e )] () vp v d i = [ln( + e )] (4) wee I S is te specific cuent. i f, i ae nomalized fowad and evese cuent, and v p, v s, v d ae nomalized pinc off voltage, souce and dain voltages []. Te MOSFET equivalent capacito is: C eq = CgsC bs + C gdc bd + C gb (5) C gs + C bs C gd + C bd wee C gs,c bs,c gd,c bd,c gb ae nonlinea paametes and tei definitions follow te EKV MOSFET model definitions in []. Tis decoupled MOSFET maco-models peseve te EKV MOSFET I-V and capacito popeties wit a simple stuctue. Teefoe it is easy to combine tem stuctually in te digital cell noise model. 4. DIGITAL CELL MACRO-MODELS Tis section discusses te deivation of maco-models fo digital cells. Examples ae sown fo pimay cells suc as a) b) Figue 5: MOSFET aay invete and nand gates. Fo compeensive cells we intoduce model composition and pesent te buffe maco-model as an example. 4. Symbolic equations fo model deivation Fo pimay cells suc as invete and nand gate, te symbolic expession of and ae deived fom te following nodal equations:. Powe/ line electical popety. fi sp = C pkgn gv (g sn I L n Ln Vsn Ṽ sn ) + R pkgn Ln gi sn = C pkgp gv (g Vsp Vsp g sp I L p Lp ) + R pkgp L p (6) (7) wee f Isp, f Isn ae total cuent into PMOS tansistos/out of NMOS tansistos. C pkgn, C pkgp, L n, L p efes to te paasitic coupling and is te tansient time step.. MOSFET connection. In ode to geneate digital cell automatically, te MOS- FET aay M as sown in Figue 5 is used as a stating topology. Te selection matix SEL P UN, SEL P DN ae used to select te MOSFET in te pull-up netwok and pull-down netwok PUN and PDN. Te composition matix COM(P UN), COM(P DN) ae used to deive te MOSFET topology in PUN and PDN, as descibed in I(PDN/PUN). Combining I(PDN/PUN) we get te digital cell topology as a cuent matix I(Total), eac line of te matix descibes te cuent flowing at one level of te topology. Te nodal equations ae deived fom I(T otal) as sown in te following Nand topology deivation example. As an example, fo Nand gate, M(P UN) = M(P DN) = SEL(P UN) = SEL(P DN) = COM(P UN) = COM(P DN) = I dp I dp I dp I dn I dn I dn (8) (9) () () () () I(P UN/P DN) = M SEL COM(P UN/P DN) (4) I(T otal) = I(P UN) I(P DN) (5) = 4 I dp I dp 5 I dn + I dn Te nodal equation fo node between MOS i,j and MOS (i+),j

4 VDD Cpkgp Vin Lpkgp Rpkgp Ceq_p VDD B A Ceqp Ceq_n Lpkgp Cpkgn Rpkgn B A Ceqn Figue 6: Invete noise injection model in te digital cell is: X j=,n I(T otal) i,j + X j=,n. Injection to substate node. I(T otal) i+,j = (6) I inj = C eqv in V in + V b V b (7) wee C eq is te equivalent capacitance of te MOSFET. V in, V in ae te input voltage, and V b, V b ae te body voltage at te beginning and te end of a tansient time step. 4. Substate netwoking. Te equation fo substate netwok is descibed in section equation ()-(). 4. Nonlinea function appoximation eo Te nonlinea MOSFET cuent model and capacito model causes difficulties in deiving symbolic expessions fo V out and V sub, and I inj. To solve te poblem we used Piece-wise Newton intepolation of te st and nd ode to make V out, V sub, I inj solvable. Te eo associated wit te piece-wise model include inte segment eo and inta segment eo. Inte-segment eo efes to te diffeence between te piece-wise segment and te oiginal function. By coosing small segment lengt (.5) tis eo is contolled witin 8. Inta-segment eo efes to te deviation fom oiginal model wit an inappopiate coice of te segment. To educe tis eo we seac exclusively ove possible segments and pick te segment tat povides te closest appoximation to te oiginal nonlinea function. 4. Pimay digital cell maco-models Te pimay digital cell maco-models is a composition of te powe/gound coupling, substate coupling and MOSFET noise injection model we discussed in Section. Figues 6 and 7 sow te maco-model of te INV and Nand cell as examples fo pimay digital cells. Tis section pesents te symbolic equations descibing te maco-model. A. Invete maco-model Te Invete maco-model can be descibed by te following nodal equations coesponds to te impotant nodes in te maco-model suc as input node, output node, substate node, and powe/gnd line node. Te notation follows equation (7)-(8). Id n + I inj = C pkgn g V sn dv out Id p Id n Cout = (8) + I Ln d g V sn L n (9) V Ln /R pkgn = I Ln g V sn + d g V sn VLn L n () dv in dg V sp dv in dv bn C eq p + C eq n = () Ṽsn + dg Vsn V sub = V bn + dv bn V sub () Figue 7: Nand noise injection model Te symbolic expession of te voltage at eac input of te substate netwok can be deived fom tese equations. Te injection cuent I inj teefoe can be obtained fom te substate netwok template as we discussed in equation () and (5). B. Nand maco-model Te Nand maco-model can be descibed by te following nodal equations coesponds to te impotant nodes in te maco-model suc as input node, output node, substate node, intemediate node in PDN and powe/gnd line node. Te notation follows equation (7)-(8), V node is te voltage at te PDN intemediate node. Id p + Id p Id n C outdv out/ = () Id n + I inj + I inj = C pkgn g V sn Id n Id n = C node dv node (4) + I Ln d g V sn L n (5) V Ln = I Ln ( V g sn + dv g sn VLn ) (6) R pkgn L n C eqp dv in dg V sp Ṽsn + dg Vsn V sub Ṽsn + d g Vsn V bn + V bn + dv bn V bn + dv bn + C eqn dv in dv bn = (7) Ṽ sn + dg Vsn V bn (8) = V bn + dv bn V sub + V bn + dv bn V sub Simila to INV cell, te symbolic expession of te voltage at eac input of te substate netwok can be deived fom tese equations. Te injection cuent I inj teefoe can be obtained fom te substate netwok template as we discussed in equation () and (5). 4.4 Composed digital cell maco-model Fo digital cell composed of pimay cells, te noise injection model can be geneated by composing te pimay cell noise maco-model electically. As an example, Figue 8 sows te maco-model a buffe cell composed by invete noise models. Te following equation descibes te composition of te invete maco-model to get te buffe model. I injn and I injn ae injection cuent fom te NMOS to te substate and tey come fom te invete noise maco-model. Similaly I injp and I injp ae injection cuent fom te PMOS to te substate and tey come fom te invete noise maco-model. Te Gm matixes in te following equations ae instantiated fom te substate netwok template pesented in equation () and (5) fo te buffe. Wit tese equations we can deive te body voltages of MOSFETs, as well as te substate noise voltage V sub fo te buffe cell.

5 VDD Vin C eq_n C eq_p C eq_n C eq_p Voltage(V) Invete tansient input/output voltage Vin tansisto tansisto Equivalent tansient cuent souce.4 Iinjp Iinjp Isp Cuent(uA) Substate noise Time tansient (ns) simulation 5 I eqv equivalent Isn Iinjn Iinjn Voltage(mV) tansisto I 4 g sn I injn 4 Figue 8: Buffe noise injection model 5 = I injn fi sp I injp 5 = I injp,,,,,,,,,, C,,,, + C +,,,, C,,,,,, C C C V bn V bn gv sn V sub V bp V bp gv sp V sub V bp V bp gv sp V sub (9) (4) 5. SIMULATION EXPERIMENTS Tis section offes noise simulation esults fo invete, nand and te buffe maco-model. 5. Simulation accuacy and speed up Te substate injection noise simulation of te invete fo MHz digital inputs wit diffeent input peak to peak tansition steps (5ps/5ps) and tecnology (.5um /.5um) was pefomed. Te noise peaks scale wit device sizes and ae appoximately invese popotional to te tansition time. Fo multiple input cicuits te noise peaks ae also elated to te input switcing combinations. Ou expeiment esult fo Nand in Figue sows tat simultaneous switcing of te inputs in te same diection poduces te lagest injection noise. Ou noise maco-model offes bette simulation esults tan models witout tansistos, as sown in Figue 9, because it consides te nonlinea tansisto paasitic capacitos and te inteactions between PMOS and NMOS duing tansitions. Compaing te symbolic tecnique wit SPICE, te diffeence is witin 5-%. Te eo contol is elated te intesegment eo and inta-segment eo of ou piece-wise appoximation, as we discussed in Section 4.. Cuently we Figue 9: Noise simulation wit equivalent cuent souce tuning compaed wit SPICE contoled te eo wit in 8 wit simulation time step =.ps.ps. Cuently we acieve 4 times speed up tan SPICE. Using composition of maco-model te simulation speed can be incease in a lage scale. Table sows tat 5% of simulation time is spent on piece-wise appoximation and segment selection, to impove te speed-up we will continue to study bette appoximation metods. Seac fo Solving Symbolic SPICE igt segment expession ( clk) ( clk) INV 5% 5% 6sec 6sec NAND 5% 5% 5sec 57sec BUF 49% 5% sec sec Table : Time on appoximations, symbolic expession solving, and total time(symbolic vs. SPICE) 5. Scalability Noise model composition is poposed fo lage cells in ode to educe te coding effot of flat model simulation. Tee ae tee metics to indicate te quality of composed model: Code Reusability ρ, Effot saving σ, and Composition eo ε: codelengt(basiccell) ρ = (4) codelengt(secondaycell) + codelengt(basiccell) codelengt(secondaycell, composition) σ = (4) codelengt(secondaycell, scatc) Composition Eo ε is elated to te basic cell eo and te substate paasitics. A buffe example is used to illustate ε. Good composition quality equies ρ, σ and ε. Te buffe noise model is composed of two symbolic INV noise injection model. Composition follows te electical popety of te buffe substate template, as sown in Figue 8. Fo ou expeiments we ave =, ρ =.95 and σ =.955, wic sows tat code eusability was vey ig and modeling effot fo buffe was lagely saved. Simulation accuacy is witin % compaed to SPICE simulation, as sown in Figue. Te souce of te eo ε BUF comes fom te eo ε INV of te invete module (capacitos in PMOS substates negligible fom layout extaction): ε BUF = (ε INV n, n n, n ε INV n, n n, n ) ; n, ( n, n n, n ) (4) ε INV and ε INV ae diffeent at eac time step because te tansition is evesed. Fo te buffe template wit n, (esults fom layout extaction): n, ε BUF [, max(ε INV, ε INV )] (44)

6 Voltage(mV) Voltage(V) Invete tansient substate noise analysis (5ps tansition) Vin symbolic symbolic Vin spice sp um symbolic.5um spice um symbolic.5um spice Voltage(mV) Voltage(V) Invete tansient substate noise analysis (5ps tansition) Vin symbolic symbolic Vin spice sp (mv) Vin a (V) Vin b (V) (V) spice symbolic spice symbolic Figue : nand substate noise simulation esult Vin/(V) Vin Voltage(mV).5um symbolic.5um spice (mv) 6 4 symbolic spice Figue : Invete substate noise fo 5ps/5ps tansition time on.5um and.5um tecnology In geneal, noise model composition saves significant effot in developing noise model fo lage digital cicuit witout losing muc accuacy povided tat good contol of simulation eo exists fo basic digital cells. Te metod is potentially capable of andling lage scale digital cicuits by ieacically building noise models. Since te spacial infomation of te substate injection point is incopoated in te substate netwok template. Using tis modelling metod we ae able to pedict te spatially and tempoally te occupance of substate noise peaks in a digital design. 6. CONCLUSION In tis pape we poposed a substate noise maco-model fo digital cell wit a substate template and an equivalent EKV MOSFET model. Symbolic expessions ae deived fo te substate voltage, injection cuent and output voltage of eac pimay digital cells. Poposed models contain pysical detail of te device and pocess, teefoe tey ae valid fo diffeent pocessing tecnology and input tansition, and ae moe accuate as compaed to te maco-model geneated fom Spice simulation and cuve fitting. Ou maco-models ae accuate witin 5-% fom SPICE simulation wit te full cicuit and MOSFET model, and te simulations ae at least 4 times faste. Te metod as potentials to pedict tempoally and spatially te occuence of substate noise peaks fo lage digital design using maco-models composed of pimay digital cell models. 7. REFERENCES [] M. Badaoglu et. al., Hig-Level Simulation of Substate Noise Geneation fom Lage Digital Cicuits wit multiple Supplies, Poc. DATE,, pp. 6-. [] R. Mugai et. al., Sensitivity-based Modeling and Metodology Fo Full-Cip Substate Noise Analysis, Poc. DATE, Figue : Buffe substate noise simulation esult [] A. Samavedam et al, A Scalabel Substate Noise Coupling Model fo Design of Mixed-Signal IC s, JSSC, Vol.5, No. 6, June. [4] J. Biaie, K. S. Kis, Pinciples of Substate Cosstalk Geneation in CMOS cicuits, IEEE Tans. CAD, Vol. 8, No.6, June, pp [5] A. Koyama et al, Switcing Well Noise Modeling and Minimization Stategy fo Digital Cicuits wit a Contollable Tesold Voltage Sceme, IEEE Tans. CAD, Vol.9, No.6,June, pp [6] X. Aagones et al, Analysis and Solutions fo Switcing Noise Coupling in Mixed-Signal ICs, Kluwe, 999. [7] N.P. van de Meijs et al, SPACE USER s Manual, May. [8] N. K. Vegese et al, Rapid Simulation of Substate Coupling Effects in Mixed-model ICs, Poc. CICC, 99, pp [9] R. Gapuey et al, Modeling and Analysis of Substate coupling in integated cicuits, Jounal of Solid-state Cicuits, Vol., No., Mac 996. [] C. Enz et al, An analytical MOS Tansisto Model Valid in All Regions of Opeation and Dedicated to Low-Voltage and Low-Cuent Applications, Analog Integated Cicuits and Signal Pocessing, Kluwe, 995. [] L. P. Huelsman, Pesonal compute symbolic analysis pogams fo undegaduate engineeing couses, Poc. ISCAS, 989, pp [] D. Foty, MOSFET modeling wit Spice, Pentence Hall, 997. [] Tanne Consulting and Engineeing Sevices, Digital Low Powe Standad Cell Libay. [4] Removed fo blind eview.