5 Key Steps To Design A Compact, High Efficiency PFC Stage Using the NCP1611

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1 5 Key Steps To Design A Compact, High Efficiency PFC Stage Using the NCP6 APPLICATION NOTE This paper describes the key steps to rapidly design a Discontinuous Conduction Mode PFC stage driven by the NCP6. The process is illustrated in a practical 60-W, universal mains application: Maximum Output Power: 60 W Rms Line Voltage Range: from 90 V to 65 V Regulation Output Voltage: 390 V Frequency Fold-back when the Line Current is less than 450 ma Introduction Housed in a SO 8 package, the NCP6 is designed to optimize the efficiency of your PFC stage throughout the load range. Incorporating protection features for rugged operation, it is ideal in systems where cost-effectiveness, reliability, low stand-by power and high efficiency are key requirements: Current Controlled Frequency Fold-back (CCFF): The circuit operates in Critical conduction Mode (CrM) when the instantaneous line current is medium or high. When this current is lower than a preset level, the frequency linearly decays to about 0 khz. CCFF maximizes the efficiency at both nominal and light loads (Note ). In particular, stand-by losses are minimized. Skip Mode: To further optimize the efficiency, the circuit skips cycles near the line zero crossing where the power transfer is particularly inefficient. If superior power factor is needed, this feature can be inhibited by forcing a minimum 0.75-V voltage. Low Start-up Current and large V CC range: The extra low start-up consumption of the B version (NCP6B) allows the use of high-impedance resistors for charging the V CC capacitor. The A version (NCP6A) is targeted in applications where the circuit is fed by an auxiliary power source. Its start-up level is lower than.5 V to allow the circuit to be powering from a -V rail. Both versions feature a large V CC operating range (9.5 V to 35 V). Fast Line/Load Transient Compensation (Dynamic Response Enhancer and Soft OVP): Due to the slow loop response of traditional PFC stages, abrupt changes in the load or in the input voltage may cause significant over or under-shoots. This circuit drastically limits these possible deviations from the regulation point. Safety Protections: NCP6 features make the PFC stage extremely robust. Among them, we can mention the Brown-Out Detection block (Note ) that stops operation when the ac line is too low and the -level Current Sensing, that forces a low duty-ratio operation mode in the event that the current exceeds 50% of the current limit which may be caused by the inductor saturation or by a short of the bypass or boost diode. Eased Manufacturing and Safety Testing: Elements of the PFC stage can be accidently shorted, badly soldered or damaged as a result of manufacturing or handling incidents, excessive operating stress or other troubles. In particular, adjacent pins of controllers can be shorted, a pin, grounded or badly connected. It is often required that such open/short situations do not cause fire, smoke nor loud noise. The NCP6 integrates enhanced functions that help address requirement, for instance, in case of an improper pin connection (including GND) or of a short of the boost or bypass diode. Application note AND906 details the behavior of a NCP6-driven PFC stage under safety tests [].. Like in FCCrM controllers, internal circuitry allows near-unity power factor even when the switching frequency is reduced.. The voltage of the Brown-out detection block input pin ( V SENSE ) is also used to detect the line range and reduce the loop gain in high-line conditions (-step feed-forward) Semiconductor Components Industries, LLC, 03 January, 03 Rev. Publication Order Number: AND906/D

2 PFC STAGE DIMENSIONING V in IL L V bulk AC Line R X Feedback V bulk R fb D zcd D EMI Filter R X C in R bo R z 4 5 V CC R zcd R ocp Q LOAD R bo R fb C z C p R FF R sence C bulk Figure. Generic Schematic Step : Define the Key Specifications f line : Line frequency. 50 Hz/60 Hz applications are targeted. Practically, they are often specified in a range of Hz and for calculations such as hold-up time, one has to factor in the lowest value specified. (V line,rms ) LL : Lowest level of the line voltage. This is the minimum rms input voltage for which the PFC stage must operate. Such a level is usually 0 % below the minimum typical voltage which could be 00 V in many countries. We will take: (V line,rms ) LL =90V. (V line,rms ) HL : Highest level for the line voltage. This is the maximum input rms voltage. It is usually 0% above the maximum typical voltage (40 V in many countries). We select: (V line,rms ) HL = 64 V. (V line,rms ) boh : Brown-out line upper threshold. The circuit prevents operation until the line rms voltage exceeds (V line,rms ) boh. The NCP6 offers a 0% hysteresis. Hence, if no specific action is taken, it will detect a brown-out situation and stop operation when the rms line voltage goes below (V line,rms ) bol that equates (90% (V line,rms ) boh ). In our application, we target: (V line,rms ) boh 90% (V line,rms ) LL 8 V (V line,rms ) bol 90% (V line,rms ) boh 73 V V out,nom : Nominal output voltage. This is the regulation level for the PFC output voltage (also designated bulk voltage). V out,nom must be higher than ( (V line,rms ) HL ). 390 V is our target value. (V out ) pk pk : Peak-to-peak output voltage ripple. This parameter is often specified as a percentage of the output voltage. It must be selected equal or lower than 8% to avoid triggering the Dynamic Response Enhancer (DRE) in normal operation. t HOLD UP : Hold-up time. This parameter specifies the amount of time the output will remain valid during line drop-out. One line cycle is typically specified. This requirement requires knowing the minimum voltage on the PFC stage output necessary for the proper operation in your application (V out,min ). We have assumed (V out,min = 350 V) is high enough to provide the downstream converter with a sufficient input voltage. P out : Output power. This is the power consumed by the PFC load. P out,max Maximum output power. This is the maximum output power level, that is, 60 W in our application. (P in,avg ) max : Maximum input power. This is the maximum power that can be absorbed from the mains in normal operation. This level is obtained at full load, low line. Assuming an efficiency of 95% in these conditions, we will use: (P in,avg ) max W 95% I line,max : Maximum line current obtained at full load, low line. P FF(%) : Line Current Threshold below which the circuit reduces the frequency (CCFF) expressed as a percentage of I line,max. If this parameter is higher than 00%, the PFC stage will permanently operates with a reduced frequency. Conversely, if P FF(%) is close to zero, the PFC stage will function in CrM (no frequency fold-back) in almost the whole power range. This parameter is normally selected in the range of 0 to 0%. Step : Power Components Selection In heavy load conditions, the NCP6 operates in Critical conduction Mode (CrM). Hence, the inductor, the

3 bulk capacitor and the power silicon devices are dimensioned as usually done with any other CrM PFC. This section does not detail this process, but simply highlights key points.. Inductor Selection The on-time of the circuit is internally limited. The power the PFC stage can deliver, depends on the inductor since L will determine the current rise for a given on-time. More specifically, the following equation gives the power capability of the PFC stage: (P in,avg ) HL V line,rms T on,max (eq. ) L The smaller the inductor, the higher the PFC stage power capability. Hence, L must be low enough so that the full power can be provided at the lowest line level: L (V line,rms ) LL (P in,avg ) max T on,max (eq. ) Like in traditional CrM applications, the following equations give the other parameters of importance: Maximum peak current: Maximum rms current: (I L,pk ) max (P in,avg ) max (eq. 3) (V line,rms ) LL (I L,rms ) max (I L,pk ) max (eq. 4) 6 In our application, the inductor must then meet the following requirements: L H (I L,pk ) max A (eq. 5) 90 (I L,rms ) max A (T on,max =0s) is the minimum value for T on,max (the typical value being 5 s). (T on,max =0s) is hence, used in Equation 5 since this is the worst case when calculating L. It is in addition, recommended to select an inductor value that is at least 5% less than that returned by Equation 5 for a healthy margin. A 00-H/6-A pk inductor (ref: from WÜRTH ELEKTRONIK) is selected. It consists of a 0: auxiliary winding for zero current detection. One can note that the switching frequency in CrM operation depends on the inductor value: f sw V line (t) Vout V line (t) (eq. 6) 4 P in,avg V out L For instance, at low line, full load (top of the sinusoid), the switching frequency is: f sw ( 90) (390 90) 80 khz (eq. 7) Power Silicon Devices Generally, the diode bridge and the power MOSFET are placed on the same heat-sink. As a rule of the thumb, one can estimate that the heat-sink will have to dissipate around: 4% of the output power in wide mains applications (95% being generally the targeted minimum efficiency) % of the output power in single mains applications. In our wide-mains application, about 6.4 W are then to be dissipated. We selected a low-profile heat-sink from COLUMBIA-STAVER (reference: TP07ST/0/.5/ NA/SP/03) whose thermal resistance has been measured to be in the range of 6C/W. Among the sources of losses that contribute to this heating, one can list: The diodes bridge conduction losses that can be estimated by the following equation: P bridge V f P out.8 V f P out V line,rms V line,rms where V f is the forward voltage of the bridge diodes. The MOSFET conduction losses are given by: (eq. 8) (P on ) max (eq. 9) 4 3 R DS(on) P out,max (V line,rms ) LL 8 (V line,rms ) LL 3 V out,nom In our application, we have: P BRIDGE = 3.4 W, assuming that V f is V. (P on ) max = 3.4 R DS(on). In our application, a low R DS(on) MOSFET is selected to avoid excessive MOSFET losses. Assuming that R DS(on) doubles at high temperature, the maximum conduction losses are about.7 W. The total conduction losses can then be as high as about 5. W. Switching losses cannot be easily computed. We will not attempt to predict them. Instead, as a rule of the thumb, we will assume a loss budget equal to that of the MOSFET conduction ones. Experimental tests will check that they are not under-estimated. One can anyway note that the MOSFET turn off can be accelerated using the schematic of Figure, where the Q NPN transistor (TO9) amplifies the MOSFET turn off gate current. This enhancer is not implemented in our board. 3

4 DRV R D N448 Q R R0 0 k Figure. Q Speeds Up the MOSFET Turn Off The boost diode is the source of the following conduction losses: (I out V f ), where I out is the load current and V f the diode forward voltage. The maximum output current being nearly 0.4 A, the diode conduction losses are in the range of 0.4 W (assuming V f = V). P DIODE = 0.4 W. 3. Output Bulk Capacitor There generally are three main criteria/constraints when defining the bulk capacitor: Peak-to-peak low frequency ripple: (V out ) pk pk M P out,max C bulk V out,nom (eq. 0) where ( = f line ) is the line angular frequency. This ripple must keep lower than 4% of the output voltage (8% peak-to-peak). Taking into account the line frequency minimum value (47 Hz), this leads to: C bulk F (eq. ) 8% Hold-up time specification: C bulk P out,max t HOLDUP V out,nom V out,min Hence, a 0-ms hold-up time imposes: (eq. ) 60 0 m C bulk 08 F (eq. 3) Rms capacitor current: The rms current depends on the load characteristic. Assuming a resistive load, we can derive the following approximate expression of its magnitude (Note 3): (I c,rms ) max (eq. 4) 3 (P in,avg ) max 9 (V line,rms ) LL V out,nom P out,max V out,nom In our application, we have: I C,rms Step 3: Feedback Arrangement As shown by Figure, the feed-back arrangement consists of: A resistor divider that scales down the bulk voltage to provide pin8 with the feedback signal. The upper resistor of the divider generally consists of three or four resistors for safety considerations (see R 8, R 9 and R 0 of Figure 7). If not, any accidental shortage of this element would apply the output high voltage to the controller and destroy it. A filtering capacitor that is often placed between pin8 and ground to prevent switching noise from distorting the feedback signal. A -nf capacitor is often implemented. Generally speaking, the pole it forms with the feedback resistors must remain at a very high-frequency compared to the line one. Practically, C fb 50 Rfb R fb fline generally give good results. A type compensation network. Consisting of two capacitors and of one resistor, this circuitry sets the crossover frequency and the loop characteristic. In steady-state the feedback being in the range of the.5-v regulation reference voltage, the feedback bottom resistor (R fb of Figure or R of Figure 7) sets the bias current in the feedback resistors as follows: I FB V REF R fb.5 R fb (eq. 6) Trade-off between losses and noise immunity dictates the choice of this resistor. Resistors up to 56 k (I FB 50 A) generally give good results. Higher values can be considered if allowed by the board PCB layout. Please note anyway that a 50-nA sink current (500 na max. on the 40C to 5C temperature range) is built-in to ground the feedback pin and disable the driver if the pin is accidently open. If I FB is set below 50 A, the regulation level may be significantly impacted by the 50-nA sink current. When the bottom resistor is selected, select the upper resistor as follows: R fb R fb V out,nom V REF (eq. 7) In our application, we select a 7-k for R fb (I FB 9 A). As for R fb, two,800-k resistors are placed in series with a 560-k one. These normalized values precisely give: (R fb = 4.6 M), leading to a nominal 388-V regulation level, which is acceptable A (eq. 5) 3. It remains wise to verify the bulk capacitor heating on the bench! 4

5 Compensating the Loop: The loop gain of a PFC boost converter is proportional to the square of the line magnitude if no feed-forward is applied. Hence, this gain almost varies of an order of magnitude in universal mains conditions. The V SENSE pin voltage is representative of the line voltage value. The NCP6 uses this information to perform a discrete feed-forward function: in high-line that is detected when the pin voltage happens to exceed. V, the PWM gain is divided by 3 compared to a low-line state (which is set if V SENSE is less than.7 V for 5 ms see Figure 3 and Figure 5). Loop Gain ( ) 3*G 0 G 0 V line,rms (V in,rms ) BOH.7*(V in,rms ) BOH.*(V in,rms ) BOH 3*(V in,rms ) BOH e.g.: 78 V e.g.: 33 V e.g.: 7 V e.g.: 34 V Figure 3. -step Feed-forward Limits the Loop Gain Variation with Respect to Line Using the method described in [] and [], we can easily derive two small-signal transfer functions of our PFC stage (one for high line, one for low line): Low-line transfer function: (eq. 8) V^ out V in,rms R load V^ L V control out,nom s R load C bulk High-line transfer function: (eq. 9) V^ V out in,rms R load V^ L V control out,nom s R load C bulk Where: C bulk is the bulk capacitor. R load is the load equivalent resistance. L is the PFC coil inductance. V out,nom is the regulation level of the PFC output PFC stages must be slow. More practically, high PF ratios require the low regulation bandwidth to be in the range of 0 Hz or lower. Hence, sharp variations of the load result in excessive over and under-shoots. These deviations are effectively contained by the NCP6 dynamic response enhancer together with its accurate over-voltage protection. Still however, a type compensation is recommended as shown in the following figure: V CONTROL I CONTROL V OUT R C C R fb R fb FB OTA V REF To PWM Comparator Figure 4. Regulation Trans-conductance Error Amplifier, Feed-back and Compensation Network 5

6 The output to control transfer function brought by the type compensator is: Where: V^ control V^ out sr C C sr o (C C ) sr C C C (eq. 0) R o V out,nom V ref G EA, G EA being the 00-S error amplifier trans-conductance gain, V out,nom, the bulk nominal voltage and V REF, the OTA.5-V voltage reference. Applying the compensation method described in [] and [3], we obtain the following dimensioning equations: G 0 (V line,rms ) LL R load,min L V out,nom (eq. ) G 0 tan m C f c R load,min C bulk R 0 C G 0 f c R 0 C R R load,min C bulk C Where: (V in,rms ) LL is the rms voltage of the line when at its lowest level (90 V in our case) G 0 is static gain at the lowest level of the line ((V line,rms ) LL ) m is phase margin (in radians) f c is the targeted crossover frequency R load,min is the load equivalent resistor at full load R load,min V out,nom P out,max 60 The crossover frequency is selected as low as possible but higher or equal to the PFC boost stage pole at full load f p.4 R load,min C bulk Hz The phase margin is generally set between 45 and 70 degrees. In our application, if we target a 5-Hz crossover frequency and a 60-degree phase margin (/3 in radians), we have: G 0 C C R tan nf lets choose 0 nf C.9 F lets choose. F k (eq. ) Step 4: Input Voltage Sensing The NCP6 monitors the line voltage. In general, resistors are placed between the two line wires to discharge the X capacitors (safety requirements). These resistors, R X and R X of Figure and Figure 5, scale down the input voltage that can then be easily sensed by the controller. Assuming these resistors exhibit the same R X resistance, the voltage applied to pin is: V pin R bo (R bo R bo ) R X V R bo R bo R X (R bo R bo ) R line (t) X This expression simplifies as follows: V pin (eq. 3) R bo R X R bo R bo V line (t) (eq. 4) The brown-out comparator detects a brown-out situation if the V SENSE pin voltage remains lower than (V bol = 0.9 V) for more than 50 ms. In this case, the circuit gradually discharges the control signal until the skip staticovp level is reached and hence, the circuit stops operating. Operation resumes as soon as the V SENSE pin voltage exceeds (V boh =.0 V). If (V line,rms ) boh is the minimal rms voltage of the line to enter operation and (V line,rms ) bol the maximum voltage leading to a Brown-Out fault, we have: (V line,rms ) boh R X R bo R bo V boh (eq. 5) Rbo (V line,rms ) bol R X R bo R bo V bol (eq. 6) Rbo Where: V boh is the.0-v upper brown-out internal threshold V bol is the 0.9-V lower brown out internal threshold 6

7 AC Line EMI Filter PFC Boost Converter R X R X BONOK R bo V SENCE Pin 50-ms Blanking Time R bo.0 V If BONOK High 0.9 V If BONOK Low LLine 5-ms Blanking Time. V If LLine High.7 V If LLine Low I ramp *I ramp FFcontrol Pin Current Information Generation DRV Figure 5. Brown-Out and Line Range Detection Block R X and R X are implemented for safety considerations. In general, they must be selected so that the series combination of (R X R X =R X ) form with the X EMI capacitors, a time constant less than s. In our case, the two -M resistors (R X = R X = R X = M) are implemented that together with the selected X capacitors, leads to a.8-s discharge time constant, which may be too long for most applications (even when considering R bo and R bo resistors that slightly lower the actual X capacitors discharge impedance). In this case, appropriately reduce R X and R X. Low stand-by losses and noise immunity are the considerations when dimensioning R bo and R bo. The first criterion leads to high-impedance resistors to limit the bias current drawn from the line since it can significantly impact the light load losses. On the other hand, very large values can cause noise issues. In practice, (R bo = 0 k generally gives good results. R X, R X and R bo being selected, R bo can be derived from Equation 5 based on the desired (V line,rms ) boh level as follows: R bo R bo (V line,rms ) boh VboH R X (eq. 7) In our application if (V line,rms ) boh is 8 V, (R X = R x = R X = M) and (R bo = 0 k), we obtain: 0 k 8 R bo 000 k 0 k 653 k (eq. 8).0 V In practice, 3,800-k resistors in series with a 560-k one are used for a global 5,960-kR bo value which leads to ((V line,rms ) boh 77.5 V) and ((V line,rms ) bol 69.8 V). Remark: A filtering capacitor C bo is recommended between pin and ground to protect the pin from possible surrounding noise. It must be small however not to distort the voltage sensed by pin. Practically, the time constant it 7

8 forms together with the sensing resistors must remain lower than the line period divided by 50 T line f line that is less than 50 s in 50-Hz line conditions. If not, the voltage applied to pin, may not be proportional to the input voltage but a filtered, phase-shift portion of it, so this should be taken into account when dimensioning the brown-out circuitry and the frequency fold-back behavior. In our case, the resistive impedance on pin can be approximated to R bo. Hence, R bo C bo C bo 00 f line.4 nf 00 R bo f line 00 0 k 60 Step 5: Current Sense Network The current sense circuitry consists of: A current sensing resistor R CS A resistor R FF that adjusts the frequency fold-back characteristic => Computing R CS The circuit detects an over-current situation if the voltage across the current sense resistor exceeds 0.5 V. Hence: R CS 0.5 (eq. 9) (I L,pk ) max Combining this equation with Equation 3 leads to: In our practical case, R CS (V line,rms ) LL 4 (eq. 30) (P in,avg ) max R CS (eq. 3) In order to have a bit of margin, a 80-m resistor is selected. R CS losses can be computed using the equation giving the MOSFET conduction losses where R CS replace R DS(on) : (P RCS ) max 4 3 R CS (eq. 3) (P in,avg ) max (V line,rms ) LL 8 (V line,rms ) LL 3 V out,nom Hence, our 80-m current sense resistor will dissipate about 75 mw at full load, low line. R SENSE must be applied to the CS/ZCD pin through a resistor (R OCP of Figure ). This resistor must be greater than 3.9 k but not too high for noise immunity necessity. Generally, resistors in the range of 5 k give good results. => Zero Current Circuitry The CS/ZCD pin is also designed to receive a signal from an auxiliary winding for Zero Current Detection. As illustrated in Figure, this voltage is applied thought a diode to prevent this signal from distorting the current sense information during the on-time and through a resistor R ZCD. This resistor must be high enough so that no more than 5 ma is injected to the CS/ZCD pin. The auxiliary winding being maximum near the line zero crossing and equal to n aux n p V out,nom where respectively, n aux and n p are the auxiliary and primary turns ratio of the magnetic component, this constraint leads to: R ZCD n aux n V out,nom p V CL(pos) 5mA V CL(pos) R OCP (eq. 33) Where V CL(pos) is the 9-V minimum level of the CS/ZCD pin positive clamp. The voltage applied to the CS/ZCD pin is: V ZCD R OCP R ZCD R OCP n aux n P (V out,nom V line ) (eq. 34) This voltage is compared to the NCP6 750-mV internal threshold for demagnetization detection. For a proper detection, a scale down factor R OCP n aux R ZCD R OCP n P in the range of 0, generally gives good results. One way is to select (R OCP =R ZCD ), (n aux /n p ) in the range of 0. and re-arranging Equation 33, compute n aux n V out,nom P VCL(pos) R ZCD R OCP. 5mA In our application, this leads to (R OCP =R ZCD > 4. k). We selected: (R OCP =R ZCD = 4.7 k). This selection also meets the (R OCP > 3.9 k) requirement (see precedent paragraph). The NCP6 integrates a leading edge blanking on the CS/ZCD pin that prevents the need for a filtering capacitor. It is still possible to add one but it must be very small not to distort the ZCD signal. Otherwise, the circuit may not turn on at the very valley or worse, inappropriately skip valleys. In other words, check that the ZCD signal is correct and not too filtered. In our application this capacitor should not exceed pf. => Computing R FF R FF adjusts the current level below which the frequency starts to be reduced. The FFcontrol pin sources a current that is proportional to: 8

9 I FF V pin V control V control,min (eq. 35) V control,max V control,min Since (V pin = V) when (V line = (V line,rms ) BOH ), we can write: V V pin V line. (Vline,rms ) BOH Further noting that V control V control,min t on V control,max V control,min t on,max where t on,max is the 5-s internal maximum on-time and that Equation 35 changes into: I line V line t on L, I FF 56 L I line 5 (eq. 36) (V line,rms ) BOH The FFcontrol pin voltage is then: V FF 56 R FF L I line 5 (eq. 37) (V line,rms ) BOH The PFC stage operates in critical conduction mode (no frequency reduction) when V FF exceeds.5 V, that is, as long as the instantaneous line current is higher than: (I line ) th 5 (V line,rms ) BOH (eq. 38) R FF L If as specified, we want to start to reduce the frequency when the line current goes below 450 ma, resistor RFF must be: R FF 5 (V line,rms ) BOH L (eq. 39) k It may be more convenient to express this threshold as a percentage of the maximal line current which is given by: I line,max (P in,avg ) max.67 A (eq. 40) (V in,rms ) LL With a 70-k resistor, the circuit starts to reduce the frequency when the line current is about 7% of its maximum value. The minimum 0-kHz operation will be obtained when the FFcontrol pin voltage is about 0.75 V nominal. At that point, the current is (7% 0.75/.5) or 5% of its maximum value. Below this level, the circuit enters skip mode. Remark: A filtering capacitor C FF is recommended between pin3 and ground to protect the pin from possible surrounding noise. In a typical application, it must be small however not to distort the voltage sensed by pin. Practically, the time constant it forms together with the sensing resistors must remain lower than the line period divided by 50 T line f line that is less than 50 s in 50-Hz line conditions. In our case, the resistive impedance on pin3 is R FF. Hence, R FF C FF C FF 50 f line (eq. 4) 4 pf 50 R FF f line k 60 Layout and Noise Immunity Considerations The NCP6 is not particularly sensitive to noise. However, usual layout rules for power supply apply. Among them, let us remind the following ones: The loop area of the power train must be minimized Star configuration for the power ground that provides the current return path Star configuration for the circuit ground The circuit ground and the power ground should be connected by one single path This path should preferably connect the circuit ground to the power ground at a place that is very near the grounded terminal of the current sense resistor (R sense ). A 00 or 0-nF ceramic capacitor should be placed between the circuit V CC and GND pins, with minimized connection length The components (resistors or capacitors) that program the circuit operation must be placed as close as possible to the pin they drive. As aforementioned, it is furthermore recommended to place a filtering capacitor on the 3 relatively high-impedance pins of the circuit: feedback, Input voltage sensing (V SENSE ) and FFcontrol to protect the pin from possible surrounding noise. It must be small however not to distort the voltage sensed by these pins. See the corresponding sections for more details. 9

10 Table. SUMMARY OF THE MAIN EQUATIONS Steps Components Formulae Comments Step Key Specifications f line : Line frequency. It is often specified in a range of Hz for 50 Hz/60 Hz applications. (V line,rms ) LL : Lowest Level of the line voltage, e.g., 90 V. (V line,rms ) HL : Highest Level for the line voltage (e.g., 64 V in many countries). (V line,rms ) boh : Brown-Output Line Upper Threshold. The circuit prevents operation until the line rms voltage exceeds this level. V out,nom : Nominal Output Voltage. (V out ) pk pk : Peak-to-Peak output voltage low-frequency ripple. t HOLD UP : Hold-up Time that is the amount of time the output will remain valid during line drop-out. (V out,min ): Minimum output voltage allowing for operation of the downstream converter. P out,max : Maximum output power consumed by the PFC load, that is, 60 W in our application. (P in,avg ) max : Maximum power absorbed from the mains in normal operation. Generally obtained at full load, low line, it depends on the efficiency that, as a rule of a thumb, can be set to 95%. Input Diodes Bridge Losses P bridge V f P out.8 V f P out V line,rms V line,rms V f is the forward voltage of any diode of the bridge. It is generally in the range of V or less. Inductor L (V line,rms ) LL (P in,avg ) max T on,max (I L,pk ) max (P in,avg ) max (V line,rms ) LL In our application: L H 70 (I L,pk ) max A 90 (I L,rms ) max (I L,pk ) max 6 (I L,rms ) max A Step Power Components MOSFET Conduction Losses (P on ) max 4 3 R DS(on) P out,max (V line,rms ) LL 8 (V line,rms ) LL 3 V out,nom R DS(on) is the drain-source on-state resistance of the MOSFET Bulk Capacitor Constraints P out,max C bulk (V out ) pk pk V out,nom C bulk P out,max t HOLDUP V out,nom V out,min (I c,rms ) max 3 (P in,avg ) max 9 (V line,rms ) LL V out,nom P out,max V out,nom These 3 equations quantify the constraints resulting from the low-frequency ripple ((V out ) pk pk that must be kept below 8%), the hold-up time requirement and the rms current to be sustained. 0

11 Table. SUMMARY OF THE MAIN EQUATIONS (continued) Steps Components Formulae Step3 Feedback Arrangement Resistor Divider Compensation R fb R fb V out,nom V REF C fb R fb.5 I FB 50 Rfb R fb fline G 0 (V line,rms ) LL R load,min L V out,nom G 0 tan m C f c R load,min C bulk R 0 C G 0 f c R 0 C Comments I FB is the bias current that is targeted within the resistor divider. Values in the range of 50 A to 00 A generally give a good trade-off between losses and noise immunity. C FB is the filtering capacitor that can be placed between the FB pin and ground to increase the noise immunity of this pin. R R load,min C bulk C Step4 Input Voltage Sensing Input Voltage Sensing Resistors R bo R bo C bo (V line,rms ) boh VboH R X 50 R bo f line R X is the resistance of the X capacitors discharge resistors R X and R X according to Figure 5. (V line,rms ) boh line rms level above which the circuit starts operating. V boh is an internal -V reference. Step5 Current Sense Network Current Sense Resistor Zero Current Detection R CS (P RCS ) max 4 3 R CS (P in,avg ) max (V line,rms ) LL R ZCD (V line,rms ) LL 4 (P in,avg ) max 8 (V line,rms ) LL 3 V out,nom n aux n V out,nom p V CL(pos) V CL(pos) 5mA R OCP (V line,rms ) LL is the line rms voltage lowest level in normal condition (e.g., 90 V). V out,nom is the output nominal level (e.g., 390 V). (P in,avg ) max is the maximum input power of your application. Placed between R CS and the CS/ZCD pin, resistor R OCP must be greater than 3.9 k but not too high for noise immunity. Generally, resistors in the range of 5 k give good results. Current Controlled Frequency Fold-back R FF 5 (V line,rms ) BOH L (I line ) th C FF 50 f line R FF (I line ) th is the line current level below which the NCP6 starts to reduce the frequency.

12 Detailed Schematic for our 60-W, Universal Mains Application C4, 0 nf Type = X R, 000 k IN U GBU606 C5 470 nf/400 V D N5406 L, 00 H (np/ns = 0) D MUR550 Rth B5753S50M V in V aux V line R, 000 k C nf Type = Y D3 N448 R5. Q IPA50R50 DRV V bulk CM L F C nf Type = Y C3 680 nf Type = X R6 D4 N448 R4 0 k R3 80 m, 3W C7 F/50 V C6a 68 F/450 V DZ 33 V C6b 68 F/450 V I sense GND V CC L N Earth Vrms Socket for External VCC Power Source Figure 6. Application Schematic Power Section V line R 560 k R3,800 k R4,800 k R5,800 k R6 0 k C6 00 pf R 7 k C8 nf C0 0 nf R k C9. F R8 560 k R9,800 k R0,800 k R4 70 k R6 0 k R7 0 k C 470 pf R3 0 R5 0 k C5 0 nf D6 N448 C NC C3 0 nf ZD V R8 7 R0, 4.7 k D5 N448 C4 NC R9 NC R7 0 R 4.7 k V bulk V in V CC V aux DRV I sense GND Figure 7. Application Schematic Control Section

13 Conclusions This paper summarizes the key steps when dimensioning a NCP6-driven PFC stage. The proposed approach being systematic, it can be easily applied to other applications. In addition, an Excel Spreadsheet is available that further eases your design by computing the main components of your application according to the described method [5]. The process has been illustrated by the example of the 60-W, wide-mains evaluation board. You can find details and information on the performance of this board in the NCP6 Evaluation Board Manual [4]. Implementation details (BOM, GERBER files) can be found on our web site [6]. More details on the circuit operation can be found in its data sheet [7]. References [] Joel Turchi, Safety tests on a NCP6-driven PFC stage, Application note AND9064/D, D.PDF. [] Joel Turchi, Compensation of a PFC stage driven by the NCP654, Application note AND83/D, D.PDF. [3] Joel Turchi, Compensating a PFC stage, Tutorial TND38 D available at: D.PDF. [4] EVBUM49/D, NCP6 Evaluation Board User s Manual, D.PDF [5] NCP6 design worksheet, [6] NCP6 evaluation board documents, [7] NCP6 data sheet, D.PDF. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative AND906/D