A CMOS Proteretic Bistable Device

Transcription

1 A CMOS Proteretic Bistable Device by Apuroop kumar Reddy Anyam, Azeemuddin Syed in India Conference (INDICON), 2016 IEEE Annual. Report No: IIIT/TR/2016/-1 Centre for VLSI and Embeded Systems Technology International Institute of Information Technology Hyderabad , INDIA December 2016

2 A CMOS Proteretic Bistable Device Anyam Apuroop Kumar Reddy, Syed Azeemuddin Center for VLSI and Embedded Systems International Institute of Information Technology Hyderabad, India M.R. Sayeh Department of Electrical and Computer Engineering Southern Illinois University Carbondale Carbondale, IL 62901, United States Abstract CMOS Schmitt trigger is a widely used hysteretic device due to its noise immunity. However, hysteresis by itself incorporate a delay in the device. In order to eliminate the problem of delay and advance the transition, we propose a circuit which works on the principle of proteresis. It is similar to hysteresis but has reverse behavior. Theoretically, when compared to an hysteretic bistable device, a proteretic device has a swapped triggering voltages which leads to twofold speed without altering the ability of noise immunity. The simulation results demonstrate an improvement of approximately 140% in transition time delay when compared to the Schmitt trigger at the cost of area and could be further improved by proper sizing. By using UMC 180 nm CMOS technology, a 0.2 V width proteretic loop has been achieved which signifies the amount of noise immunity it possesses. Index Terms Schmitt trigger; Hysteresis; Proteresis; I. INTRODUCTION In digital electronics, conversion of an analog signal into a digital signal is a necessary role to be performed as most of the signal naturally exist in analog form. A CMOS inverter is a basic building block in comparator [1] which is commonly used in analog to digital converter (ADC). An inverter has a triggering voltage based on which input-output relations are defined. In general, when an input is above this voltage, the output is considered as high and similarly, low when it is below it. For a particular supply voltage and relative PMOS, NMOS sizes, the triggering voltage is fixed. Hence when noise appears at triggering point, then the output undergoes multiple transitions between high (V cc ) and low (0) leading to more power consumption. To overcome this, one can use circuits with two thresholds, one for rising edge and another for the falling edge. A commonly used circuit with two thresholds is a Schmitt trigger [2] and it works on the principle of hysteresis. Hysteresis is a greek origin word which means lag or behind and a circuit working on hysteresis means it has a delay in its response (in both directions). A CMOS schmitt trigger is a widely used hysteretic bistable circuit for its performance in noisy environment. Schmitt trigger has many applications in the construction of ADC [3], SRAMS [4], Imaging sensors [5] and ASK demodulates for Wireless transceivers [6] and retinal prosthetic device [7]. Variants of Schmitt trigger which can control its hysteresis with voltage [8] and current [9] are also used in frequency doubling [10] and retinal focal plain sensing [11] respectively /16/$ IEEE Fig. 1. CMOS Schmitt Trigger Circuit [2]. It has countless applications in basic electronics, imaging and medical. The immunity of Schmitt trigger is due to its two delayed distinct triggering voltages, due to which it is slower than an inverter in transition response and has to be eliminated. Alternatively, it is adding lag or hysteresis to the triggering voltage of CMOS inverter resulting in a delayed transition. The identified lag can be removed and could be rushed by replacing hysteresis nature of the circuit with anti-hysteresis or reverse-hysteresis behavior. The word proposed for reverse hysteresis is proteresis [12], proto in greek means before. The circuit showing proteresis can act as a transition accelerator circuit [13] and also an optical proteretic bistable device is used in high-speed oscillation applications [14]. In this paper, the proposed circuit is developed by adding an extra stage of 8 transistors to CMOS Schmitt trigger. II. CMOS SCHMITT TRIGGER CMOS Schmitt trigger as shown in Fig. 1 consist of 3 PMOS and 3 NMOS with two distinct triggering voltages, one for rising edge namely upper triggering voltage (V sh ) and

3 TABLE I HIGH IMPEDANCE O/P FOR LOGICALLY INVERTED INPUTS A AND B. IT ALSO SHOWS THE FASTEST POSSIBLE CASE FOR TRANSITION TO 0. A B Q10 Q9 Q7 Q8 O/p Vcc 0 On Off off On H.I 0 Vcc Off On On Off H.I Vth,n Vcc On On On Off 0 Fig. 2. Voltage Transfer Characteristics of CMOS Schmitt Trigger. another for falling edge, namely lower triggering voltage (V sl ) which helps in building noise immunity of the circuit. Fig. 2 shows the voltage transfer characteristics (VTC) of the Schmitt trigger. The voltage difference between the two triggering voltages is the amount of noise immunity it possesses. III. PROPOSED PROTERETIC CIRCUIT Fig. 3. An Addition Stage for Schmitt Trigger to work as a Proteretic Device. A. Working of additional stage The circuit as shown in Fig. 3 is an additional stage for CMOS Schmitt trigger for it to work as a proteretic device. One can examine this circuit by initially assuming the two inputs A and B to be logically opposite to each other. From the table shown in Table. I, it is clear that the output (i.e, C) will remain in high impedance state for the above two both the cases. Considering another case where one (A) of inputs is varying keeping another one (B) constant, which follows B to be at V cc andaat0. At this stage Q7, Q9 are turned on and Q8, Q10 are turned off, thus making the output C to be in high impedance state. By varying input A from 0 to V th,n (of Q10), turns on Q10 and shorts C to ground, thus making V th,n as an upper triggering point. Further increasing the input to V cc V th,p, turns off Q7. It completely isolates output C from V cc and 0, making it a high impedance state. Similar behavior is seen when input A is varied from V cc to 0. Similarly, considering a case where B is at 0 andaatv cc. At this stage Q7, Q9 are turned off and Q8, Q10 are turned on. Which made output C to be in the high impedance stage. By varying input A from V cc to V cc V th,p, it turns Q7 on and shorts C to V cc, thus turning V cc V th,p as a lower triggering point. Further decreasing the input to V th,n turns off Q10, making the output to be in high impedance state. Similar behavior is seen when input A is varied from 0 to V cc. B. Graphical Method for Constructing a Proteresis VTC Fig. 4 depicts the information presented above in graphical terms. Where G1 is a case considered when B is 0 and A varying between V cc and 0. G2 is a case considered when BisV cc and A is varying between 0 and V cc. G3 is a case considered when B is V cc for A varying from 0 to V cc and B as 0 for A varying from V cc to 0 thus, resulting in an anticlockwise loop. G4 is a case considered when B is 0 for A varying from 0 to V cc and B as V cc for A varying from V cc to 0 thus, resulting in a clockwise loop. For an inverting device, if the VTC has a clockwise loop then it possesses an hysteretic behavior and similarly anticlockwise loop for a proteretic behavior. G5 is VTC for a CMOS inverter. To remove the high impedance state one need to combine the G3 and G5 to get a proteresis curve. At the circuit level, this is done by shorting the outputs of the inverter and the circuit shown in fig 2. C. Complete Circuit with working conditions For the input B to be changed as above condition, B should be an inverting output of A and also have some bistability. Schmitt trigger is the best choice for it. The problem encountered while using Schmitt trigger is that it should have its

4 TABLE II SHOWS THE RESPONSE OF THE CIRCUIT OF FIG. 3FOR A RISING FORM 0 TO V cc WITH AN ASSUMPTION OF B AS SCHMITT TRIGGER OUTPUT OF A. A B C Q10 Q9 Q7 Q8 0 Vcc H.I Off On On Off Vth,n Vcc 0 On On On Off Vcc - Vth,p 0 0 On Off off On VSH 0 H.I On Off off On Vcc 0 0 On Off off On B is fixed initially to V cc and A is varying from 0 to V cc.if suppose V u (proposed circuit upper triggering voltage) is less than V cc V th,p, then a stage exists where all the transistors are turned on and creating a short path between the ground and V cc source. The table also shows how the high impedance state between 0 and V th, V sh and V cc can be easily removed by shorting it with inverter output. The additional inverter at the output is to isolate the circuit output from external connection as it has a lot of fan out. Another advantage of the inverter is that it help in reducing the transition time between V cc and 0, thus reducing the power wastage and resulting in sharp VTC as shown in Fig. 7. IV. RESULTS Fig. 4. Graphically way of building a proteresis Voltage Transfer characteristic(vtc) response with help of combining the possible VTC responses of circuit from Fig. 3 with CMOS inverter VTC. upper triggering point (V sh ) less than V dd V th,p, or else a short path between the ground and V cc source exist resulting in power wastage. Similar is the case when V sl >V th,n. (Where V sl is the lower triggering point of CMOS Schmitt trigger.) The Fig. 5 shows the complete proteretic circuit Fig. 6. Timing diagram of input sinusoidal with its hysteric (green) and proteretic (blue) outputs. It clearly shows that a proteretic response is faster than hysteric Fig. 5. Complete proteretic circuit with inverter buffer output. The Table. II shows the behavior of the circuit when input Fig. 6 shows the timing diagram of the Schmitt trigger and the proposed proteresis improvement to it along with the input sinusoidal signal. It shows that the upper triggering voltage is shifted from 1.1 V to 0.7 V and similarly the lower triggering voltage is shifted from 0.6 V to 0.9 V. Thus making this circuit approximately 140% faster in transition than the CMOS Schmitt trigger by taking inverter threshold as a reference. As mentioned earlier, the amount of noise immunity of a circuit is the difference in two triggering voltages ( V u V l ). Fig. 7 shows the VTC of the proteretic device. It has a noise

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