ADC Description. ECE/CS 5780/6780: Embedded System Design. External Input Pin Descriptions. ADC Block Diagram

Transcription

1 ADC Description ECE/CS 578/678: Embedded System Design Scott. Little Lecture 23: Integrated ADC Configuration 8/-bit resolution. 7 µs, -bit single conversion time. Programmable sample time. External trigger control. Conversion completion interrupt generation. 8 analog input channels via an analog input multiplexer. -8 sequence lengths for conversion. Continuous conversion mode. Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 / 2 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 2 / 2 ADC Block Diagram External Input Pin Descriptions ATDB8C BUS CLOCK CLOCK PESCALE ATD CLOCK CONVESION COMPLETE INTEUPT V H V L V DDA V SSA AN7 / PAD7 AN6 / PAD6 AN5 / PAD5 AN4 / PAD4 AN3 / PAD3 AN2 / PAD2 AN / PAD AN / PAD ANALOG MUX MODE AND TIMING CONTOL SUCCESSIVE APPOXIMATION EGISTE (SA) AND DAC SAMPLE & HOLD ATD INPUT ENABLE EGISTE ESULTS ATD ATD ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 + COMPAATO PAD-PAD6: Serve as the analog input for channel #. They can also be configured for digital GPIO. PAD7: Serves as the analog input for channel 7. It can also be configured to provide an external trigger for the ADC or be used as digital GPIO. V H,V L : The high and low reference voltages for the ADC. V DDA,V SSA : Power supplies for the ADC analog circuits. POT AD DATA EGISTE Figure 8-. ATDB8C Block Diagram MC9S2C Family eference Manual pg. 224 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 3 / 2 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 4 / 2

2 ATDCTL2 Part ATDCTL2 Part 2 Module Base + x ADPU AFFC AAI ETIGLE ETIGP ETIGE ASCIE eset Figure 8-5. ATD Control egister 2 (ATDCTL2) ADPU: enables ADC and disables ADC. AFFC: enables fast clear which results in any access to a result register causing the associated CCF flag to clear. is normal operation. AAI: enables the ADC to run even when the MCU is in ait mode. halts the ADC when the MCU enters ait mode. ASCIE: disables interrupts. enables interrupts. Interrupts occur when ASCIF is set to. ASCIF: If ASCIE = the ASCIF flag equals the SCF (ATDSTAT[7]) flag else ASCIF =. Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 5 / 2 ASCIF ETIGE: enables an external trigger to start ADC conversion. Channel 7 is not available in external trigger mode. ETIGLE ETIGP External Trigger Sensitivity Falling edge ising edge Low level High level Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 6 / 2 ATDCTL3 Part ATDCTL3 Part 2 Table 8-4. Conversion Sequence Length Coding Module Base + x S8C S4C S2C SC FIFO FZ FZ eset Figure 8-6. ATD Control egister 3 (ATDCTL3) S8C, S4C, S2C, SC: Set the number of conversions/sequence. FIFO: is normal operation. enables FIFO mode where each conversion is put into the next result register in order. The order wraps around. Intended usage is with continuous conversion or triggered conversion. FIZ[:]: Determines how the ADC will respond in debug mode when a breakpoint is encountered. S8C S4C S2C SC Number of Conversions per Sequence X X X 8 Table 8-5. ATD Behavior in Freeze Mode (Breakpoint) FZ FZ Behavior in Freeze Mode Continue conversion eserved Finish current conversion, then freeze Freeze Immediately Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 7 / 2 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 8 / 2

3 ATDCTL4 Part ATDCTL4 Part 2 Module Base + x SES8 SMP SMP PS4 PS3 PS2 PS PS eset SES8: is -bit resolution and is 8-bit resolution. SMP[:]: Two bits select the length of the second phase of the sample time in units of ADC conversion cycles. A longer time improves the accuracy of the conversion. PS[4:]: Five bits select the frequency of the ADC conversion clock frequency using the equation: ADCclock = Maximum conversion frequency is 2 MHz and minimum conversion frequency is 5 khz. Eclk *.5. PS+ Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 9 / 2 Table 8-7. Sample Time Select SMP SMP Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 6 A/D conversion clock periods Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 / 2 ATDCTL5 Part ATDCTL5 Part 2 Module Base + x DJM DSGN SCAN MULT CC CB CA eset Figure 8-8. ATD Control egister 5 (ATDCTL5) DJM: is left justified data and is right justified data. DSGN: is unsigned data and is signed data. Signed data is not available with right justification. SCAN: is single conversion and is continuous conversion. SES8 DJM DSGN Table 8-. Available esult Data Formats X X esult Data Formats Description and Bus Bit Mapping 8-bit / left justified / unsigned bits bit / left justified / signed bits bit / right justified / unsigned bits 7 -bit / left justified / unsigned bits 6 5 -bit / left justified / signed bits 6 5 -bit / right justified / unsigned bits 9 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 / 2 Table 8-2. Analog Input Channel Select Coding CC CB CA Analog Input Channel AN AN AN2 AN3 AN4 AN5 AN6 AN7 MULT: hen the ADC samples only from the input specified by the channel selection code (CC,CB,CA). hen the ADC samples across channels. The number of channels sampled is set by the S#C bits. The first channel examined is set by the channel selection code. Subsequent channels selected are determined by incrementing the channel selection code. CC, CB, CA: Selects the analog channel to be sampled or sampled first. Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 2 / 2

4 ATDSTAT Part ATDSTAT Part 2 Module Base + x SCF ETOF FIFO CC2 CC CC eset Figure 8-9. ATD Status egister (ATDSTAT) SCF: The flag is set when a conversion sequence completes. If continuous conversion is being performed the flag is set after each conversion completes. The flag is cleared when a is written to SCF, a new conversion sequence is started, or if AFFC = (ATDCTL2) and a result register is read. ETOF: The external trigger overrun flag is set when ETIGLE= (ATDCTL2) and additional active edges are detected while a conversion is in progress. The flag is cleared when a is written to ETOF, a conversion sequence is aborted, or a new conversion sequence is started. Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 3 / 2 FIFO: Indicates that a result register has been written to before its associated conversion complete flag (CCF#) has been cleared. This is useful in FIFO mode to indicate that result registers are out of sync with input channels. The flag is cleared when a is written to FIFO or a new conversion sequence is started. CC[2:]: epresent the binary value of the conversion counter which points to the result register that will receive the result of the current conversion. Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 4 / 2 ATDTEST ATDSTAT Module Base + x U U U U U U U eset Figure 8-. ATD Test egister (ATDTEST) SC: Setting this bit allows a special conversion channel to be used. The special channel is selected via the CA, CB, and CC bits. Table 8-5. Special Channel Select Coding SC CC CB CA Analog Input Channel X X eserved V H V L (V H +V L ) / 2 eserved SC Module Base + xb CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF CCF eset Figure 8-2. ATD Status egister (ATDSTAT) CCF[7:]: A conversion complete flag is set at the end of each conversion in a conversion sequence. For example, CCF is set after the first conversion when the data in ATDD is available, etc. A CCF# flag is cleared when a new conversion sequence is started, if AFFC = (ATDCTL2) and a read of ATDSTAT is followed by a read of result register ATDD#, or AFFC = and a read of a result register ATDD#. Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 5 / 2 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 6 / 2

5 ATDDIEN ATDD#H/ATDD#L Left Justified Module Base + xd IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN IEN eset IEN[7:]: hen IEN# is digital input is disabled on PTAD#. hen IEN# is digital input is enabled on PTAD#. Module Base + x = ATDDH, x2 = ATDDH, x4 = ATDD2H, x6 = ATDD3H x8 = ATDD4H, xa = ATDD5H, xc = ATDD6H, xe = ATDD7H BIT 9 MSB BIT 7 MSB BIT 8 BIT 7 BIT eset BIT Figure 8-5. Left Justified, ATD Conversion esult egister, High Byte (ATDDxH) Module Base + x = ATDDL, x3 = ATDDL, x5 = ATDD2L, x7 = ATDD3L x9 = ATDD4L, xb = ATDD5L, xd = ATDD6L, xf = ATDD7L BIT U BIT U eset Figure 8-6. Left Justified, ATD Conversion esult egister, Low Byte (ATDDxL) -bit data -bit data Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 7 / 2 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 8 / 2 ATDD#H/ATDD#L ight Justified Setting up and starting an ADC conversion Module Base + x = ATDDH, x2 = ATDDH, x4 = ATDD2H, x6 = ATDD3H x8 = ATDD4H, xa = ATDD5H, xc = ATDD6H, xe = ATDD7H BIT 9 MSB eset BIT 8 Figure 8-7. ight Justified, ATD Conversion esult egister, High Byte (ATDDxH) Module Base + x = ATDDL, x3 = ATDDL, x5 = ATDD2L, x7 = ATDD3L x9 = ATDD4L, xb = ATDD5L, xd = ATDD6L, xf = ATDD7L BIT 7 BIT 7 MSB BIT BIT eset BIT BIT Figure 8-8. ight Justified, ATD Conversion esult egister, Low Byte (ATDDxL) -bit data -bit data Power up the ADC (ADPU = ) and other ATDCTL2 settings. ait for the ADC recovery time. Configure the number of conversions via ATDCTL3. Configure resolution, sampling time, and ADC clock speed via ATDCTL4. Configure the starting channel, single/multiple channel, continuous or single sequence and result data format via ATDCTL5. riting to ATDCTL5 should happen last as it starts the conversion. Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 9 / 2 Scott. Little (Lecture 23: ADC Config) ECE/CS 578/678 2 / 2