MPS Node BLM Version Version /14/09

Transcription

1 MPS Node BLM Version Version /14/09 This version of BLM code was derived from the MPSNode Version 30 even though the working version of the code was version 2D. This is mostly due to the fact that the MPS Node Messages were changed from V2D to V30. As of 7/03/09, this document is under re-write as the BPM document. References to PIC, BYKIK or Mitigation device are incorrect.

2 Table of Contents Drawing Numbers... 5 Arcturus Chip Selects... 5 MPS Node Memory MAP... 5 BLM Latched Fault Memory (16 Bit)... 6 BLM HV Threshold Memory (16 Bit)... 6 ADC Memory... 7 MPS Node Registers (32 Bit)... 8 Memory and Register Space Write Cycles Read Cycles Latched Register [0] Latched Register [1] Latched Register [2] Filtered Register [3] Filtered Register [4] Filtered Register [5] Output Register Control Register [6] Output Register Status Register [7] Input Debounce Select Register [8] Input Debounce Select Register [9] Input Debounce Select Register [10] Input Debounce Select Register [11] Input Debounce Select Register [12] Input Debounce Select Register [13] Input Debounce Select Register [14] Input Debounce Select Register [15] Input Debounce Select Register [16] Input Debounce Select Register [17] Input Debounce Select Register [18] Input Debounce Select Register [19] Debounce Selection values Time Slot Register [20] Time Stamp Seconds Register [21] Time Stamp NanoSeconds Register [22] Input Polarity Register [23] Input Polarity Register [24] Input Polarity Register [25] Version Register [26] Link Node Control [27] Event Counter Register [29] Compiled Date Register [29] Chassis Type Register [30] System Type [31] Jeff Olsen Page 2 9/25/2009

3 Fiber Control Register [34] Fiducial Delay Register [35] Fiducial Width Register [36] Fiducial DCM Phase Control Register [37] Virtual Card (Status) Register [38] Fault LED Disable Register [41] Fault LED Disable Register [42] Fault LED Disable Register [43] DeadMan Enable Register0 [44] DeadMan Enable Register1 [45] DeadMan Enable Register2 [46] DeadMan Input MPS Link Node Configuration[47] BLM Threshold Faults[48] GigaBit Ethernet interface Ethernet Addresses UDP Header BSA ID (0x70) Link Synchronization (0x01) Broadcast Link Unlatch BLM (0x11) Unicast Link Response BLM (0x81) Unicast Status Link Node Status Trigger Byte BSA BLM Message (0xB0) Unicast MPS Link Node Response Summary Input Assignments Fiber Optic Transceiver data Serial ID data fields Address 0xA0 (from SFF-8472 MSA) EEPROM Serial ID Memory Contents Enhanced Feature Set Memory (Address A2h) Display LED s Input Card (SLAC ) Input Connector Output Card (SLAC ) Lemo Inputs Lemo Outputs Isolated Outputs LEMO Inputs Summary LEMO Outputs Summary Isolated Outputs Summary Link Node Configuration (0x00) Lemo Inputs for Mitigation Control Mode Lemo Outputs for Mitigation Control Mode Isolated Outputs for Mitigation Control Mode BLM Configuration (0x01) Jeff Olsen Page 3 9/25/2009

4 Lemo Inputs for BLM Configuration Lemo Outputs for BLM Configuration Isolated Outputs for BLM Configuration BYKIK Configuration (0x02) Lemo Inputs for BYKIK Configuration Lemo Outputs for BYKIK Configuration Isolated Outputs for BYKIK Configuration MPG Mode Configuration (0x03) Lemo Inputs for MPG Node Configuration Lemo Outputs for MPG Node Configuration Isolated Outputs for MPG Node Configuration PIC Mode Configuration (0x04) Lemo Inputs for PIC Node Configuration Lemo Outputs for PIC Node Configuration Isolated Outputs for PIC Node Configuration BLM Functionality BLM Acquisition Interface Configuration HV Set Points - ACROMAG IP DAC Configuration Registers for IP231 and default settings ACROMAG IP330A ADC HV Read Back - ACROMAG IP330 ADC Registers Initial Configuration ALPHI Technologies ATC-AD41meg ADC Registers Known BUGS in the ATC-AD41meg Possible Status Bits Document Version History FPGA Version History MPS Version 30 to BLM Version 10 Notes Schematic Version History PCB Version History Notes: ARCTURUS Configuration: ARCTURUS Configuration(2): CISCO 3750 Switch Configuration EVG Setup Chassis Status Label notes: Jeff Olsen Page 4 9/25/2009

5 The MPS Link Node has four configurations: 1. Mitigation Control 2. BLM 3. BYKIK 4. MPG Control 5. PIC Each configuration has a different set of boards in the MPS Link Node Chassis. Drawing Numbers Number Rev Description Configuration Manufacture R1 MPSNode System Base 1,2,3,4,5 SLAC R1 Input Card 1,2,3,4,5 SLAC R1 Output Card 1,2,3,4,5 SLAC R1 MPSNode Main Board 1,2,3,4,5 SLAC R0 Original L Board Obsolete SLAC R1 IP I/O Card Obsolete SLAC R2 IP-QINT ADC SLAC 8 Channel IP Charge-Integrating ADC R0 BLM Interconnect L Board 2 SLAC IP330A 16Bit Analog Input Module 2 Acromag IP231 16Bit Analog Output Module 2 Acromag ATC-AD41meg 16Bit x 4 1MegaSample ADC 3 ALPHI Technology This Module has several BUGS. Arcturus Chip Selects The MPS Node uses CS1. MPS Node Memory MAP Memory Address Name Description Mem17 0x7DFE 0x2400 BLM Memory 16Bit BLM Memory Memory Mem16 0x23FF 0x2380 IP Board 3 16Bit IO space Mem15 0x237F 0x2300 IP Board 2 16Bit IP231 DAC IO space Mem14 0x22FF 0x2280 IP Board 1 16Bit IP330 ADC IO space Mem13 0x227F 0x2200 IP Board 0 16Bit QADC IO space Mem12 0x21FF 0x2180 IP Board 3 16Bit ID space Mem11 0x217F 0x2100 IP Board 2 16Bit IP231 DAC ID space Mem10 0x20FF 0x2080 IP Board 1 16Bit IP330 ADC ID space Jeff Olsen Page 5 9/25/2009

6 Mem9 0x207F 0x2000 IP Board 0 16Bit QADC ID space Mem7 0x1914 0x1900 BLM Latched Fault 16Bit Status Mem5 0x181E 0x1800 BLM Thresholds 16Bit Mem4 0x1414 0x1400 ADC Data 32Bit Environmental ADC Mem3 0x13FF 0x Bytes of Fiber 1 Transceiver Address 32Bit See AVAGO Datasheet A2h Read as 64 4 byte/words Mem2 0x12FF 0x Bytes of Fiber 1 32Bit Transceiver Address A0h Read as 64 4 byte/words Mem1 0x11FF 0x Bytes of Fiber 0 32Bit Transceiver Address A2h Read as 64 4 byte/words Mem0 0x10FF 0x Bytes of Fiber 0 Transceiver Address A0h Read as 64 4 byte/words 32Bit BLM Latched Fault Memory (16 Bit) 0x1920 HV Threshold Latched Fault Status R 0x191E Channel 7 Latched Fault Status R 0x191C Channel 6 Latched Fault Status R 0x191A Channel 5 Latched Fault Status R 0x1908 Channel 4 Latched Fault Status R 0x1906 Channel 3 Latched Fault Status R 0x1904 Channel 2 Latched Fault Status R 0x1902 Channel 1 Latched Fault Status R 0x1900 Channel 0 Latched Fault Status R Latched by MPS Link Node BLM Sequencer, not the QADC. See QADC document for details. Cleared by Link Node Processor only. Unlatched data is in the QADC IO space. BLM HV Threshold Memory (16 Bit) 0x181E HV 7 Threshold High R/W 0x181C HV 7 Threshold Low R/W 0x181A HV 6 Threshold High R/W Jeff Olsen Page 6 9/25/2009

7 0x1818 HV 6 Threshold Low R/W 0x1816 HV 5 Threshold High R/W 0x1814 HV 5 Threshold Low R/W 0x1812 HV 4 Threshold High R/W 0x1810 HV 4 Threshold Low R/W 0x180E HV 3 Threshold High R/W 0x180C HV 3 Threshold Low R/W 0x180A HV 2 Threshold High R/W 0x1808 HV 2 Threshold Low R/W 0x1806 HV 1 Threshold High R/W 0x1804 HV 1 Threshold Low R/W 0x1802 HV 0 Threshold High R/W 0x1800 HV 0 Threshold Low R/W ADC Memory 0x1414 0x1400 ADC Data 0x1414 Temperature_Addr T = N / x1410 P3D3Vmon_Addr P3D3 = N /1707 0x140C P5Vmon_Addr VDD = N / x1408 P12Vmon_Addr V12 = N / x1404 P24Vmon_Addr V24 = N / x1400 XilinxTemp_Addr T = N / Jeff Olsen Page 7 9/25/2009

8 MPS Node Registers (32 Bit) Register Address Name R/W x00C0 BLM Threshold Faults R/W x00BC MPS Configuration R 0x x00B8 DeadMan_Addr2 R/W x00B4 DeadMan_Addr1 R/W x00B0 DeadMan_Addr0 R/W x00AC LED_Mask_Addr2 R/W x00A8 LED_Mask_Addr1 R/W x00A4 LED_Mask_Addr0 R/W Comment [jjo1]: Read Only Automaicatlly is a BLM x0098 Virtual Input Card (Status) R x0094 Fiducial DCM Phase ** R/W x0090 BLM Trigger Width R/W x008C BLM Trigger Delay R/W x0088 Fiber Optic SFP Control R/W x007C System Type R MPS x0078 Chassis Type R BLM x0074 Compiled Date R x0070 EventCounter R x006C BLM Control R/W x0068 Version R x0064 Time_Stamp_nSec_Addr R x0060 Time_Stamp_Sec_Addr R x005C Time_Slot_Addr R x0058 Input_Pol_Cntl_Addr2 R/W x0054 Input_Pol_Cntl_Addr1 R/W x0050 Input_Pol_Cntl_Addr0 R/W x004C Input_DeBounce_Addr11 R/W x0048 Input_DeBounce_Addr10 R/W x0044 Input_DeBounce_Addr9 R/W x0040 Input_DeBounce_Addr8 R/W x003C Input_DeBounce_Addr7 R/W Comment [jjo2]: Module ID Stuff Comment [jjo3]: New Event Counter Comment [jjo4]: New Features added Jeff Olsen Page 8 9/25/2009

9 0014 0x0038 Input_DeBounce_Addr6 R/W x0034 Input_DeBounce_Addr5 R/W x0030 Input_DeBounce_Addr4 R/W x002C Input_DeBounce_Addr3 R/W x0028 Input_DeBounce_Addr2 R/W x0024 Input_DeBounce_Addr1 R/W x0020 Input_Debouce_Addr0 R/W x0014 Filtered_Reg_Addr2 R x0010 Filtered_Reg_Addr1 R x000C Filtered_Reg_Addr0 R x0008 Latched_Reg_Addr2 R x0004 Latched_Reg_Addr1 R x0000 Latched_Reg_Addr0 R Jeff Olsen Page 9 9/25/2009

10 Memory and Register Space Write Cycles Writeable Memory and Register Space can be written any time. Writes to IP Memory Space or IO Space will be queued in a FIFO. The data will be written to the IP interface when the Acquisition sequencer is idle. Read Cycles Most Data in Register Space is valid all the time, except some of the fault data which is only valid after the Acquisition cycle. Reading from the registers can be done at any time and is non-invasive. Reading from Link Node Memory Space, IP IO Space, and IP Memory Space can require extra steps to insure that the Memory Space has current and valid data in it. Some of the memory is external to the Link Node Xilinx and is directly accessible only by slow serial or parallel interfaces. There are several ways to deal with these external Memory Spaces. 1. Let the Arcturus have direct access. This would require hanging the Arcturus Bus while the bridge sequencer gets the requested data from the remote device. In the case of IP Bus access, this could hold the bus for 1us if the IP Sequencer is Idle, to several ms if an Acquisition cycle is in process. Reading the Fiber Transceiver data would also hang the Arcturus Bus for several us. This is not desirable. 2. Queue the Read Requests The Arcturus would request data from an address and then test a flag to see when data is valid. This would be a very slow way to read the 12K block of memory from the QADC, and would return data acquired during many Acquisition cycles. The data set would not be consistent or Beam Synchronous. 3. Force a Block Read of desired space This method causes the entire copy or shadow memory to be updated at a slow rate and then set a flag when the block has been updated. This means that in the case of the IP Memory and IO space, all of the data in the shadow memory will be from the last sample. The Acquisition cycles are stopped during this process, so it is invasive. Jeff Olsen Page 10 9/25/2009

11 Size Write Read Device Valid IP Memory 0x7DFE 16 Queued R QADC Unused 0xFFFF IPBLKRD Space 0x2400 0x59BC0 RAW ACC 0x59BF IPBLKRD Data 0x5820 Reserved 0x58FF IPBLKRD 0x5830 BaseLine 0x582F IPBLKRD Data 0x5820 Reserved 0x581F IPBLKRD 0x5818 RAW ADC 0x5817 IPBLKRD Data 0x5800 Reserved 0x5nFF IPBLKRD 0x5n26 Threshold 0x5n25 IPBLKRD 0x5n1A Dose Data 0x5n19 0x5n00 ACQ ADC BYKIK 0x07FF ACQ AD41 Waveform 0x0000 IP IO Space 0x23FF 16 Queued R ADC Control and 0x007E IPBLKRD 0x2200 AD41 Data 0x0000 DAC Unused 0x007E IPBLKRD IP231 0x002C Configuration 0x002A IPBLKRD Registers 0x0020 DAC Set 0x001E IPBLKRD Point 0x0000 ADC Unused 0x007E IPBLKRD IP330 0x0060 ADC Data 0x005E ACQ 0x0040 Configuration Registers 0x003E 0x0000 IPBLKRD QADC Unused 0x007E IPBLKRD 0x0048 Channel 0x0046 ACQ Faults 0x0020 Configuration Registers 0x001E 0x0000 IPBLKRD IP ID Space 0x21FF- 16 W R IP INIT 0x2000 Latched PIC 0x1A3E R ACQ Jeff Olsen Page 11 9/25/2009

12 Faults 0x1A00 Latched BLM Faults 0x1920 0x1900 BYKIK 0x1828-0x1820 BLM HV 0x181E Thresholds 0x1800 Environment 0x ADC Data 0x1400 Fiber 0x13FF Transceiver 0x1000 Link Node 0x00C4 - Register 0x0000 Space R ACQ 16 W R Always 16 W R Always R Always R FBLKRD 32 W R Always Always Data is always valid FBLKRD Data is valid after issuing a Fiber Block Read and waiting for the Fiber Done. See Fiber Control Register [34]. AQQ Data is valid and updated during every data acquisition cycle. This can only be read after a Sync Read start in the BLM Control Register. IP Init When the Link Node Mode is set, an IP Init must be issued. This reads all of the IP ID Space and writes initial configuration values into the IP Modules. See BLM Control Register [27] and the Link Node Configuration register [47]. IPBLKRD Data is valid after issuing a IP Block Read and waiting for the IP Block Read Done. See BLM Control Register [27]. This is NOT Beam Synchronous and is invasive. The Acquisition sequencer is stopped for several trigger cycles while data is read from the IP Interface and stored into the Shadow Memory. This should ONLY be done as a diagnostic. Comment [jjo5]: Sync Data Read Latched Register [0] Bit Name Use [31:00] Latched0 Latched input values 31 to 0 R Latched Register [1] Bit Name Use [31:00] Latched1 Latched input values 63 to 32 R Latched Register [2] Bit Name Use [31:00] Latched2 Latched input values 95 to 64 R Filtered Register [3] Bit Name Use Jeff Olsen Page 12 9/25/2009

13 [31:00] Filtered0 Filtered input values 31 to 0 R Filtered Register [4] Bit Name Use [31:00] Filtered1 Filtered input values 63 to 32 R Filtered Register [5] Bit Name Use [31:00] Filtered2 Filtered input values 95 to 64 R Jeff Olsen Page 13 9/25/2009

14 Output Register Control Register [6] Bit Name Use [31:28] Unused [27:24] Trigger Input 0 => Do not change Latch Clear [23:20] Trigger Output Control Trigger 2 and 3 [19:16] Trigger Output Control Trigger 0 and 1 [15:06] Undefined [05:04] PIC Mode HV Control. 5ms oneshot [03:00] Undefined 1 => Clear Set or clear output 00 => Do not change 01 => Set Output Low 10 => Set Output High 11 => Do not change Read only Controlled from Link Node 00 => Do not change 01 => HV On 10 => HV Off 11 => Do not change R Output Register Status Register [7] Bit Name [31:20] Unused [19:16] Trigger Input Latch Status [15:12] Trigger Input Status [11:10] CPU Trigger Output Status [09:08] Glink Trigger Output Status [07:04] CPU Output Status [03:00] Glink Output Status Input Debounce Select Register [8] Bit Name [31:24] Unused [23:21] Debounce Select Input 7 [20:18] Debounce Select Input 6 [17:15] Debounce Select Input 5 [14:12] Debounce Select Input 4 [11:09] Debounce Select Input 3 [08:06] Debounce Select Input 2 [05:03] Debounce Select Input 1 [02:00] Debounce Select Input 0 Jeff Olsen Page 14 9/25/2009

15 Input Debounce Select Register [9] Bit Name [31:24] Unused [23:21] Debounce Select Input 15 [20:18] Debounce Select Input 14 [17:15] Debounce Select Input 13 [14:12] Debounce Select Input 12 [11:09] Debounce Select Input 11 [08:06] Debounce Select Input 10 [05:03] Debounce Select Input 9 [02:00] Debounce Select Input 8 Input Debounce Select Register [10] Bit Name [31:24] Unused [23:21] Debounce Select Input 23 [20:18] Debounce Select Input 22 [17:15] Debounce Select Input 21 [14:12] Debounce Select Input 20 [11:09] Debounce Select Input 19 [08:06] Debounce Select Input 18 [05:03] Debounce Select Input 17 [02:00] Debounce Select Input 16 Input Debounce Select Register [11] Bit Name [31:24] Unused [23:21] Debounce Select Input 31 [20:18] Debounce Select Input 30 [17:15] Debounce Select Input 29 [14:12] Debounce Select Input 28 [11:09] Debounce Select Input 27 [08:06] Debounce Select Input 26 [05:03] Debounce Select Input 25 [02:00] Debounce Select Input 24 Jeff Olsen Page 15 9/25/2009

16 Input Debounce Select Register [12] Bit Name [31:24] Unused [23:21] Debounce Select Input 39 [20:18] Debounce Select Input 38 [17:15] Debounce Select Input 37 [14:12] Debounce Select Input 36 [11:09] Debounce Select Input 35 [08:06] Debounce Select Input 34 [05:03] Debounce Select Input 33 [02:00] Debounce Select Input 32 Input Debounce Select Register [13] Bit Name [31:24] Unused [23:21] Debounce Select Input 47 [20:18] Debounce Select Input 46 [17:15] Debounce Select Input 45 [14:12] Debounce Select Input 44 [11:09] Debounce Select Input 43 [08:06] Debounce Select Input 42 [05:03] Debounce Select Input 41 [02:00] Debounce Select Input 40 Input Debounce Select Register [14] Bit Name [31:24] Unused [23:21] Debounce Select Input 55 [20:18] Debounce Select Input 54 [17:15] Debounce Select Input 53 [14:12] Debounce Select Input 52 [11:09] Debounce Select Input 51 [08:06] Debounce Select Input 50 [05:03] Debounce Select Input 49 [02:00] Debounce Select Input 48 Jeff Olsen Page 16 9/25/2009

17 Input Debounce Select Register [15] Bit Name [31:24] Unused [23:21] Debounce Select Input 63 [20:18] Debounce Select Input 62 [17:15] Debounce Select Input 61 [14:12] Debounce Select Input 60 [11:09] Debounce Select Input 59 [08:06] Debounce Select Input 58 [05:03] Debounce Select Input 57 [02:00] Debounce Select Input 56 Input Debounce Select Register [16] Bit Name [31:24] Unused [23:21] Debounce Select Input 71 [20:18] Debounce Select Input 70 [17:15] Debounce Select Input 69 [14:12] Debounce Select Input 68 [11:09] Debounce Select Input 67 [08:06] Debounce Select Input 66 [05:03] Debounce Select Input 65 [02:00] Debounce Select Input 64 Input Debounce Select Register [17] Bit Name [31:24] Unused [23:21] Debounce Select Input 79 [20:18] Debounce Select Input 78 [17:15] Debounce Select Input 77 [14:12] Debounce Select Input 76 [11:09] Debounce Select Input 75 [08:06] Debounce Select Input 74 [05:03] Debounce Select Input 73 [02:00] Debounce Select Input 72 Jeff Olsen Page 17 9/25/2009

18 Input Debounce Select Register [18] Bit Name [31:24] Unused [23:21] Debounce Select Input 87 [20:18] Debounce Select Input 86 [17:15] Debounce Select Input 85 [14:12] Debounce Select Input 84 [11:09] Debounce Select Input 83 [08:06] Debounce Select Input 82 [05:03] Debounce Select Input 81 [02:00] Debounce Select Input 80 Input Debounce Select Register [19] Bit Name [31:24] Unused [23:21] Debounce Select Input 95 [20:18] Debounce Select Input 94 [17:15] Debounce Select Input 93 [14:12] Debounce Select Input 92 [11:09] Debounce Select Input 91 [08:06] Debounce Select Input 90 [05:03] Debounce Select Input 89 [02:00] Debounce Select Input 88 Debounce Selection values Bits Rate 111 5s 110 1s ms ms ms 010 1ms us us Jeff Olsen Page 18 9/25/2009

19 Time Slot Register [20] Bit Name Use [31:08] Unused [07:00] TimeSlot Time Stamp Seconds Register [21] Bit Name Use [31:00] Time Stamp Time Stamp NanoSeconds Register [22] Bit Name Use [31:15] Time Stamp [14:00] Pulse ID Input Polarity Register [23] Bit Name Use [31:00] Input polarity Inputs => Low True 1 => High True Input Polarity Register [24] Bit Name Use [31:00] Input polarity Inputs => Low True 1 => High True Input Polarity Register [25] Bit Name Use [31:00] Input polarity Inputs => Low True 1 => High True Version Register [26] Bit Name Use [31:24] 01 [23:16] Unused [15:08] Board ID Switch [07:00] Version Number Jeff Olsen Page 19 9/25/2009

20 Link Node Control [27] Bit Name Function Use [31:12] Unused [11] IP Interface IP Interface Timed out waiting Writing 1 Clears Timeout for ACK [10] QADC Timeout QADC Timed Out waiting for Writing 1 Clears DRDY [09] HVADC Timeout IP Interface Timed Out waiting Writing 1 Clears for ACK [08] ACQ_Dead BLM Sequencer Timed out Writing 1 Clears [07:05] [04] BLMSyncRd Start Synchronous Readout Set to 0 when the Acquisition is done and data is available [03] IPBLKRd Start IP Interface Readout Set to 0 when the Acquisition is done and data is available [02] BLM_ClrThres Clear BLM Threshold Faults Diagnostic only [01] BLM_Start Start a BLM Acquisition cycle Diagnostic only [00] IP_Init Initializes the IP interface. Event Counter Register [29] Bit Name Function Use [31:00] Event Counter Number of events sampled Compiled Date Register [29] Bit Name Function Use [31:00] Date Date in hex /14/2009 Chassis Type Register [30] Bit Name Function Use [31:00] Type 0x424C4DA0 BLM System Type [31] Bit Name Function Use [31:00] System Type 0x4D5053A0 MPS Comment [jjo6]: New Comment [jjo7]: New Comment [jjo8]: New Comment [jjo9]: New Comment [jjo10]: New Feature Comment [jjo11]: New Register Comment [jjo12]: New Comment [jjo13]: New Comment [jjo14]: New Jeff Olsen Page 20 9/25/2009

21 Fiber Control Register [34] Bit Name Function Use [31:01] Unused [00] Done Fiber Optic Data available Writing to the register clears bit 0 and causes the Fiber Optic Data sequencer to start taking data from the Fiber Optic Transceiver. When all data has been read, bit 0 is set to a 1 and new data is available. Fiducial Delay Register [35] Bit Name Function Use [31:20] Unused [19:00] FIDDelay Controls the Delay of the internally generated Fiducial. BLM Start 119Mhz ticks Fiducial Width Register [36] Bit Name Function Use [31:20] Unused [19:00] FIDWidth Controls the Width of the internally generated Fiducial BLM Start QADC Trigger 119Mhz ticks Fiducial DCM Phase Control Register [37] Bit Name Function Use [31:19] Unused [19] Gap Polarity DCM Reset 1 => Reset 0 => ok [18] 119Pres 119 Mhz Present [17] [16] DCM Lock DCM Locked [15:00] FIDPhase Controls the phase of the Fiducial DCM to fine tune the Missing Fiducial recovery circuit. Range x0000-0x03FF Jeff Olsen Page 21 9/25/2009

22 Virtual Card (Status) Register [38] Bits [31:09] Unused [11] IP Interface Timeout [10] QADC Timeout [09] HVADC Timeout [08] ACQ Dead [07] 360 BLM Trigger Missing [06] BYKIK Over Threshold Fault [05] BYKIK Under Threshold Fault [04] BX Kick Latch [03] 30 Hz Standby Trigger Missed Less than 20Hz [02] 30 Hz Abort Trigger Missed Less than 20Hz [01] 120 Hz Standby Trigger Missed Less than 80Hz [00] 120 Hz Abort Trigger Missed Less than 80Hz Comment [jjo15]: New This register is cleared by the MPS Link Fault LED Disable Register [41] Bit Name Function Use [31:00] FAULTLEDDIS0 Removes selected inputs [31:00] from the front panel Fault LED 1 => Input will not be used in the Fault LED Fault LED Disable Register [42] Bit Name Function Use [31:00] FAULTLEDDIS1 Removes selected inputs [63:32] from the front panel Fault LED 1 => Input will not be used in the Fault LED Fault LED Disable Register [43] Bit Name Function Use [31:00] FAULTLEDDIS2 Removes selected inputs [95:64] from the front panel Fault LED 1 => Input will not be used in the Fault LED DeadMan Enable Register0 [44] Bit Name Function Use [31:00] DeadManEn0 Enables the DeadMan input circuit after the input filter for selected inputs [31:00] 1 => Input DeadMan enable Jeff Olsen Page 22 9/25/2009

23 DeadMan Enable Register1 [45] Bit Name Function Use [31:00] DeadManEn1 Enables the DeadMan input circuit after the input filter for selected inputs [63:32] 1 => Input DeadMan enable DeadMan Enable Register2 [46] Bit Name Function Use [31:00] DeadManEn2 Enables the DeadMan input circuit after the input filter for selected inputs [95:64] 1 => Input DeadMan enable DeadMan Input The Inputs can have a DeadMan One-shot on them after the Input Filter. This DeadMan times out after 10Ms. The DeadMan timeout is restarted on either the rising or falling edge of the input. MPS Link Node Configuration[47] Bit Name Function [31:07] Unused [07:00] Set Output Card Trigger input and Output Configuration 0x04 => PIC Mode 0x03 => MPG Control Mode 0x02 => BYKIK Mode 0x01 => 0x00 => Mitigation Control Mode Comment [jjo16]: Read Only, always 1 for BLM BLM Threshold Faults[48] Bit Name Function [31:16] BLM Threshold Faults [15:02] Unused [01:00] BYKIK Threshold Faults Jeff Olsen Page 23 9/25/2009

24 GigaBit Ethernet interface The GigaBit Ethernet interface is used to transfer fault information to the MPS Link Node Processor. Ethernet Addresses Ethernet MAC Address IP Address 02:00:00:00:00:[Board ID Switch] C0:A8:00: [Board ID Switch] UDP Header All UDP Messages start with a 2 byte header Byte Value Direction 0 MPS Node message version Version < 1.5 => 0x01 Version = 1.5 => 0x02 Version = 3.0 => 0x03 1 Message Type 0x70 => BSA Enable BSA to Link Node 0X71 => BSA Disable 0x01 => Link Sync 0x02 => Link Permit 0x10 => Link Status UnLatch 0x11 => Link BLM UnLatch 0x12 => Link PIC UnLatch Link Processor to Link Node 0x80 => Link Status 0x81 => BLM Message 0x82 => PIC Message 0xB0 => BLM BSA Message 0xB1 => PIC BSA Message 0xB2 => BYKIK BSA Message Link Node to Link Processor Link Node to BSA Comment [jjo17]: New Op Codes BLM Beam Loss Monitor BSA Beam Synchronous Data Acquisition Message Version changed from 1 to 2 after MPS Node Version 1.4 Message Version changed from 2 to 3 after MPS Node Version 3.0 Jeff Olsen Page 24 9/25/2009

25 UDP Messages BSA ID (0x70) Byte The BSA message sets the IP Address of the BSA processor in the Link Node Link Synchronization (0x01) Broadcast Byte Timestamp Seconds past Epoch 4 Timestamp NanoSeconds[16:00] Pulse ID[14:00] 8 TimeSlot Link Unlatch BLM (0x11) Unicast Byte Timestamp Seconds past Epoch 4 Timestamp NanoSeconds[16:00] Pulse ID[14:00] 8 TimeSlot Link Node ID S1[07:00] S1[15:08] C S2[07:00] S2[15:08] S3[07:00] S3[16:08] 10 S4[07:00] S4[15:08] S5[07:00] S5[15:08] 14 S6[07:00] S6[15:08] Status1[07:00] Status1[15:08] Status2[07:00] Status2[15:08] BLMFaults0[07:00] BLMFaults0[15:08] BLMFaults1[07:00] BLMFaults1[15:08] BLMFaults2[07:00] BLMFaults2[15:08] BLMFaults3[07:00] BLMFaults3[15:08] BLMFaults4[07:00] BLMFaults4[15:08] BLMFaults5[07:00] BLMFaults5[15:08] BLMFaults6[07:00] BLMFaults6[15:08] BLMFaults7[07:00] BLMFaults7[15:08] HV Threshold Error 18 Output[07:00] Trigger[07:00] Link Node Status Link Response BLM (0x81) Unicast Byte Timestamp Seconds past Epoch 4 Timestamp NanoSeconds[16:00] Pulse ID[14:00] 8 TimeSlot Link Node ID S1[07:00] S1[15:08] C S2[07:00] S2[15:08] S3[07:00] S3[16:08] 10 S4[07:00] S4[15:08] S5[07:00] S5[15:08] 14 S6[07:00] S6[15:08] Status1[07:00] Status1[15:08] Status2[07:00] Status2[15:08] BLMFaults0[07:00] BLMFaults0[15:08] BLMFaults1[07:00] BLMFaults1[15:08] BLMFaults2[07:00] BLMFaults2[15:08] BLMFaults3[07:00] BLMFaults3[15:08] BLMFaults4[07:00] BLMFaults4[15:08] BLMFaults5[07:00] BLMFaults5[15:08] BLMFaults6[07:00] BLMFaults6[15:08] BLMFaults7[07:00] BLMFaults7[15:08] HV Threshold Error 18 Output[07:00] Trigger[07:00] Link Node Status Jeff Olsen Page 25 9/25/2009

26 Status Bits [31:12] Reserved [11] IP Interface Timeout [10] QADC Timeout [09] HV ADC Timeout [08] Acquisition Sequencer Timeout [07] 360 Hz BLM Trigger missed [06:00] Reserved Comment [jjo18]: New Link Node Status Bits [03] UDP Error IPV4 Type not UDP [02] MPS Version Error MPS Version wrong [01] MPS Type Error MPS Type wrong [00] RX Message Error Trigger Byte [07:04] [03:00] Trigger Input Status Trigger Output Status Jeff Olsen Page 26 9/25/2009

27 BSA BLM Message (0xB0) Unicast Byte Timestamp Seconds past Epoch 2 4 Timestamp NanoSeconds[16:00] Pulse ID[14:00] 3 8 TimeSlot Link Node ID Channel 0 Baseline 1 C Channel 0 Q p _Beam Channel 0 Q 1 _Beam_L 2 10 Channel 0 Q 1 _Beam_H Channel 0 Q 10 _Beam_L 3 14 Channel 0 Q 10 _Beam_H Channel 0 Q 30 _Beam_L 4 18 Channel 0 Q 30 _Beam_H Channel 0 Q 60 _Beam_L 5 1C Channel 0 Q 60 _Beam_H Channel 0 Q p _Test 6 20 Channel 0 Q 1 _Test_L Channel 0 Q 1 _Test_H 7 24 Channel 1 Baseline Channel 1 Q p _Beam 8 28 Channel 1 Q 1 _Beam_L Channel 1 Q 1 _Beam_H 9 2C Channel 1 Q 10 _Beam_L Channel 1 Q 10 _Beam_H Channel 1 Q 30 _Beam_L Channel 1 Q 30 _Beam_H Channel 1 Q 60 _Beam_L Channel 1 Q 60 _Beam_H Channel 1 Q p _Test Channel 1 Q 1 _Test_L 13 3C Channel 1 Q 1 _Test_H Channel 2 Baseline Channel 2 Q p _Beam Channel 2 Q 1 _Beam_L Channel 2 Q 1 _Beam_H Channel 2 Q 10 _Beam_L Channel 2 Q 10 _Beam_H Channel 2 Q 30 _Beam_L 17 4C Channel 2 Q 30 _Beam_H Channel 2 Q 60 _Beam_L Channel 2 Q 60 _Beam_H Channel 2 Q p _Test Channel 2 Q 1 _Test_L Channel 2 Q 1 _Test_H Channel 3 Baseline Channel 3 Q p _Beam 21 5C Channel 3 Q 1 _Beam_L Channel 3 Q 1 _Beam_H Channel 3 Q 10 _Beam_L Channel 3 Q 10 _Beam_H Channel 3 Q 30 _Beam_L Channel 3 Q 30 _Beam_H Channel 3 Q 60 _Beam_L Channel 3 Q 60 _Beam_H 25 6C Channel 3 Q p _Test Channel 3 Q 1 _Test_L Channel 3 Q 1 _Test_H Channel 4 Baseline Channel 4 Q p _Beam Channel 4 Q 1 _Beam_L Channel 4 Q 1 _Beam_H Channel 4 Q 10 _Beam_L 29 7C Channel 4 Q 10 _Beam_H Channel 4 Q 30 _Beam_L Channel 4 Q 30 _Beam_H Channel 4 Q 60 _Beam_L Channel 4 Q 60 _Beam_H Channel 4 Q p _Test Channel 4 Q 1 _Test_L Channel 4Q 1 _Test_H 33 8C Channel 5 Baseline Channel 5 Q p _Beam Channel 5 Q 1 _Beam_L Channel 5 Q 1 _Beam_H Channel 5 Q 10 _Beam_L Channel 5 Q 10 _Beam_H Channel 5 Q 30 _Beam_L Channel 5 Q 30 _Beam_H 37 9C Channel 5 Q 60 _Beam_L Channel 5 Q 60 _Beam_H 38 A0 Channel 5 Q p _Test Channel 5 Q 1 _Test_L 39 A4 Channel 5 Q 1 _Test_H Channel 6 Baseline 40 A8 Channel 6 Q p _Beam Channel 6 Q 1 _Beam_L 41 AC Channel 6 Q 1 _Beam_H Channel 6 Q 10 _Beam_L 42 B0 Channel 6 Q 10 _Beam_H Channel 6 Q 30 _Beam_L 43 B4 Channel 6 Q 30 _Beam_H Channel 6 Q 60 _Beam_L 44 B8 Channel 6 Q 60 _Beam_H Channel 6 Q p _Test 45 BC Channel 6 Q 1 _Test_L Channel 6 Q 1 _Test_H 46 C0 Channel 7 Baseline Channel 7 Q p _Beam 47 C4 Channel 7 Q 1 _Beam_L Channel 7 Q 1 _Beam_H 48 C8 Channel 7 Q 10 _Beam_L Channel 7 Q 10 _Beam_H 49 CC Channel 7 Q 30 _Beam_L Channel 7 Q 30 _Beam_H 50 D0 Channel 7 Q 60 _Beam_L Channel 7 Q 60 _Beam_H 51 D4 Channel 7 Q p _Test Channel 7 Q 1 _Test_L 52 D8 Channel 7 Q 1 _Test_H Link Node Status Jeff Olsen Page 27 9/25/2009

28 MPS Link Node Response Summary Dir Mitigation Mode = 0 BLM Mode = 1 BYKIK Mode = 2 MPG Mode = 3 PIC Mode = 4 UDP Len Code Rx Sync Sync Sync Sync Sync 13 0x51 Rx Status Unlatch Status Unlatch Status Unlatch Status Unlatch Status Unlatch 50 0x61 Rx BLM Unlatch 36 0x62 Rx PIC Unlatch 78 0x63 Rx Permit Permit Control 23 0x71 Tx Status Status Status Status Status 50 0xAC Tx BLM Faults 36 0xB1 Tx BSA 222 0xBA Tx PIC 78 0xC1 Jeff Olsen Page 28 9/25/2009

29 Input Assignments The generic MPS Link Node chassis has up to 6 inputs cards and 1 output card. S1 S2 S3 S4 S5 S6 S7 Bit 15 Chan 16 Chan 32 Chan 48 Chan 65 Chan 80 Chan 96 Trigger Input 1-4 Bit 8 Chan 9 Chan 25 Chan 41 Chan 57 Chan 73 Chan 89 Bit 7 Chan 8 Chan 24 Chan 40 Chan 56 Chan 72 Chan 88 Trigger Output 1-4 Outputs 1-8 Bit 0 Chan 1 Chan 17 Chan 33 Chan 49 Chan 65 Chan 81 Jeff Olsen Page 29 9/25/2009

30 Fiber Optic Transceiver data The Transceivers have diagnostics built in to facilitate component monitoring, fault isolation and predictive failure (See AVAGO app note 5016). All 512 bytes of diagnostic data is available in the Xilinx memory starting at location 0x1000. The byte data from the transceiver is read as 32 bit words. The following tables are from the AVAGO datasheet. For detailed information see AVAGO Datasheet. Serial ID data fields Address 0xA0 (from SFF-8472 MSA). BASE ID FIELDS Byte # Size Name Field Description Field 0 1 Identifier Type of serial transceiver 1 1 Ext. Identifier Extended identifier of type of serial transceiver 2 1 Connector Code for connector type Transceiver Code for electronic compatibility or optical compatibility 11 1 Encoding Code for serial encoding algorithm 12 1 BR, Nominal Nominal bit rate, units of 100 Mbits/sec Reserved 14 1 Length (9μm) km Link length supported for 9/125 Ïm fiber, units of km 15 1 Length (9μm) Link length supported for 9/125 Ïm fiber, units of 100m 16 1 Length (50μm) Link length supported for 50/125 Ïm fiber, units of 10m 17 1 Length (62.5μm) Link length supported for 62.5/125 Ïm fiber, units of 10m 18 1 Length (Copper) Link length supported for copper, units of meters 19 1 Reserved Vendor name SFP vendor name (ASCII) 36 1 Reserved Vendor OUI SRP vendor IEEE company ID Vendor PN Part number provided by SFP vendor (ASCII) Vendor rev Revision level for part number provided by vendor (ASCII) Wavelength Laser wavelength 62 1 Reserved 63 1 CC_BASE Check code for Base ID Fields (addresses 0 to 62) EXTENDED ID FIELDS Options Indicates which optional transceiver signals are implemented 66 1 BR, max Upper bit rate margin, units of % Jeff Olsen Page 30 9/25/2009

31 67 1 BR, min Lower bit rate margin, units of % Vendor SN Serial number provided by vendor (ASCII) Date Code Vendor s manufacturing date code 92 1 Diagnostic Monitoring Type Indicates which type of diagnostic monitoring is implemented (if any) in the transceiver 93 1 Enhanced Options Indicates which optional enhanced features are implemented (if any) in the transceiver 94 1 SFF-8472 Compliance Indicates which revision of SFF8472 the transceiver complies with 95 1 CC_EXT Check code for the Extended ID Fields addresses 64 to94 VENDOR SPECIFIC ID FIELDS Vendor Specific Vendor Specific EEPROM Reserved Reserved for future use Jeff Olsen Page 31 9/25/2009

32 EEPROM Serial ID Memory Contents Enhanced Feature Set Memory (Address A2h) Byte # 1 Temp H Alarm LSB [1] 34 Rx Pwr L Alarm MSB [5] 2 Temp L Alarm MSB [1] 35 Rx Pwr L Alarm LSB [5] 3 Temp L Alarm LSB [1] 36 Rx Pwr H Warning MSB [5] 4 Temp H Warning MSB [1] 37 Rx Pwr H Warning LSB [5] 5 Temp H Warning LSB [1] 38 Rx Pwr L Warning MSB [5] 6 Temp L Warning MSB [1] 39 Rx Pwr L Warning LSB [5] 7 Temp L Warning LSB [1] Reserved 8 Vcc H Alarm MSB [2] External Calibration Constants [6] 9 Vcc H Alarm LSB [2] 95 Checksum for Bytes 0-94 [7] 10 Vcc L Alarm MSB [2] 96 Real Time Temperature MSB [1] 11 Vcc L Alarm LSB [2] 97 Real Time Temperature LSB [1] 12 Vcc H Warning MSB [2] 98 Real Time Vcc MSB [2] 13 Vcc H Warning LSB [2] 99 Real Time Vcc LSB [2] 14 Vcc L Warning MSB [2] 100 Real Time Tx Bias MSB [3] 15 Vcc L Warning LSB [2] 101 Real Time Tx Bias LSB [3] 16 Tx Bias H Alarm MSB [3] 102 Real Time Tx Power MSB [4] 17 Tx Bias H Alarm LSB [3] 103 Real Time Tx Power LSB [4] 18 Tx Bias L Alarm MSB [3] 104 Real Time Rx average MSB [5] 19 Tx Bias L Alarm LSB [3] 105 Real Time Rx average LSB [5] 20 Tx Bias H Warning MSB [3] 106 Reserved 21 Tx Bias H Warning LSB [3] 107 Reserved 22 Tx Bias L Warning MSB [3] 110 Status/Control 23 Tx Bias L Warning LSB [3] 111 Reserved 24 Tx Pwr H Alarm MSB [4] 112 Flag Bits 25 Tx Pwr H Alarm LSB [4] 113 Flag Bits 26 Tx Pwr L Alarm MSB [4] 114 Reserved 27 Tx Pwr L Alarm LSB [4] 115 Reserved 28 Tx Pwr H Warning MSB [4] 116 Flag Bits 29 Tx Pwr H Warning LSB [4] 117 Flag Bits 30 Tx Pwr L Warning MSB [4] Reserved 31 Tx Pwr L Warning LSB [4] Customer Writeable 32 Rx Pwr H Alarm MSB [5] Vendor Specific 33 Rx Pwr H Alarm LSB [5] Notes: 1. Temperature (Temp) is decoded as a 16 bit signed twos compliment integer in increments of 1/256 C. 2. Supply Voltage (Vcc) is decoded as a 16 bit unsigned integer in increments of 100 μv. 3. Laser bias current (Tx Bias) is decoded as a 16 bit unsigned integer in increments of 2 μa. Jeff Olsen Page 32 9/25/2009

33 4. Transmitted average optical power (Tx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 μw. 5. Received average optical power (Rx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 μw. 6. Bytes are not intended for use with AFCT-57R5APZ, but have been set to default values per SFF Byte 95 is a checksum calculated (per SFF-8472) and stored prior to product shipment. Jeff Olsen Page 33 9/25/2009

34 Display LED s LED 4 Fault Detected 3 GLINK Error 2 GLINK Active 1 GLINK Locked Jeff Olsen Page 34 9/25/2009

35 Input Card (SLAC ) 16 channels of IDIM type inputs on a DB37 connector using Avago HCPL-063L. 4.7K Series resistor limits current to 5ma at 24V. Input Connector Pin 19 GND GND GND +24V V CH CH 15+ CH CH 14+ CH CH 13+ CH CH 12+ CH CH 11+ CH CH 10+ CH CH 9+ CH CH 8+ CH CH 7+ CH CH 6+ CH CH 5+ CH CH 4+ CH CH 3+ CH CH 2+ CH CH 1+ CH CH 0+ Jeff Olsen Page 35 9/25/2009

36 Output Card (SLAC ) The Output Card has 4 Trigger Outputs and 8 Isolated Outputs. Two of the Trigger Outputs (0 and 1) are controlled by the Link Node Processor over the Glink and are 3ms re-triggerable one-shots. Four of the Isolated Outputs (0, 1, 2 and 3) are controlled by the Link Node Processor over the Glink and are 3ms re-triggerable one-shots. 4 ea 50 ohm TTL Inputs using Philips 74LVC2G17DBVR Schmitt-Trigger 4 ea 50 ohm TTL Outputs using Philips N74F3037D Driver 8 ea Isolated Outputs using the Vishay VO1400A Solid State Relay (SSR) on a DB25 Connector. Load voltage 60 V, load current 100 ma. Lemo Inputs Channel Channel Connector 3 2 J4 1 0 J3 Lemo Outputs Channel Channel Connector 3 2 J2 1 0 J1 Jeff Olsen Page 36 9/25/2009

37 Isolated Outputs Pin 13 GND GND GND +24V V NC NC NC 22 9 Ch Ch 7+ Ch Ch 6+ Ch Ch 5+ Ch Ch 4+ Ch Ch 3+ Ch Ch 2+ Ch Ch 1+ Ch Ch 0+ Jeff Olsen Page 37 9/25/2009

38 LEMO Inputs Summary MPS Link Node Ch Mitigation Mode = 0 BLM Mode = 1 BYKIK Mode = 2 MPG Mode = 3 PIC Mode = Mhz Abort Trigger 119Mhz 1 Aux Trig Standby Trigger Beam Trig 2 BXKIK Input BXKIK 3 EVG Abort EVG Abort LEMO Outputs Summary Ch Mitigation Mode = 0 BLM Mode = 1 BYKIK Mode = 2 MPG Mode = 3 PIC Mode = 4 0 ADC Trigger BYKIK Abort ADC Trigger 1 TC TRIG 2 Stretched ADC Trigger Stretched ADC Trigger 3 Strobe Strobe Strobe Strobe Strobe Strobe is a 1ms pulse generated when a Sync Message is received on the MPS Link. Isolated Outputs Summary Ch Mitigation Mode = 0 BLM Mode = 1 BYKIK Mode = 2 MPG Mode = 3 PIC Mode = 4 Link Permit Link Output Link Permit Link Output CPU 0 Pockel Cell Output 0 HVPS Control 1 Mechanical Output 1 HVPS Control Shutter 2 BYKIK BYKIK Output 2 HVPS Control 3 Laser Heater Output 3 HVPS Control 4 Output 4 5 Output 5 6 Output 6 7 Output 7 Jeff Olsen Page 38 9/25/2009

39 Link Node Configuration (0x00) Lemo Inputs for Mitigation Control Mode Channel Function Lemo Outputs for Mitigation Control Mode Channel Function Stretched Link Status Strobe Isolated Outputs for Mitigation Control Mode Channel Function 0 Pockel Cell Controlled by 1 Mechanical Shutter LINK Node 2 BYKIK Processor 3 Laser Heater 5ms Jeff Olsen Page 39 9/25/2009

40 BLM Configuration (0x01) MPS Link Node Lemo Inputs for BLM Configuration Channel Function 0 119Mhz Clock Lemo Outputs for BLM Configuration Channel Function 0 ADC Trigger 1 2 Stretched ADC Trigger 3 Stretched Link Status Strobe Isolated Outputs for BLM Configuration Channel Function Jeff Olsen Page 40 9/25/2009

41 BYKIK Configuration (0x02) Lemo Inputs for BYKIK Configuration Channel Function 0 Abort Trigger 120 and 30 Hz DeadMan 1 Standby Trigger 120 and 30 Hz DeadMan 2 BXKIK Input 3 EVG Abort Single Shot Mode Lemo Outputs for BYKIK Configuration Channel Function 0 BYKIK Abort Stretched Link Status Strobe Isolated Outputs for BYKIK Configuration Channel Function 0 Controlled by Link Node Permit 1 Message Processor (0x71) 2 BYKIK 3 4 From CPU Jeff Olsen Page 41 9/25/2009

42 MPG Mode Configuration (0x03) Lemo Inputs for MPG Node Configuration Channel Function Lemo Outputs for MPG Node Configuration Channel Function Stretched Link Status Strobe Isolated Outputs for MPG Node Configuration Channel Function 0 Output 0 Controlled by 1 Output 1 Link Node Output 2 Output 2 Message (0x41). 3 Output 3 5ms 1 Shot 4 Output 4 5 Output 5 6 Output 6 7 Output 7 Jeff Olsen Page 42 9/25/2009

43 PIC Mode Configuration (0x04) Lemo Inputs for PIC Node Configuration Channel Function Lemo Outputs for PIC Node Configuration Channel Function 0 ADC Trigger 1 2 Stretched ADC Trigger 3 Stretched Link Status Strobe Isolated Outputs for PIC Node Configuration Channel Function 0 Controlled by 1 EPIC s HV On Pulse 55ms 5 HV Off Pulse 55ms 6 7 Jeff Olsen Page 43 9/25/2009

44 BLM Functionality IP BUS COLD FIRE XILINX Address Decoder Controll er BLM Interface Write FIFO 64 Words Threshold Memory HV DAC HV ADC BLM Sequencer Q ADC Read Memory Spare ID Memory 16Kx16 Link Node Link Node Fault Memory Faults BSA BSA BSA Data BSA 119Mhz Trigger Trigger The Cold Fire can write to the BLM Interface Write FIFO or Threshold Memory any time. The BLM Sequencer will transfer the data from the Write FIFO to the appropriate IP Device after the next BLM Acquisition cycle and current state of the IP Devices has been read and put into the BLM Interface Read Memory. Jeff Olsen Page 44 9/25/2009

45 Read IP ID s Initialize IP Cards Wait For Done Read IP Cards Compare Thresholds Generate Faults Write Memory FIFO Empty No Write FIFO Data To IP Cards Yes Jeff Olsen Page 45 9/25/2009

46 BLM Acquisition Interface Configuration HV Set Points - ACROMAG IP DAC The High Voltage for the BLM system is set using the ACROMAG IP DAC configured for +/- 10V, Offset Binary. Data Format Control Hex Counts PEP and Argon HV Voltage xFFFF KV x KV x NA Counts = (V +10) /20 * = V* The PEP and Argon BLM power supply control voltage is 0 to +10V corresponding to an output of 0 to -10KV Counts = ((-1*HV/1000) +10)/20 * = -1* HV * Configuration Registers for IP231 and default settings Offset 0x00 DAC Channel 0 R/W 0x02 DAC Channel 1 R/W 0x04 DAC Channel 2 R/W 0x06 DAC Channel 3 R/W 0x08 DAC Channel 4 R/W 0x0A DAC Channel 5 R/W 0x0C DAC Channel 6 R/W 0x0E DAC Channel 7 R/W 0x10 DAC Channel 8 R/W 0x12 DAC Channel 9 R/W 0x14 DAC Channel 10 R/W 0x16 DAC Channel 11 R/W 0x18 DAC Channel 12 R/W 0x1A DAC Channel 13 R/W 0x1C DAC Channel 14 R/W 0x1E DAC Channel 15 R/W 0x20 Transparent Mode W 0x22 Simultaneous Mode W Jeff Olsen Page 46 9/25/2009

47 0x24 Simultaneous Output Trigger W 0x26 DAC Write Status R 0x28 Control Register W Data Format is Offset Binary. Initial Setup Read IP ID data Set Bit 7 in Control Register to Reset the Board. Set DAC Channels 0-7 to Initial Values in Xilinx Set DAC Channels 8-15 to zero. Set Transparent Mode by writing to the Transparent Mode Register Usage Writes from EPIC s are set to the DAC Channels 0 7. Jeff Olsen Page 47 9/25/2009

48 ACROMAG IP330A ADC HV Read Back - ACROMAG IP330 ADC The High Voltage for the BLM system is read back from the ACROMAG IP330A ADC configured for +/- 10V, Offset Binary. Data Format Argon HV Monitor Hex Counts Voltage -9.9KV xFFFF KV x NA x Data Format PEPII HV Monitor Hex Counts Voltage -9.9KV xC KV x NA x HV (Argon) = -1 * ( (Counts ) / ) * 1000 HV (PEP) = -2 * ( (Counts ) / ) * 1000 The Argon BLM power supply monitor voltage is 0 to +10V corresponding to an output of 0 to -10KV. The PEP BPM power supply monitor voltage is 0 to +5V corresponding to an output of 0to -10KV. Registers Offset MSB LSB Offset 0x00 Control Register 0x01 0x02 Timer Prescale Interrupt Vector 0x03 0x04 Conversion Timer 0x05 0x06 End Channel Start Channel 0x07 0x08 New Data Channels x09 0x0A New Data Channels x0B 0x0C Missed Data Channels x0D 0x0E Missed Data Channels x0F 0x10 Start Convert 0x11 Jeff Olsen Page 48 9/25/2009

49 Initial Configuration Control Register (0x00) Bits Function Use Value [15:14] Unused 00 [13:12] Interrupt Control Disable 00 [11] Timer Disable 0 [100:8] Scan Mode Burst Single 100 [070:6] Unused 00 [05:03] Acquisition Mode Differential Input 000 [02] External Trigger Input 0 [01] Data Format Offset Binary 1 [00] Unused 0 0x0402 Start/End Channel (0x06) Bits Function Use Value [15:13] Unused 000 [12:8] End Channel Channel [07:05] Unused 000 [04:00] Start Channel Channel x0700 Gain Registers (0x20 0x26) Bits Function Use Value [15:10] Unused [090:8] Gain Channel 0 00 [07:02] Unused [01:00] Gain Channel x0000 Data Registers 0x40 0x4E Offset Binary Data ALPHI Technologies ATC-AD41meg ADC The ALPHI Tech ATC-AD41MEG ADC is used to read the ByKik waveform. It is configured as a +/- 10V, Offset Binary. Jeff Olsen Page 49 9/25/2009

50 Data Format ByKik Hex Counts Voltage xFFFF x x Volts = (Counts ) / ) MPS Link Node Registers Offset MSB LSB Offset 0x00 Internal Clock Divisor 0 0x01 0x02 Internal Clock Divisor 1 0x03 0x04 Internal Clock Divisor 2 0x05 0x06 Channel Mask 0x07 0x08 Trigger Event 0x09 0x0A Unused 0x0B 0x0C Stop Acquisition 0x0D 0x0E Acquisition Control 0x0F 0x10 Source Intreq1 0x11 0x12 Clear Intreq0 Latch 0x13 0x14 0x15 0x16 FIFO Control/Status 0x17 0x18 Reset FIFO 0x18 0x1A Hardware FIFO 0x1B 0x1C Unused 0x1D 0x1E Unused 0x1F 0x20 Unused 0x21 0x22 Unused 0x23 0x24 Unused 0x25 0x26 Start Acquisitions 0x27 0x28 Interrupt Vector 0x29 0x2A A/D Converter Setup 0x2B 0x2C Unused 0x2D 0x2E Unused 0x2F 0x30 FIFO DMA 0x31 0x32 FIFO DMA 0x33 0x34 FIFO DMA 0x35 0x36 FIFO DMA 0x37 0x38 FIFO DMA 0x39 0x3A FIFO DMA 0x3B 0x3C FIFO DMA 0x3D 0x3E FIFO DMA 0x3E Jeff Olsen Page 50 9/25/2009

51 Internal Clock Divisor 0 (0x01) Bits Function Use Value [07:04] IP Clock Divider 32Mhz/(31+1) 0x1F 0x1F Internal Clock Divisor 0 (0x03) Bits Function Use Value [07:04] IP Clock Divider 32Mhz/(31+1) 0 0x00 Internal Clock Divisor 0 (0x05) Bits Function Use Value [07:04] IP Clock Divider 32Mhz/(31+1) 0 0x00 Channel Mask (0x07) Bits Function Use Value [07:04] Unused [03:00] Channel Mask x0E Acquisition Control (0x0F) Bits Function Use Value [07:06] Sample Clock 32 Mhz IP Clock 00 Source [05:04] Trigger Source External Trigger 00 [03:02] Stop Acquisition FIFO PAF Flag 00 Source [01:00] Trigger Source Enable after PAE 00 0x00 FIFO Control/Status (0x17) Bits Function Use [07] FIFO FF FIFO Full [06] FIFO PAF FIFO Almost Full [05] FIFO PAE FIFO Almost Empty [04] FIFO EF FIFO Empty [03:01] Unused [00] FIFO Register 1 => FIFO Register Access 0 => FIFO Data Access FIFO A/D Converter (0x2B) Bits Function Use Value Jeff Olsen Page 51 9/25/2009

52 [07] OB/2C Straight Binary 1 [06] WARP Warp Mode 1 [05] IMPULSE Normal 0 [04] Byte Swap Normal 0 [03:00] Unused 0xC0 Known BUGS in the ATC-AD41meg 1. Will not respond to Back-Back Read cycles. Must have at least 1 IDLE state between ACK and the next SEL. 2. FIFO Register requires additional address setup time. 3. In an 8Mhz backplane, you can not set the Clock divider to less than 12 or the module will not respond. This means that on an 8Mhz backplane, the fastest you can run the 1Megasample ADC is 650K. Jeff Olsen Page 52 9/25/2009

53 Possible Status Bits 1 E_TxLock Gigabit Ethernet transmit clock locked 2 E_RxLock Gigabit Ethernet receive clock locked 3 Event_Lock Event Receiver Clock locked 4 Timing_Lock 119Mhz Timing Clock locked 5 PS_OK Power Supplies within tolerance 6 Missing_Sync G-Link sync not received for > 3ms 7 SFP1 Not Present G-Link SFP Not Present 8 SFP2 Not Present Event Receiver SFP Not Present 9 Jeff Olsen Page 53 9/25/2009

54 Power Consumption With Arcturus booted, Fibers connected with 250Mhz Clock No IP cards, No IO cards Voltage Measured Current Power Notes 3.3V 1.64A 5.41W Arcturus, Xilinx, IP Translators A 1.65W SFP 3.3V, IP Translators, IP Cards 03/05/08 With Arcturus, Link, and EVR 3.3V 3.2V 2.2A 7.04W 5.0V 4.99V W Jeff Olsen Page 54 9/25/2009

55 Document Version History MPS Link Node Version Date V01 04/14/08 Original V02 04/14/08 Changed Link Message types Added Permit message type V03 06/26/08 Fixed Permit Message Definition V04 07/29/08 Added Virtual Cards BYKIK Abort trigger logic Added Link Status Readback Added BYKIK ADC Trig Control registers V1.0 09/14/09 Convert Link Node Document to BLM specific Document Jeff Olsen Page 55 9/25/2009

56 FPGA Version History MPS Link Node Version Date V01 09/21/07 11/02/07 Saved as mpsnode_xv01 V02 11/02/07 Added IP Interface to V01 V03 11/07/07 Add USB Interface 01/14/08 Completed GigaBit Interface 3 Released board to Dayle Saved as V03.zip V04 01/14/08 Added Broadcast Output mode Op 62 Fixed a couple of bugs in decoding the Broadcast Fixed end of frame response V10 02/22/08 Added Timing Fiber Interface 03/25/08 Changed IO Card to Slot 7 instead of Slot 1. Shifted Inputs Cards to Slot 1 6. Did NOT fix schematics yet. V11 05/06/08 First Production release. Removed Timing interface, it is not used in MPS Link Node. Was a test for MKSU. V12 Fixed intermittent Arcturus crash by using the correct clock edge for the TA signal V13 06/17/08 Swapped the input Byte order in the Status message V14 06/26/08 Fixed Permit Message V15 07/29/08 Added Virtual Cards 08/06/08 Added Deadman to inputs 08/13/08 BYKIK Abort Trigger Logic 120 and 30 Hz DeadMan on Trigger inputs V16 08/19/08 Fixed DeadMan Circuit V17 09/26/08 Delivered V16 to Dayle, so I changed the version. Working on BLM/BSA interface V18 10/02/08 Delivered V17 to Steve. Fixed error in BLM message length V19 10/10/08 Added BYKIK ADC Threshold V20 BLM/PIC interface V21 12/03/08 ByKIK Single shot Jeff Olsen Page 56 9/25/2009