Chuck Corley. NPD Applications Engineering

Transcription

1 Chuck Corley NPD Applications Engineering June 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc..

2 Higher frequency operation and ever smaller geometries for microprocessors increase the challenges of supplying stable voltage(s) from the Power Distribution Network (PDN) on the printed circuit board (PCB). Additionally, at lower operating voltages there is less margin for error in the DC voltage supply value despite high static current demand. While modern voltage regulators address this problem, the PDN on the PCB must be carefully designed to preserve a stable voltage at the microprocessor despite fluctuating current demand at a wide range of frequencies. This presentation will examine how to design for a tighter DC specification of ± 3% and an AC specification of ± 5%. 2

3 Defining the problem 3% DC voltage requirement Time versus frequency domain Designing the PDN Validating the PDN design 3

4 Requirements Power Supply must supply a stable voltage reference Power Supply must distribute adequate current Problems: Switching power supplies actually supply a digitally varying voltage (~600 KHz) Microprocessor s current demand varies at core frequency (~2GHz) Power Distribution Network (PDN) has resistance, capacitance, inductance, mutual capacitance, and mutual inductance through PCB, socket, vias, and die. Need to solve problems in the time and frequency domains with a time domain specification. 4

5 c 1.10 Core and Platform Supply Voltage 1.0V ± 30 mv Combined DC and AC variance from nominal not to exceed ±50 mv except for an overshoot of less than +100 mv for less than 1 us during transients. Transient voltages may result from current steps of up to 20A with slew rates of 12 A/us max. Volts 1 us 60 Amps % AC 10% >500KHz % DC 12 A/us T4240 Voltage spec 40 Final T4240 Current TBD t (us) t (us)

6 Noise on VDD_CA (sense): ~142 mv P-P or ± 6.5% 6

7 Well documented problem (see references slide) Customers are demanding more information from silicon vendors to aid in solution. Silicon vendors are tightening the DC specifications while better clarifying the transient behavior. Ideally, silicon vendors would supply target impedance as a function of frequency. 7

8 impedance, ohms? 1E+01 1E+00 VRM On-chip, package 1E-01 1E-02 Board level PDN design 1E-03 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 1E+10 freq, Hz P mV T4240 3% ΔV(f)/ ΔI(f) =Ztarget 8

9 Static timing requires paths to finish inside 1 cycle. (most paths) For e5500 on P5020, the core was timed to 460ps % of Paths Still Toggling After Clock Edge at t=0 (blue)

10 Defining the problem Designing the PDN Using Rules of Thumb PDN design in one dimension In Excel In Spice PDN design in two dimensions Altera s app note PDN design in three dimensions Sigrity OptimizePI Validating the PDN design 10

11 the device can generate transient power surges and high frequency noise in its power supply noise must be prevented, and the chip requires a clean, tightly regulated source of power. place at least one decoupling capacitor at each VDD, BVDD, OVDD, CVDD, GVDD, and LVDD pin of the chip. utilizing short traces to minimize inductance directly under the device [or] surrounding the part. capacitors should have a value of 0.01 or 0.1 μf. ceramic SMT (surface mount technology) to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB to enable quick recharging of the smaller chip capacitors. low ESR (equivalent series resistance) connected through two vias to minimize inductance. Suggested bulk capacitors μf (AVX TPS tantalum or Sanyo OSCON). 11

12 VDD_CA 18 pins SENSEVDD_CA VRM.002 Ω 1ea 47uF 4ea 1000uF senser 6ea 47uF 4ea 1.0uF 4ea 0.1uF 4ea 0.01uF 2ea 2.2uF 4ea 1000pF.14Ω.0075Ω.14Ω.012Ω.028Ω.06Ω.006Ω.16Ω 2.2nH.57nH 2.2nH.4nH.4nH.4nH.4nH.4nH Plane(s) 1750pF.001 Ω.03 nh.085 Ω 50 nf.0003 Ω Iac ea ~5.6 sq ins PDN PKG DIE By my definition: Two dimensional view would include vias and spreading resistance/inductance Three dimensional view would include mutual inductance of vias and board stackup 12

13 Impedance (Ω) 1.E+01 P5020 Development System Impedance 1.E+00 1.E-01 1.E-02 Total VRM 1ea 47uF 4ea 1000uF 6ea 47uF 4ea 1.0uF 4ea 0.1uF 4ea.01uF 2ea 2.2uF 4ea 1000pF Plane 1.E-03 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency (Hz) 13

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15 Impedance (Ω) Zvrm Ztarget Zeff Zs Zh = Zs + Zv Zv Ftarget E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 Frequency (Hz) 15

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17 Z (f) = VDD_cr0(f) / I senser (f) 17

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19 Red curve is 3D (based on board file) analysis of RevA using Freescale s original decoupling capacitors Blue curve is lower component count solution found by OptimizePI (22 decaps instead of Freescale s original 33) 1MHz 10MHz 100MHz 19

20 OptimizePI also minimizes number of capacitors and/or cost 20

21 Defining the problem Time versus frequency domain 3% DC voltage requirement Designing the PDN Validating the PDN design Sweep frequency stimulus Time domain voltage measurement Frequency domain impedance measurement 21

22 TIME DOMAIN: To confirm or correct: current steps of up to 20A with slew rates of 12 A/us max. statement from the spec and use as di/dt value in impedance simulations. FREQUENCY DOMAIN: To measure, on a system, the PDN impedance over frequency. Fortunately, the QorIQ Power Architecture microprocessors architecturally support a programmatic means (the wait instruction) for alternating between high current consumption and very low current consumption. For multiple cores, we can alternate between higher than normal customer usage and lower than normal customer usage. The results should be very useful for PDN design and validation. 22

23 Programmatically cause the actual die to represent a variable load at controlled frequencies. Current High minimal power wait instruction Low power intensive instructions minimal power wait instruction power intensive instructions decr intrpt decr intrpt decr intrpt cr3.eq = 0* cr3.eq = 1* cr3.eq = 0* cr3.eq = 1* decr intrpt Max frequency = platform clk/16 Voltage GPIO[7] signal for o scope sync *cr3.eq is toggle to tell the ISR whether returning to low or high power code. 23

24 wait stops synchronous processor activity until an asynchronous interrupt occurs. The processor may use this to reduce power consumption. When an interrupt occurs while the processor is waiting, its associated save/restore register 0 will point to the instruction following the wait. Current Core frequency stays constant. Power switches from HI to LO and back on decrementer interrupt. Hypothesis: current is constant for HI and LO at all decrementer frequencies. I max I static 0 0 C max V 2 f C wait V 2 f HI LO f 24

25 Voltage Current GPIO 25

26 Voltage Current GPIO At 1333 MHz core 96 V/s 248 V/s -71 V/s 26

27 Recommend you attend FTF-NET-F0369, Linear Technology: Design Guidelines & Solutions for Implementing a Power Distributions System to meet the 3% Core Tolerance Specification for QorIQ Processors Thursday, 9:30AM V OUT (100mV/div) V O_PP Overshoot I OUT (20A/div) Undershoot Step-Up I O Step-Down 27

28 Voltage Current GPIO At 1333 MHz core 31 A/ms A/ms 28

29 Defining the problem Time versus frequency domain 3% DC voltage requirement Designing the PDN Validating the PDN design Sweep frequency stimulus Time domain voltage measurement Frequency domain impedance measurement 29

30 CPU high current demands require: Very low impedance power network Package to silicon interface that uses thousands of bumps Challenge how to measure accurately the CPU power network impedance profile? VNA measurement methods not applicable Can not feed thousands of bumps Can not perform the measurement with the silicon mounted on the package Lacks the interaction between die, Cdie, and the power network * CPU Power Supply Impedance Profile Measurement Using FFT and Clock Throttling, Alex Waizman, EPEP

31 Use: CPU die PLL bypass mode to generate a controlled stimulus Oscilloscope FFT capabilities for impedance extraction Flip-Flops are distributed across the whole die Many C4 bumps consume CPU current We get full interaction between die, die decoupling and power network In a paper by the same author, he says: A method that allows CPU power delivery impedance profile measurements by running controlled code on the CPU die that stimulates a controlled current consumption by the CPU is described in reference [1]. However, not all computer architectures allow easy generation of controlled current consumption codes with a repetitive pattern. 31 * CPU Power Supply Impedance Profile Measurement Using FFT and Clock Throttling, Alex Waizman, EPEP 2007

32 The resulting Icc square wave can be decomposed into it s Fourier series components ICC 1st Harm 3rd Harm 5th Harm

33 Decrementer (and other timer) interrupts are programmable in multiples of Platform Clock Frequency/16 and Platform Clock Frequency/32 for P At Platform Clock of 600 MHz (decrementer = n x 26.7ns): Decrementer Cnt 2 xt DEC F=1/(2 xt DEC ) 3 x F 5 x F 50,000, s 0.37 Hz 1.12 Hz 1.87 Hz μs 93 KHz 281 KHz 469 KHz μs 187 KHz 562 KHz 937 KHz μs 937 KHz 2.81 MHz 4.69 MHz ns 1.87 MHz 5.62 MHz 9.37 MHz ns 9.37 MHz MHz MHz 1 53 ns MHz MHz MHz 33

34 Decrementer (and other timer) interrupts are programmable in multiples of Platform Clock Frequency/16 for P4080 and Platform Clock Frequency/32 for P5020. At Platform Clock of 800 MHz (decrementer = n x 20ns): Decrementer Cnt 2 xt DEC F=1/(2 xt DEC ) 3 x F 5 x F 50,000,000 2 s 0.5 Hz 1.5 Hz 2.5 Hz μs 125 KHz 375 KHz 625 KHz μs 250 KHz 750 KHz 1.25 MHz ns 1.25 MHz 3.75 MHz 6.25 MHz ns 2.5 MHz 7.5 MHz 12.5 MHz 2 80 ns 12.5 MHz 37.5 MHz 62.5 MHz 1 40 ns 25 MHz 75 MHz 125 MHz 34

35 The current for a square wave can be measured at low frequency and it s Fourier components assumed to remain constant as frequency increases (though they may not be measurable) The Fourier decomposition of Vdd_sense can be measured with an oscilloscope. And impedance as a function of frequency can be computed at up to 5 times the fundamental frequency of the square wave. F{V dd_sense (f)} = Z(f) * F{I cc (f)} Alex Waifman CPU Power Supply Impedance Profile Measurement Using FFT and Clock Gating Electrical Performance of Electronic Packaging, 2003, pp:

36 We can measure CPU current here at low frequency here We can measure die voltage here 36

37 0.1 Z'(f) E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 37

38 Impedance (Ω) Compute in Excel (1D) 1.E+01 P5020 Development System Impedance Compute in LTSpice (1/2D) 1.E+00 1.E-01 1.E-02 Total VRM 1ea 47uF 4ea 1000uF 6ea 47uF 4ea 1.0uF 4ea 0.1uF 4ea.01uF 2ea 2.2uF 4ea 1000pF Plane Z'(f) E-03 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E Compute in Altera Tool (2D) Compute in OptimizePI (3D) 10 Zvrm E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E Ztarget Zeff Measure Zs Zh = Zs + Zv Ftarget Zv 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 Frequency (Hz) 38

39 We can measure CPU current here And here, etc We can measure CPU voltage here 39

40 Higher frequency parts are drawing more current with faster transitions. Characterization of current and change in current on new silicon is tardy and inadequate relative to what is needed for PDN design. Specification calls for even more accurate voltage (± 3%) while trying to allow for inevitable transients (± 5-10%) that exist in system and on IC testers. Rules-of-thumb are no longer sufficient; analysis is required from simple Excel to three-dimensional finite element analysis depending on how much risk the designer can tolerate. The more accurate the system simulation the more demand there is for accurate die and package models that are not yet available. 40

41 1. Extended Adaptive Voltage Positioning (EAVP), Alex Waizman and Chee-Yee Chung, pp 65-68, CPU Power Supply Impedance Profile Measurement Using FFT and Clock Gating, Alex Waizman, pp 29-32, Resonant Free Power Network Design Using Extended Adaptive Voltage Positioning (EVAP) Methodology, Alex Waizman and Chee-Yee Chung, IEEE Transactions on Advanced Packaging, Vol. 24, No. 3, August A Resonance-Free Power Delivery System Design Methodology Applying 3D Optimized Extended Adaptive Voltage Positioning, Tao Xu and Brad Brim, pp , Integrated Power Supply Frequency Domain Impedance Meter (IFDIM), Alex Waizman, pp , Power Delivery Network (PDN) Tool User Guide, Altera, March

42 7. High-Speed Digital Design: A Handbook of Black Magic, Howard Johnson and Martin Graham, Prentice-Hall, Frequency-Domain Characterization of Power Distribution Networks, Istvan Novak and Jason R. Miller, Artech House, 2007 Facebook.com/Freescale Tag yourself in photos and upload your own! Tweeting? Please use hashtag #FTF2012 Session materials will be Look for announcements in the FTF Group on LinkedIn or follow Freescale on Twitter 42

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