FDPC5030SG. POWERTRENCH Power Clip 30 V Asymmetric Dual N Channel MOSFET

Transcription

1 POWERTRENCH Power Clip V Asymmetric Dual N Channel MOSFET General Description This device includes two specialized N-Channel MOSFETs in a dual package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET () and synchronous SyncFET () have been designed to provide optimal power efficiency. ELECTRICAL CONNECTION Features : N-Channel Max R DS(on) = 5. m at V GS = V, I D = 7 A Max R DS(on) = 6.5 m at V GS = 4.5 V, I D = 4 A : N-Channel Max R DS(on) =.4 m at V GS = V, I D = 5 A Max R DS(on) = 3. m at V GS = 4.5 V, I D = A Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses. MOSFET Integration Enables Optimum Layout for Lower Circuit Inductance and Reduced Switch Node Ringing. RoHS Compliant Applications Computing Communications General Purpose Point of Load Table. PIN DESCRIPTION Pin Name Description HSG High Side Gate GR Gate Return 3, 4, V+(HSD) High Side Drain 5, 6, 7 SW Switching Node, Low Side Drain 8 LSG Low Side Gate 9 GND (LSS) Low Side Source N-Channel MOSFET Top View Bottom View Power Clip 56 (PQFN8 5x6) CASE 483AR HSG GR V+ V+ PIN ASSIGNMENT * GND(LSS) PAD *PAD V+(HSD) MARKING DIAGRAM $Y&Z&3&K FDPC 5SG LSG SW SW SW PIN $Y = ON Semiconductor Logo &Z = Assembly Plant Code &3 = Numeric Date Code &K = Lot Code = Specific Device Code ORDERING INFORMATION See detailed ordering and shipping information on page of this data sheet. Semiconductor Components Industries, LLC, 6 January, 9 Rev. 3 Publication Order Number: /D

2 MOSFET MAXIMUM RATINGS (T A = 5 C, Unless otherwise specified) Symbol Parameter Unit V DS Drain to Source Voltage V Bvdsst Bvdsst (Transient) < ns V V GS Gate to Source Voltage +/ +/ V I D Drain Current Continuous (T C = 5 C) (Note 5) Continuous (T C = C) (Note 5) Continuous (T A = 5 C) 7 (Note a) 5 (Note b) Pulsed (T A = 5 C) (Note 4) 7 53 A E AS Single Pulsed Avalanche Energy (Note 3) mj P D Power Dissipation for Single Operation (T C = 5 C) (T A = 5 C) (T A = 5 C) 3. (Note a). (Note c) 5.3 (Note b). (Note d) W T J, T STG Operating and Storage Junction Temperature Range 55 to +5 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS Symbol Parameter Unit R JC Thermal Resistance, Junction to Case C/W R JA Thermal Resistance, Junction to Ambient (Note a) 55 (Note b) C/W R JA Thermal Resistance, Junction to Ambient (Note c) (Note d) C/W PACKAGE MARKING AND ORDERING INFORMATION Device Top Marking Package Reel Size Tape Width Quantity Power Clip 56 3 mm 3, Units ELECTRICAL CHARACTERISTICS (T J = 5 C unless otherwise noted) Symbol Parameter Test Conditions Type Min Typ Max Unit OFF CHARACTERISTICS BV DSS Drain to Source Breakdown Voltage I D = 5 A, V GS = V I D = ma, V GS = V V BV DSS / T J Breakdown Voltage Temperature Coefficient I D = 5 A, referenced to 5 C I D = ma, referenced to 5 C 5 6 mv/ C I DSS Zero Gate Voltage Drain Current V DS = 4 V, V GS = V V DS = 4 V, V GS = V 5 A I GSS Gate to Source Leakage Current, Forward V GS = V, V DS = V V GS = V, V DS = V ± ± na na ON CHARACTERISTICS V GS(th) Gate to Source Threshold Voltage V GS = V DS, I D = 5 A V GS = V DS, I D = ma V V GS(th) / T J Gate to Source Threshold Voltage Temperature Coefficient I D = A, referenced to 5 C I D = ma, referenced to 5 C 5 3 mv/ C

3 ELECTRICAL CHARACTERISTICS (T J = 5 C unless otherwise noted) Symbol Parameter Test Conditions Type Min Typ Max Unit ON CHARACTERISTICS R DS(on) Drain to Source On Resistance V GS = V, I D = 7 A V GS = 4.5 V, I D = 4 A V GS = V, I D = 7 A, T J =5 C m V GS = V, I D = 5 A V GS = 4.5 V, I D = A V GS = V, I D = 5 A,T J =5 C g FS Forward Transconductance V DS = 5 V, I D = 7 A V DS = 5 V, I D = 5 A S DYNAMIC CHARACTERISTICS C iss Input Capacitance : V DS = 5 V, V GS = V, f = MHZ C oss Output Capacitance : V DS = 5 V, V GS = V, C rss Reverse Transfer Capacitance f = MHZ pf pf pf R g Gate Resistance SWITCHING CHARACTERISTICS t d(on) Turn-On Delay Time : V DD = 5 V, I D = 7 A, t r Rise Time R GEN = 6 : V DD = 5 V, I D = 5 A, t d(off) Turn-Off Delay Time R GEN = ns ns ns t f Fall Time 3 ns Q g Total Gate Charge V GS = V to V : V DD = 5 V, I D = 7 A : V DD = 5 V, I D = 5 A nc Q g Total Gate Charge V GS = V to 4.5 V : V DD = 5 V, I D = 7 A : V DD = 5 V, I D = 5 A nc Q gs Gate to Source Gate Charge : V DD = 5 V, I D = 7 A : V DD = 5 V, I D = 5 A nc Q gd Gate to Drain Miller Charge : V DD = 5 V, I D = 7 A : V DD = 5 V, I D = 5 A. 4.3 nc SOURCE-DRAIN DIODE CHARACTERISTICS V SD Source to Drain Diode Forward Voltage V GS =V, I S = 7 A (Note ) V GS =V, I S = 5 A (Note ) V t rr Reverse Recovery Time I F = 7 A, di/dt = A/ s Q rr Reverse Recovery Charge I F = 5 A, di/dt = A/ s Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTES:. R JA is determined with the device mounted on a in pad oz copper pad on a.5.5 in. board of FR4 material. R CA is determined by the user s board design ns nc 3

4 a) C/W when mounted on a in pad of oz copper. b) 55 C/W when mounted on a in pad of oz copper. SS SF DS DF G SS SF DS DF G c) C/W when mounted on a minimum pad of oz copper. d) C/W when mounted on a minimum pad of oz copper. SS SF DS DF G SS SF DS DF G. Pulse Test: Pulse Width < s, Duty cycle <.%. 3. : E AS of 54 mj is based on starting T J = 5 C; L = 3 mh, I AS = 6 A, V DD = V. V GS = V, % tested at L =. mh, I AS = A. : E AS of 96 mj is based on starting T J = 5 C; L = 3 mh, I AS = 8 A, V DD = V. V GS = V, % tested at L =. mh, I AS = 7 A. 4. Pulsed Id refer to Figure NO TAG and Figure NO TAG SOA graphs for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. 4

5 TYPICAL CHARACTERISTICS ( N-Channel) (T J = 5 C unless otherwise noted) ID, DRAIN CURRENT (A) 45 5 V GS = V V GS = 6 V V GS = 4.5 V V GS = 3.5 V V GS = 3 V PULSE DURATION = 8 ms DUTY CYCLE =.5% MAX V DS, DRAIN TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ONRESISTANCE V GS = 3 V PULSE DURATION = 8 ms DUTY CYCLE =.5% MAX V GS = 3.5 V V GS = 4.5 V V GS = 6 V V GS = V I D, DRAIN CURRENT (A) Figure. On Region Characteristics Figure. Normalized OnResistance vs. Drain Current and Gate Voltage NORMALIZED DRAIN TO SOURCE ONRESISTANCE I D = 7 A V GS = V T J, JUNCTION TEMPERATURE ( C) Figure 3. Normalized On Resistance vs. Junction Temperature rds(on), DRAIN TO SOURCE ONRESISTANCE (mw) 4 PULSE DURATION = 8ms DUTY CYCLE =.5% MAX T J = 5 o C I D = 7 A T J = 5 o C V GS, GATE TO SOURCE VOLTAGE (V) Figure 4. Normalized On Resistance vs. Gate to Source Voltage I D, DRAIN CURRENT (A) 45 5 PULSE DURATION = 8ms DUTY CYCLE =.5% MAX V DS = 5 V T J = 5 o C T J = 5 o C T J = 55 o C IS, REVERSE DRAIN CURRENT (A).. V GS = V T J = 5 o C T J = 5 o C T J = 55 o C V GS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Source to Drain Diode Forward Voltage vs. Source Current 5

6 TYPICAL CHARACTERISTICS ( N-Channel) (T J = 5 C unless otherwise noted) VGS, GATE TO SOURCE VOLTAGE (V) I D = 7 A V DD = 5 V V DD = V V DD = V Q g, GATE CHARGE (nc) CAPACITANCE (pf) C iss C oss C rss f = MHz V GS = V. V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain to Source Voltage IAS, AVALANCHE CURRENT (A) T J = 5 o C T J = 5 o C I D, DRAIN CURRENT (A) 45 5 R qjc = 5.6 o C/W V GS = 4.5 V V GS = V... t AV, TIME IN AVALANCHE (ms) T C, CASE TEMPERATURE o ( C) Figure 9. Unclamped Inductive Switching Capability Figure. Maximum Continuous Drain Current vs. Case Temperature ID, DRAIN CURRENT (A) 5 THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE T J = MAX RATED R qjc = 5.6 o C/W ms ms ms ms DC CURVE BENT TO T C = 5 o C MEASURED DATA.. 8 V DS, DRAIN to SOURCE VOLTAGE (V) Figure. Forward Bias Safe Operating Area P(PK), PEAK TRANSIENT POWER (W) 5 SINGLE PULSE R qjc = 5.6 o C/W T C = 5 o C t, PULSE WIDTH (sec) Figure. Single Pulse Maximum Power Dissipation 6

7 TYPICAL CHARACTERISTICS ( N-Channel) (T J = 5 C unless otherwise noted) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. DUTY CYCLEDESCENDING ORDER D = SINGLE PULSE t, RECTANGULAR PULSE DURATION (sec) Figure 3. JunctiontoCase Transient Thermal Response Curve P DM t t NOTES: Z qjc (t) = r(t) x R qjc R qjc = 5.6 o C/W Peak T J = P DM x Z qjc (t) + T C Duty Cycle, D = t / t 7

8 TYPICAL CHARACTERISTICS ( N-Channel) (T J = 5 C unless otherwise noted) ID, DRAIN CURRENT (A) 9 V GS = 3.5 V V GS = 3 V V GS = 4.5 V V GS = V PULSE DURATION = 8 ms V GS =.5 V DUTY CYCLE =.5% MAX 3 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 4. OnRegion Characteristics NORMALIZED DRAIN TO SOURCE ONRESISTANCE V GS =.5 V PULSE DURATION = 8 ms DUTY CYCLE =.5% MAX V GS = 3 V V GS = 3.5 V V GS = 4.5 V V GS = V I D, DRAIN CURRENT (A) Figure 5. Normalized onresistance vs. Drain Current and Gate Voltage NORMALIZED DRAIN TO SOURCE ONRESISTANCE I D = 5 A V GS = V T J, JUNCTION TEMPERATURE ( C) Figure 6. Normalized OnResistance vs. Junction Temperature rds(on), DRAIN TO SOURCE ONRESISTANCE (mw) 5 5 T J = 5 o C PULSE DURATION = 8ms DUTY CYCLE =.5% MAX I D = 5 A T J = 5 o C V GS, GATE TO SOURCE VOLTAGE (V) Figure 7. OnResistance vs. Gate to Source Voltage I D, DRAIN CURRENT (A) 8 4 PULSE DURATION = 8ms DUTY CYCLE =.5% MAX V DS = 5 V T J = 5 o C T J = 5 o C T J = 55 o C IS, REVERSE DRAIN CURRENT (A).. V GS = V T J = 5 o C T J = 55 o C T J = 5 o C V GS, GATE TO SOURCE VOLTAGE (V) Figure 8. Transfer Characteristics V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 9. Source to Drain Diode Forward Voltage vs. Source Current 8

9 TYPICAL CHARACTERISTICS ( N-Channel) (T J = 5 C unless otherwise noted) VGS, GATE TO SOURCE VOLTAGE (V) I D = 5 A V DD = V V DD = V V DD = 5 V 4 5 Q g, GATE CHARGE (nc) Figure. Gate Charge Characteristics CAPACITANCE (pf) f = MHz V GS = V C iss C oss C rss. V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. Capacitance vs. Drain to Source Voltage IAS, AVALANCHE CURRENT (A) T J = 5 o C T J = 5 o C T J = o C... t AV, TIME IN AVALANCHE (ms) I D, DRAIN CURRENT (A) 8 4 V GS = V V GS = 4.5 V R qjc = 4.9 o C/W T C, CASE TEMPERATURE ( o C) Figure. Unclamped Inductive Switching Capability Figure 3. Maximum Continuous Drain Current vs. Case Temperature ID, DRAIN CURRENT (A) THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE T J = MAX RATED ms ms ms ms R qjc = 4.9 o C/W CURVE BENT TO DC T C = 5 o C MEASURED DATA.. V DS, DRAIN to SOURCE VOLTAGE (V) Figure 4. Forward Bias Safe Operating Area P(PK), PEAK TRANSIENT POWER (W) SINGLE PULSE R qjc = 4.9 o C/W T C = 5 o C t, PULSE WIDTH (sec) Figure 5. Single Pulse Maximum Power Dissipation 9

10 TYPICAL CHARACTERISTICS ( N-Channel) (T J = 5 C unless otherwise noted) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. DUTY CYCLEDESCENDING ORDER D = SINGLE PULSE t, RECTANGULAR PULSE DURATION (sec) Figure 6. JunctiontoCase Transient Thermal Response Curve P DM t t NOTES: Z qjc (t) = r(t) x R qjc R qjc = 4.9 o C/W Peak T J = P DM x Z qjc (t) + T C Duty Cycle, D = t / t

11 TYPICAL CHARACTERISTICS (continued) SyncFET Schottky Body Diode Characteristics ON s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 7 shows the reverse recovery characteristic of the. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. CURRENT (A) di/dt = A/ms TIME (ns) Figure 7. SyncFET Body Diode Reverse Recovery Characteristics I DSS, REVERSE LEAKAGE CURRENT (A) T J = 5 o C T J = o C T J = 5 o C V DS, REVERSE VOLTAGE (V) Figure 8. SyncFET Body Diode Reverse Leakage vs. DrainSource Voltage POWERTRENCH is a registered trademark and SyncFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS. C X PKG C L 4 A PQFN8 5X6,.7P CASE 483AR ISSUE O B DATE SEP PKG LC PIN # INDICATOR 5 8 TOP VIEW C X SEE DETAIL A RECOMMENDED LAND PATTERN SIDE VIEW 3.5± C A B.5 C.5 NOTES: UNLESS OTHERWISE SPECIFIED.65±.5.46±.5.9±.5.49± ±.5 3.9±.5 4.±.5 5.±.5 BOTTOM VIEW.57±.5.65±.5.37±.5.53±.5.48±.5 A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION, MO9, DATED /. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED.MM. D) DIMENSIONING AND TOLERANCING PER ASME Y4.5M994.. C.8 C (SCALE: X).5. C SEATING PLANE DOCUMENT NUMBER: STATUS: NEW STANDARD: Semiconductor Components Industries, LLC, October, Rev. DESCRIPTION: 98AON3666G ON SEMICONDUCTOR STANDARD PQFN8 5X6,.7P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped CONTROLLED COPY in red. Case Outline Number: PAGE OF XXX

13 DOCUMENT NUMBER: 98AON3666G PAGE OF ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM FAIRCHILD PQFN8K TO ON SEP 6 SEMICONDUCTOR. REQ. BY I. CAMBALIZA. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Semiconductor Components Industries, LLC, 6 September, 6 Rev. O Case Outline Number: 483AR

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