THE consumer electronics market demands high speed,

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1 IEEE JOURNAL OF SOLID-STATE CIRCUITS 1 A 12 Gb/s 0.9 mw/gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture Takashi Masuda, Ryota Shinoda, Jeremy Chatwin, Member, IEEE, Jacob Wysocki, Member, IEEE, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Member, IEEE, Zhiwei Zhou, Hideyuki Suzuki, and Norio Shoji Abstract A wide band, low power, injection-locked oscillator (ILO)-type clock and data recovery (CDR) with high jitter tolerance is implemented in 28 nm CMOS. A robust phase and frequency detection algorithm independently controls ILO free running frequency and clock phase without an external time reference. A wide capture range of -25/+15% enables referencefree frequency acquisition. Jitter tolerance is 0.56 UI at 300 MHz and 1 UI at 120 MHz, with 2 UI locking time after optional calibration. The CDR operates from 1 to 12 Gbps, consuming 11 mw from 0.9 V supply at 12 Gbps for a power efficiency of 0.9 mw/gbps. A comparison with published results shows a substantial improvement on the trend of wide CDR bandwidth coupled to degraded power efficiency. Index Terms Burst mode, clock and data recovery (CDR), fast locking, FC-ILO, frequency capturing, injection-locked oscillator (ILO), jitter tolerance, reference free. I. INTRODUCTION THE consumer electronics market demands high speed, low power serial links. In this work, we focus on improving the receiver for a short-reach serial electrical link focusing on the data recovery circuit. The receiver s fundamental purpose is to correctly recover data, and the commonly used measurement of the receiver s ability to recover data is jitter tolerance (JTOL), with a higher JTOL being preferable. Improvement in JTOL typically comes at the expense of power consumption, meaning that any claimed improvement in JTOL must be weighed against the power required to achieve the improvement. In order to improve a given receiver, we seek to improve JTOL without substantially increasing power consumption. For clock and data recovery (CDR) circuits, JTOL is measured as a function of jitter frequency. The typical characteristics of a JTOL plot include a flat response above the CDR Manuscript received April 13, 2016; revised June 7, 2016; accepted July 12, This paper was approved by Guest Editor Elad Alon. T. Masuda, R. Shinoda, K. Uchino, Y. Ueno, K. Maruko, Z. Zhou, H. Suzuki, and N. Shoji are with Sony Semiconductor Solutions Corporation, Atsugi-shi, Kanagawa, Japan. J. Chatwin and J. Wysocki are with Mixed Signal Systems Inc., Scotts Valley, CA USA. Y. Miyajima is with Sony LSI Design Inc., Atsugi-shi, Kanagawa, Japan. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /JSSC Fig. 1. Example (a) CDR JTOL and (b) bandwidth. bandwidth and a 20 db/decade slope below the CDR bandwidth (for a first-order CDR). For a second-order CDR, there is also a 40 db/decade slope below a second frequency (ignoring the possibility of jitter peaking). For a given frequency below the CDR bandwidth, the JTOL is improved by increasing the CDR bandwidth, as shown in Fig. 1. If the CDR bandwidth is very wide, bang-bang jitter can reduce the high frequency JTOL. However, it is assumed that the penalty to JTOL from bang-bang jitter is outweighed by the benefit to JTOL from the goal of this work: CDR bandwidth maximization. An additional consideration in the link design is the use of external frequency references. In most cases, a reference is required on the transmitter end. On the receiver end, a reference can be used to reliably set the clock frequency of the CDR. However, the required external components, such as a crystal, increase system cost. Additionally, mismatch between the references on the transmitter and receiver sides can result in a frequency error between the receiver clock and received data, degrading the JTOL. Therefore, it is preferable to design a system that does not rely on a receiver reference, but adjusts clock phase and frequency to the incoming data automatically. In this work, we define reference-free to mean a receiver that functions without a physical external reference, whether that is accomplished through infinite locking range or, as is the case with this work, finite but wide locking range combined with knowledge of the approximate incoming data rate. This paper presents a wide bandwidth, low power, injectionlocked oscillator (ILO) based CDR, called the frequency capturing ILO (FC-ILO), which can operate without an IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 2 IEEE JOURNAL OF SOLID-STATE CIRCUITS Fig. 2. Candidate multi-lane CDR architectures. external reference. Section II examines the most common existing CDR solutions and identifies the key limitations. Section III presents the details of the FC-ILO architecture. Section IV describes some of the key circuit blocks for the FC-ILO. Finally, Section V presents a test chip, fabricated in 28 nm CMOS, that improves on the published trend of increased CDR bandwidth requiring increased power consumption. II. TYPICAL SOLUTIONS AND ISSUES The typical solutions for a multi-lane CDR considered in this work fall into three basic categories: phaselocked loop (PLL) based [1], [2], phase interpolator (PI) based [3] [9], and ILO based [10], [11]. Clock forwarding can also be used [12], [13], but requires an additional transmit channel for the clock, and is not considered here. The selection criteria for this work are power efficiency, bandwidth, locking time, and frequency capture range. Power efficiency and bandwidth give an indication of the power required to achieve a given JTOL. Locking time should be minimized for possible use in a rapid on/off system. Finally, a wide frequency capture range offers the possibility of eliminating the local frequency reference. The multi-lane PLL type CDR, shown in Fig. 2, uses an individual PLL for each lane. This solution suffers from poor power efficiency because each lane requires a high-speed divider, phase-frequency detector (PFD), voltage-controlled oscillator (VCO), and phase detector (PD). It is possible to reduce power consumption by disabling the frequency control loop, meaning the divider and PFD, but the PD and VCO must remain on. The bandwidth of a typical PLL is reasonable and, because it is a type-ii CDR, meaning it corrects both phase and frequency, has wide capture range. However, the locking time can be quite long because phase error is adjusted by imposing a temporary frequency error. The multi-lane PI type CDR, shown in Fig. 2, has a single PLL that is shared by all lanes. The PI solution with a shared PLL improves the power efficiency compared to a PLL based CDR because the PLL power consumption is amortized over all lanes, reducing the per-lane power consumption. This solution can have low bandwidth and slow locking time due to the latency through the loop filter between phase error detection by the PD and phase adjustment by the MUX. The described PI solution, unlike the PLL based CDR, is Type-I, meaning that the PI loop in each lane operates at a fixed frequency (set by the master PLL) and adjusts only to the phase of incoming data by selecting different VCO phases. The multi-lane ILO based CDR is shown in Fig. 2 and, like the PI type CDR, uses a master PLL that sets a control signal used by all lanes. Each lane has a slave ILO whose phase is adjusted locally by injection of the incoming data phase. Like the PI based CDR, the power consumption of the master PLL is amortized over multiple lanes, resulting in good power efficiency. Also, like the PI solution, this is a Type-I CDR and only tracks the phase of the incoming data, not the frequency. However, unlike the PI solution, there is no latency between phase detection and phase correction, as both are performed simultaneously by the injection, resulting in very wide bandwidth and short locking time. The wide bandwidth, good power efficiency, and short locking time make the ILO based CDR attractive. However, the capture range for both the PI and ILO type CDRs is limited due to the fixed local operating frequency. In addition to the narrow capture range, a typical, multi-lane ILO or PI based CDR suffers a penalty to JTOL if there is a frequency error between the receiver and transmitter clocks. Both can tolerate some fixed frequency error by continuous phase adjustment. The phase correction aligns clock edges to data edges, but the data sampling clock is not directly adjusted. For optimum timing margin, the sampling clock edge should

3 MASUDA et al.: 12 Gb/s 0.9 mw/gb/s WIDE-BANDWIDTH INJECTION-TYPE CDR IN 28 nm CMOS WITH REFERENCE-FREE FREQUENCY CAPTURE 3 Fig. 3. Published solutions to the master slave issue be centered between data edges. However, with a frequency error, the sampling clock will be off center. This timing offset reduces either the setup or hold margin of the sampling clocks, reducing the JTOL. This timing reduction becomes worse for a large number of consecutive identical digits (CID), during which the phase error accumulates without correction. While the PI suffers more from transmitter/receiver frequency mismatch than the ILO due to lower bandwidth of the phase correction mechanism, the ILO based solution also relies on good matching between the master and slave VCO. Any mismatch between the master and slave results in a frequency error in the free running frequency (FRF) of ILO, degrading JTOL and, in extreme cases, causing the ILO to lose lock. This problem, here called the master slave issue, becomes more pronounced for very fine process geometries where matching becomes poor. Two different methods have been used to overcome the master slave issue, both of which use a single ILO rather than a master slave. One solution [14], shown in Fig. 3(a), corrects the VCO FRF between data bursts using an FLL. However, this solution does not support continuous data, and is not considered further in this work. A second solution that works for continuous data [15], [17] shown in Fig. 3(b), converts the Type-I ILO-based CDR to a Type-II CDR so that the ILO frequency tracks the frequency of the incoming data. A phase detector compares the ILO phase to the data phase at two points: directly after injection and after some period of freerunning oscillation. The conversion of an ILO based CDR to a Type-II is attractive because of the frequency tracking, which can eliminate the need for a reference. There is a problem with simply placing an ILO in a standard PLL, however, here called the dual lock-point problem. The feedback must resolve two different phase lock points set by two different phase detectors: the phase detector lock point and the injection lock point. The difference between these two lock points, in this work called static phase offset, can be caused by poor tracking over process, voltage, and temperature (PVT), local mismatch, or layout issues. The loop adjusts the FRF until the number of early transitions is balanced by the number of late transitions over some period of time. The presence of static phase offset can cause an error in the converged FRF, reducing JTOL. Loop behavior in two conditions, with and without static phase offset, is illustrated in Fig. 4 by examining the horizontal data eye histogram at the input to the phase detector. If the two lock points are the same, then the loop will correctly interpret phase error as resulting from FRF error and adjust the FRF until the edges are aligned, as shown on the left side of Fig. 4. However, if the two lock points are different, then the injection locking will pull the phase to a point that indicates an FRF error to the phase detector when no FRF error exists, as shown in the upper right portion of Fig. 4. To settle the imbalance, the loop causes an FRF error that pulls transitions after multiple CIDs in the opposite direction of the static phase offset, as shown in the bottom right portion of Fig. 4. The FRF error combined with static phase offset is a stable solution of the loop, but the widened histogram represents deterministic jitter which degrades JTOL. Because the two lock points do not inherently track each other over PVT, some method must be devised to reduce the static phase offset. III. TOPOLOGY (FC-ILO) DESCRIPTION The FC-ILO topology, which has a single ILO and continuous frequency tracking like [15], is shown in Fig. 5 and solves the dual-lock-point problem with three additional circuits: a variable delay that trims the static phase offset between the phase detector and injection lock points, a flipflop that samples the data edge, and a phase and frequency control (PFC) block that controls the ILO FRF and the variable delay. The data center flip-flop, edge flip-flop, and part of the PFC form a bang-bang phase detector (BBPD) that determines if the local clock is early or late with respect to the incoming data. Like [15], the clock frequency tracks the incoming data, eliminating the need for a reference. However, for the FC-ILO, the PFC ensures that the clock frequency and phase are automatically aligned to the incoming data without concern for matching, placing the sampling clock in the optimum location with respect to the incoming data to maximize JTOL, thus solving the dual-lock-point problem from [15]. The PFC adjusts both the variable delay and the FRF of the oscillator but receives only phase error information from the BBPD. In order to determine which output to update, the FC-ILO PFC must discriminate between two possible phase error sources: static phase offset and phase error due to ILO

4 4 IEEE JOURNAL OF SOLID-STATE CIRCUITS Fig. 4. Data crossing histograms triggered by the sampling clock with and without FRF error and static phase offset illustrating the master slave issue. Fig. 5. FC-ILO architecture. FRF error. To make such a determination, consecutive BBPD results are grouped into pairs for processing by the PFC, as shown in Fig. 6(a). If the pair both have the same value, then the phase control is updated. If the pair have different values, then the frequency control is updated, as shown in Fig. 6(b). To understand the detection algorithm, two cases are considered: phase error with no frequency error and frequency error with no static phase offset. In the first case, shown in Fig. 6(c), the clock and data have the same frequency. Phase error at each clock edge, defined as phase error = φclock-φdata, is drawn below the clock and data waveforms. Without frequency error, consecutive data edges will have the same relationship to the respective clock edges, and so, consecutive BBPD outputs will be the same, in this case early. This means that if consecutive BBPD outputs have the same sign, the phase control should be updated. The second case is shown in Fig. 6(d). The first BBPD measurement indicates that the clock is early with respect to the data. Frequency error, however, causes the phase error to drift and the second BBPD output indicates that the clock is late, meaning the BBPD result has changed sign between measurements. Therefore, given that frequency is the derivative of phase, a difference in consecutive BBPD phase comparisons indicates a frequency error and that the frequency control should be updated. The table of PFC inputs and control outputs

5 MASUDA et al.: 12 Gb/s 0.9 mw/gb/s WIDE-BANDWIDTH INJECTION-TYPE CDR IN 28 nm CMOS WITH REFERENCE-FREE FREQUENCY CAPTURE 5 Fig. 6. FC-ILO algorithm. (a) Consecutive BBPD results are examined as pairs by the PFC. (b) Truth table for the PFC algorithm. (c) FC-ILO behavior with static phase offset only. (d) FC-ILO behavior with frequency error only. is shown in Fig. 6(b). The described algorithm never adjusts the frequency and phase controls on the same step and, thus, satisfies the requirement of discriminating phase error due to static phase offset from that due to FRF error. In order to identify frequency error, the detection algorithm requires that frequency error causes a phase drift sufficient to change consecutive BBPD results. However, when used with an ILO, very strong injection can cause this algorithm to fail, requiring an additional modification. The potential failure of this algorithm with strong injection is illustrated in Fig. 7(a). This example considers the case where there is FRF error combined with perfect injection, meaning phase error is completely corrected by injection. In this example, there is a continuous stream of data transitions, and each data edge, rising or falling, adjusts the falling clock edge. Between injections, phase error accumulates but is completely reset at each data edge by injection. The phase error change due to drift is completely balanced by the phase correction from injection, so consecutive BBPD outputs have the same value, as shown in the left of Fig. 7(a), and the variable delay is adjusted. After adjustment, shown on the right of Fig. 7(a), however, the drift is still balanced by injection and all BBPD pairs still have the same value, except they have switched from both early to both late. Therefore, FRF error cannot be detected with very strong injection. The solution is to skip injection on alternate data edges, as shown in Fig. 7(b). On the left side of Fig. 7(b), the first BBPD measurement is assumed to be dominated by static phase offset. The phase error is allowed to accumulate and is not reset by injection prior to the second measurement. Despite the FRF error, consecutive BBPD outputs have the same sign, so static phase offset is detected. The variable delay is then adjusted until phase drift causes consecutive BBPD outputs to be different, which means injection skipping allows FRF error to be correctly detected. The FC-ILO solution has some important similarities to [16], an injection locked clock multiplier that includes a variable delay to trim static phase offset and injection skipping to allow the accumulation of phase error due to frequency error prior to measurement. However, the fundamental difference is that the FC-ILO distinguishes phase error from frequency error, while [16] makes a bang-bang determination of both phase and frequency error at alternating data edges. This means that if the converged frequency is exactly equal to the target, the frequency control will not be updated for the FC-ILO but will for [16], ignoring BBPD metastability.

6 6 IEEE JOURNAL OF SOLID-STATE CIRCUITS Fig. 7. Injection skipping technique. (a) Strong injection masks frequency error from PFC. (b) Injection skipping enables frequency error detection with strong injection. (c) Block diagram of key signals. While the FC-ILO uses injection skipping as part of the frequency measurement, it is not, in fact, strictly necessary. However, depending on the details of the system design, if injection skipping is not used, there is a penalty to the minimum detectable frequency error (MDFE), which should be kept small to reduce FRF error and maximize JTOL. The two cases, with and without injection skipping, are examined in Fig. 8. In this figure, the first measurement, directly after injection, consists entirely of static phase offset. In order to detect an FRF error, the next BBPD measurement must have the opposite result. If injection skipping is not used, there is some correction that occurs before the second measurement is made. The MDFE is the frequency error for which the phase error of the first measurement exactly balances the phase error of the second measurement. With injection skipping, the drift balances the static phase offset; without injection skipping, the sum of drift and correction balance the static phase offset. MDFE as a function of static phase offset, time between injections, and injection strength K isf is calculated below. Injection strength, K isf, is the ratio of output phase error to input phase error for the ILO as shown in the right portion of Fig. 8(a) and is always between 0 and 1. The MDFE expressions for both cases are: MDFE = P stat (with injection skipping) N UI P stat MDFE = N UI ( ) (without injection skipping) 1 K isf where P stat = static phase offset(s) N = clock periods between injection (dimensionless) UI = Unit Interval(s) K isf = Injection Strength (dimensionless) MDFE = Minimum Detectable Frequency Error(%) There are three conclusions we can draw from the MDFE calculations. 1) Increased time between measurements results

7 MASUDA et al.: 12 Gb/s 0.9 mw/gb/s WIDE-BANDWIDTH INJECTION-TYPE CDR IN 28 nm CMOS WITH REFERENCE-FREE FREQUENCY CAPTURE 7 Fig. 8. Minimum detectable frequency error calculation. (a) Terminology definitions. (b) Condition for calculation of MDFE. in a smaller MDFE, with or without injection skipping. Injecting from a low frequency reference with a high division ratio implies a small MDFE. If injecting from data, especially 1010 data, the MDFE can be large because the time between measurements is small. 2) The MDFE is proportional to the static phase offset, which can be as large as the step size of the variable delay. Thus, to minimize MDFE the variable delay step size should be small. 3) If injection skipping is not used, then the MDFE is a strong function of K isf.ask isf goes to 1, the MDFE becomes infinite, which means that frequency error cannot be detected at all, as illustrated in Fig. 7(a). Injection skipping is used in the solution presented in this paper to remove the dependence of MDFE on injection strength, K isf, which can vary substantially in a CMOS process. IV. CIRCUIT IMPLEMENTATION The block diagram for the CDR is shown in Fig. 9. It consists of a half rate ILO, which reduces system power compared to full rate and differs from the architecture presented in Section III. An edge detector detects rising data edges and injects the data phase to the ILO. A variable delay adjusts the relative timing between the edge detector and the data samplers. Two sets of samplers are used, one to recover the data and one to perform phase detection by sampling the data transitions. A 2:10 Demux de-serializes the sampled data 10-bit words, and, along with a second 2:10 Demux, passes the sampled data and transitions to the low speed PFC, which determines the phase error source using the FC-ILO algorithm. The PFC includes a digital loop filter that controls the phase and frequency update rate. The ILO frequency is set using a current DAC and the static phase offset is adjusted by the variable delay. Fig. 10 shows the building blocks for the ILO and variable delay, which use dual coarse/fine tuning. The basic delay component is a current starved inverter. The fine tuning control is the inverter current, while the coarse tuning control is the

8 8 IEEE JOURNAL OF SOLID-STATE CIRCUITS Fig. 9. CDR architecture. Fig. 10. Delay element with coarse and fine tuning. number of parallel elements in each delay block. The benefit of the coarse tuning method is that the normalized tuning gain, defined as the VCO tuning gain divided by the VCO frequency, remains roughly constant over a wide range of operating frequencies, as shown in Fig. 10. Fig. 11 shows the structure of the variable delay. Two data phases, SigA and SigB, are separated by the delay through the basic delay element. Two PIs are used to vary the phases of both data sent to the samplers and data sent to the edge detector. The two PIs use complementary codes to double the total tuning range with respect to the range of a single PI. At one extreme of the PI code space, the samplers receive phase SigA and the edge detector receives phase SigB. At the other extreme, the samplers receive phase SigB and the edge detector receives phase SigA. The coarse/fine tuning allows the delay tuning range to track the oscillator frequency, meaning wider tuning range for lower data rates. Fig. 12 shows the half rate ILO topology. The topology uses four pseudo-differential current-starved CMOS inverter stages, as shown in Fig. 10, with cross-coupling to align the complementary phases and cause oscillation, similar to [18] and [19]. The complementary phases are shorted together with Fig. 11. Fig. 12. Variable delay circuit. Half-rate ILO topology. a switch to inject the data phase to the clock phase. The dual coarse/fine tuning mechanism supports data rates between 1 and 12 Gbps.

9 MASUDA et al.: 12 Gb/s 0.9 mw/gb/s WIDE-BANDWIDTH INJECTION-TYPE CDR IN 28 nm CMOS WITH REFERENCE-FREE FREQUENCY CAPTURE 9 Fig. 13. Test chip block diagram. V. MEASUREMENT RESULTS The test chip, with block diagram shown in Fig. 13, consists of four lanes. Each lane has a receiver, control logic, and a test block. In addition to the CDR described previously, each receiver has an analog front-end (AFE) that compensates a channel loss of 5 db at 6 GHz, supporting 12 Gbps operation. The control logic contains an internal error checker and the digital block, which includes the PFC, which adjusts static phase offset and ILO frequency. The test block serializes the parallel output data so that the bit-error rate (BER) can be measured externally. The test chip supports two different modes of operation: reference-free and initial calibration. In the initial calibration mode, which does require a local reference, a binary search is performed at startup that compares the free running frequency of the ILO to the reference. This algorithm is appropriate for this design because the ILO frequency is set by a current DAC that is controlled directly by the digital block, as opposed to the frequency of a VCO in a standard charge-pump PLL which is set by a voltage on a capacitor that would be controlled indirectly through the charge pump. The reason to use the initial calibration mode is to allow fast locking. Once the initial frequency is acquired, the reference input is disabled and the ILO frequency tracks the incoming data. In referencefree mode, a reasonable initial guess of the DAC code for a given data rate is required. The initial guess must set the ILO to a frequency within the capture range of the loop. The test chip micrograph, fabricated in 28 nm CMOS, is shown in Fig. 14. The performance of the chip is summarized in Table I. It is tested in all cases with a PRBS9, 8B/10B data pattern. Each lane consumes 22.9 mw and the CDR consumes 11 mw, both from a 0.9 V supply. The CDR normalized power figure-of-merit (FOM) is 0.9 mw/gbps. The normalized Fig. 14. Test chip micrograph. receiver FOM is 1.9 mw/gbps. There is a 20% reduction in power for a 4-lane FC-ILO architecture compared to a 4-lane ILO CDR architecture with a master PLL. The capture range in reference-free mode is shown in Fig. 15. The capture range is tested at 10 Gbps with and without the loop by monitoring the clock frequency and the error detector. To test without the loop, data is transmitted while the VCO frequency is held using a fixed DAC code.

10 10 IEEE JOURNAL OF SOLID-STATE CIRCUITS TABLE I TEST CHIP PERFORMANCE SUMMARY Fig. 16. Fast locking measurement. Fig. 17. Jitter tolerance measurement. Fig. 15. Frequency capture range measurement results. Without the loop, error-free data is received when the halfrate clock frequency is within 2.6/+3.2% of the nominal clock frequency of 5 GHz. With the loop enabled, the clock frequency can converge to 5 GHz if the initial FRF error is within 26/+15% of5 GHz. Afterconvergence, error-freedata is received. This confirms that the loop can work correctly without an external reference. The fast locking benefit of the initial calibration mode is shown in Fig. 16. The initial clock frequency is acquired by comparing the ILO FRF against the local reference with input data disabled. After data is enabled, the CDR correctly recovers all bits after the first UI. This test was repeated several times with the same data sequence. At most, the CDR required three edges to lock. The most common locking requirement was a single edge, meaning 2 UI, thus demonstrating fast locking ability. The JTOL evaluation is shown in Fig. 17. JTOL was tested at 12 GHz. This plot shows the results of two tests and also includes extrapolated results. In the first test, the N4903B was used as a jitter generator and error checker. The result of this test is shown using the dashed line with diamonds. The JTOL of the circuit exceeded the JTOL of the error checker at all frequencies except 300 MHz. To measure further, the internal error checker was used with the external jitter generator, shown by the solid line with circles. The two tests give the same JTOL at 300 MHz. Between 60 MHz and 300 MHz, the equipment was capable of generating jitter exceeding the CDR JTOL, allowing direct measurement of the CDR performance. Below 60 MHz, however, error-free data was detected at the limit of the jitter generation capability of the equipment, so JTOL below 60 MHz was inferred. A dashed line shows the estimated JTOL for frequencies below 60 MHz, following a 20 db/decade trend. Due to the equipment limitation and low bandwidth of the frequency control loop, the 40 db/decade portion of the JTOL curve was not measured and is not included in the extrapolation. The JTOL at 300 MHz is 0.56 UIpp, including random jitter (RJ) of 0.18 UIpp at BER1e-9 and excluding inter-symbol interference (ISI) jitter generated by the channel. The flat portion of the JTOL and, hence, exact CDR bandwidth, was not directly identified because the testing was limited to 300 MHz. However, simulation indicates that 0.56 UIpp JTOL measured at 300 MHz is close to the high frequency value. The performance of this topology is compared with published results in Fig. 18, examining the trade-off between CDR bandwidth and power consumption. The power consumption is reported as RX normalized power FOM in mw/gbps on the y-axis. CDR bandwidth is not directly measured in this work and usually is not reported in the literature. Instead, an indicator of bandwidth that can be readily extracted from JTOL plots, the jitter frequency at which JTOL = 1 UIpp, is shown on the x-axis. The published results are categorized by CDR

11 MASUDA et al.: 12 Gb/s 0.9 mw/gb/s WIDE-BANDWIDTH INJECTION-TYPE CDR IN 28 nm CMOS WITH REFERENCE-FREE FREQUENCY CAPTURE Fig. 18. Comparison of CDR bandwidth and power efficiency with published results. Black results are in the range Gbps. White results are outside the range Gbps. type, PI, PLL or ILO, and relative bandwidth, inside or outside the range Gbps. The PI types have the best normalized power FOM but the lowest bandwidth, while the ILO types have the largest bandwidth. The PLL types are in the center of the trend. This work greatly improves on the published trend with the widest bandwidth and a normalized power FOM better than all but one PI solution. This comparison shows that the FC-ILO design has achieved the combined benefits of the PLL and ILO type CDRs: wide capture range, wide bandwidth, and short locking time. 11 [13] K. Hu, T. Jiang, J. Wang, F. O Mahony, and P. Y. Chiang, A 0.6 mw/gb/s, Gb/s serial link receiver using local injectionlocked ring oscillators in 90 nm CMOS, IEEE J. Solid-State Circuits, vol. 45, no. 4, pp , Apr [14] J. Terada, K. Nishimura, S. Kimura, H. Katsurai, N. Yoshimoto, and Y. Ohtomo, A Gb/s burst-mode CDR circuit using a δσ DAC, in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp [15] C.-F. Liang, S.-C. Hwu, Y.-H. Tu, Y.-L. Yang, and H.-S. Li, A reference-free, digital background calibration technique for gatedoscillator-based CDR/PLL, in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp [16] A. Elkholy, M. Talegaonkar, T. Anand, and P. K. Hanumolu, A 6.75-to8.25 GHz 2.25 mw 190 fsrms integrated-jitter PVT-insensitive injectionlocked clock multiplier using all-digital continuous frequency-tracking loop in 65 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp [17] M. Raj, S. Saeedi, and A. Emami, A 4-to-11 GHz injection-locked quarter-rate clocking for an adaptive 153 fj/b optical receiver in 28 nm FDSOI CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp [18] C.-F. Liang and K.-J. Hsiao, An injection-locked ring PLL with selfaligned injection window, in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp [19] W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, A mm2 970 μw dual-loop injection-locked PLL with 243 db FOM using synthesizable all-digital PVT calibration circuits, in IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp Takashi Masuda received the B.S. and M.S. degrees in electrical and electronics engineering from Sophia University, Tokyo, Japan, in 2001 and 2003, respectively. He joined Sony Corporation, Tokyo, in He has been engaged in research and development of CMOS analog LSIs. His research interests include high-speed interface and millimeter-wave. R EFERENCES [1] J. Lee and K.-C. Wu, A 20 Gb/s full-rate linear CDR circuit with automatic frequency acquisition, in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp [2] T. Masuda et al., A 250 mw full-rate 10 Gb/s transceiver core in 90 nm CMOS using a tri-state binary PD with 100 ps gated digital output, in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp [3] K. Fukuda et al., A 12.3 mw 12.5 Gb/s complete transceiver in 65 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp [4] H. Pan et al., A digital wideband CDR with 15.6 kppm frequency tracking at 8 Gb/s in 40 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2011, pp [5] R. Dokania et al., A 5.9 pj/b 10 Gb/s serial link with unequalized MM-CDR in 14 nm tri-gate CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp [6] H. Kimura et al., 28 Gb/s 560 mw multi-standard SerDes with singlestage analog front-end and 14-tap decision-feedback equalizer in 28 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp [7] U. Singh et al., A 780 mw 4 28 Gb/s transceiver for 100 GbE gearbox PHY in 40 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2014, pp [8] B. Raghavan et al., A sub-2 W 39.8-to-44.6 Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2013, pp [9] F. Spagna et al., A 78 mw 11.8 Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp [10] J. Lee and M. Liu, A 20 Gb/s burst-mode CDR circuit using injectionlocking technique, in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp [11] K. Maruko et al., A to Gb/s transceiver with 2.4 mw/(gb/s) burst-mode CDR using dual-edge injection-locked oscillator, in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp [12] M. Hossain and A. Chan Carusone, A 6.8 mw 7.4 Gb/s clockforwarded receiver with up to 300 MHz jitter tracking in 65 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp Ryota Shinoda received the B.E. and M.E. degrees in electronics and electrical engineering from Keio University, Yokohama, Japan, in 2010 and 2012, respectively. He joined Sony Corporation, Tokyo, Japan, in His current research interests are in analog CMOS integrated circuits for interface circuits. Jeremy Chatwin (M 98) received the B.Eng. degree in electronic engineering from the University of Manchester Institute of Science and Technology (UMIST), Manchester, U.K., in Between 1990 and 1995, he was with GEC Plessey Semiconductors, Oldham, U.K., working as a design engineer on high-speed analog design, principally TIA, and later R/W thin film and MR preamps for HDD applications. This role continued during 1996 at the Scotts Valley, CA, USA, location of the same company. In 1997 he moved to Samsung Semiconductors Inc, San Jose, CA, USA, where he was responsible for the read signal path of a 6-channel MR preamp for HDD. In 1998 he joined Mixed Signal Systems, Scotts Valley, CA, as a Design Engineer and worked on read channel development for tape, HDD and optical media. Later work has involved development of TIA, high-speed synthesizers, clock and data recovery units and elements of UWB radios. He has co-authored three ISSCC papers and is inventor or co-inventor on 10 U.S. patents. He currently is president of Mixed Signal Systems.

12 12 IEEE JOURNAL OF SOLID-STATE CIRCUITS Jacob Wysocki (M 11) received the B.S. degree in electrical engineering with highest honors and the Ph.D. in electrical engineering from the University of California, Santa Cruz, CA, USA, in 2002 and 2013, respectively. He was a researcher in the Lightwave Communications Lab at UC Santa Cruz starting in 2006, where he investigated mode-mixing and optical coupling in polymer optical fiber and optimization of transimpedance amplifiers in SiGe BiCMOS for multigigabit POF-based communication systems. During the summer of 2009, he was a technical legal consultant for Hopkins-Carley, San Jose, CA, USA. In 2011 he joined Mixed-Signal Systems, Inc., Scotts Valley, CA, USA, as an IC design engineer. His research interests include multi-gigabit communication ICs and vacuum-tube-based audio electronics. Koki Uchino received the B.E. and M.E. degrees in electrical and electronics engineering from Kagoshima University, Kagoshima, Japan, in 2007 and 2009, respectively. He joined Sony Corporation, Tokyo, Japan, in 2009 and was initially engaged in developing RF CMOS circuit design for wireless proximity interface. His current research interests are in analog CMOS circuit design for high-speed wireline interface. Yoshifumi Miyajima received the B.E. and M.E. degrees in materials science and engineering from Nagasaki University, Nagasaki, Japan, in 1991 and 1993, respectively. He began his career with Sony Semiconductor Kyusyu Corporation in 1993, and worked on the development of cache memory. Since 2004, he has been with Sony LSI Design Corporation, where he is engaged in the design and development of analog CMOS integrated circuits for optical and electrical high-speed transmission. Yosuke Ueno received the B.S. and M.S. degrees in applied physics from the University of Tokyo, Tokyo, Japan, in 2001 and 2003, respectively. In 2005, he joined Sony Corporation, Japan, and has been engaged in research and development of mixed-signal circuits for various applications including image sensors. Kenichi Maruko (M 04) received the B.S. and M.S. degrees in electrical engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 1997 and 1999, respectively. He joined Texas Instruments Japan in 1999, where he was involved in the development of mixed-signal LSI. Since 2007, he has been with Sony, where he has been engaged in high-speed serial links. Zhiwei Zhou received the B.E. degree in electric engineering from Nankai University, Tianjin, China, in 2005, and the M.S. degree in electric engineering from the University of Tokyo, Tokyo, Japan, in He joined Sony Corporation, Tokyo, Japan, in He has been involved in the development of high-speed serial interfaces. His current research interests are injection-locking CDR and low-power low-jitter PLL/SerDes design. Hideyuki Suzuki received the B.S. and M.S. degrees in electronic engineering, both from the University of Shizuoaka, Japan, in 1990 and 1992, respectively. In 1992, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, where he has been engaged in the design and evaluation of high-speed integrated circuits for optical fiber transmission systems. He is currently working at Sony Semiconductor Solutions, Kanagawa, Japan, as a general manager. His research interests include PLLs, millimeter-wave CMOS design, and high-speed interfaces. Norio Shoji received the B.E. degree in electronics engineering from Waseda University, Tokyo, Japan, in He joined Sony Corporation, Tokyo, Japan, in 1982, where he worked on analog circuit development for 34 years. He is a Distinguished Engineer for Sony Corporation.

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