Division of CIRCUITS AND SYSTEMS

Transcription

1 Division of

2 29 INTRODUCTION T he continuous growth in integrated circuit (IC) and electronic design activities in Singapore has resulted in excellent student enrolments in the Division s final year electronics option as well as the IC Design Specialist Manpower Programme (SMP) and NTU-TUM MSc Course in IC Design. Besides playing a leading role in IC design manpower training for the nation s expanding electronics and IC design industries, the division has also performed extremely well in research. On 12 th January, the division signed an agreement with Advanced RFIC (arfic) Pte Ltd to set up the $9 million new research laboratory, Advanced RFIC@NTU. The collaboration aims to advance research and development in RFIC technology. The new research laboratory contains state-of-the-art equipment, including a world-class 300 mm probe system that makes modelling, measurement and characterization of nano-rf devices as well as integrated circuits and systems possible. Thirty postgraduate scholarships have also been set aside to expand the research activities in RFIC design. sharing their latest research with NTU researchers. NTU aims to build the ISNE into an international centre of excellence in five years and our colleagues have, to date, participated actively in 6 projects to be funded by the ISNE. On 7 th September, another new research laboratory led by the division, the $10 million Electromagnetic Effects Research Laboratory (EMERL) set up jointly with DSO National Laboratories, was officially opened by the Defence Minister, Mr Teo Chee Hean. The Semi- Anechoic Chamber and the Reverberation Chamber in the EMERL allow advanced Electromagnetic Compatibility (EMC) measurement for any electronic system up to 40 GHz. With the worldwide trend of imposing EMC regulations on practically all electronic devices, the setting up of the EMERL is timely for the division to play a key role to spearhead advanced EMC research that seeks to ensure that electronic devices and systems are well designed with low electromagnetic emission, as well as high electromagnetic immunity. MOU signing for the setting up of Advanced RFIC@NTU Defence Minister, Mr Teo Chee Hean (4 th from the left) unveiling the commemorative plaque at the EMERL opening ceremony On 4 th September, NTU established the Institute for Sustainable Nanoelectronics (ISNE), a new initiative led by the division. The ISNE aims at designing and developing the next generation of embedded IC chips which consume significantly less energy with low production costs. The ISNE has received a seed funding of $4 million to kick off its research activities. The ISNE strategy will be led by Professor Krishna Palem of Rice University, who is also the Canon Visiting Professor at NTU. To officially launch the ISNE, an inaugural workshop was held on 29th October with many internationally renowned nano-electronics researchers Our colleagues have also done very well in securing research funding from both public and private sectors, such as Panasonic Semiconductor, Chartered Semiconductor, SINO-American Silicon Products, ST Microelectronics, A*STAR, DSTA and DSO National Laboratoreis. The total funding secured is close to $4 million, covering research areas in VLSI, RFIC, Reliability and EMC, which are in line with our division s long-term research capability in System-on-Chip (SoC). A CRP research proposal from our colleagues has also been shortlisted by NRF despite keen competition at the international-level.

3 30 Highlights of Research Activities With all these newly added research facilities, research initiatives and a strong research team, the division is well positioned to build up System-on-Chip (SoC) capability for the realization of many SoC systems. Amongst these are Software Defined Radio (SDR) systems that can be easily configured to operate at many existing and future worldwide air-interface standards, and ultimately to become the universal mobile communication system. 400μm GND OUT GND Vcont GND VDD GND 620μm In this report, the division would like to highlight some of its research achievements. One main component in microwave receivers is the Voltage-Controlled Oscillator (VCO). The unity frequency ft, the frequency where the transistor current gain becomes unity for 0.18μm, is about 40 GHz for optimum biasing. In a circuit with large biasing swing like a VCO, ft can be as low as 15 GHz. This proves to be a major problem for VCO design as the VCO needs to work at 24 GHz. In addition, other parameters such as tuning range and phase noise could be greatly affected by the low unity frequency. The division has developed a VCO with an oscillation frequency of 23 GHz using a CMOS transistor with ft of 15.8 GHz. Based on the 0.18μm CMOS process, our colleagues demonstrated that using novel push-pull buffer, a VCO can operate up to almost double the unity frequency. Microphotograph of the 23-GHz VCO High-speed Digital Signal Processing (DSP) is a dedicated module that has to cope with the complexity and diverse processing requirements and specifications of different SoC systems. Traditional techniques for multiplierless filtering involve optimizing the digital filter coefficients in signed power-of-two (SPT) coefficient space, and thus the coefficient multiplications are replaced by additions and shifts. However, the design of digital filters with discrete coefficient values may not always be possible in some applications such as in adaptive filtering. The division has developed a new technique where signals are converted into a sum of a limited number of SPT terms. Since hardware circuitry for the real time conversion is available, the filter is also multiplierless even though the coefficient values are not SPT. The new technique can handle very complex signal processing needs with low power consumption. IC Reliability is another important aspect of IC design, especially with the continuous reduction in line width and the increase in the number of metallization layers. Our colleagues have developed a physical model of the electromigration that allows accurate prediction the failure sites for interconnects with different line widths and structures under various stress conditions. With the model, different categories of failure mechanisms can be predicted for failure analysis.

4 31 a b M2 dummy line Void e-flow Max 4.54x x x x x x10 29 (a) FIB-SEM image of failed sample, (b) total AFD distribution at M1 test condition. Comparison of quantization error of the new technique (solid lines) and the measured results (histogram plots) With high-speed electronic systems operating at sub-nano second edge rates, board-level integration becomes a very challenging task. The interconnects begin to behave as transmission lines. In addition, parasitic effects due to inter-layer vias, interconnect bends and gaps in ground plane, start to show their impacts on circuit performance at these edge rates. Hence, Signal Integrity (SI) and EMC are becoming major issues for high-speed board design. The SI and EMC issues, if not properly resolved, will lead to unstable and intermittent operation problems. The research group in EMERL has done extensive research work and developed a systematic design methodology in SI/EMC compliant high-speed designs. Near-field electromagnetic scanning results indicating hot-spot areas that are causing SI/EMC problems

5 32 CENTRE FOR INTEGRATED T he Centre for Integrated Circuits & Systems (CICS) has 18 active full-time academic staff, 4 Research Fellows, 10 Research Associates, 3 Project Officers and 14 Technical Staff. Its research activities are focussed in three areas, namely RF Integrated Circuits and Systems, Analog/ Mixed-Signal IC, and VLSI Design and Embedded Systems, with academic staff strengths of 5, 7, and 5 respectively. Most projects concern the design and analysis of devices, circuits and sub-systems of the final SoC (System on Chip) products, with or without the embedded software. The RF Integrated Circuits and Systems group has 5 academic staff, 6 research staff and 23 research students. Its research focuses on RF IC design for wireless & mobile communications, RF modelling and characterization for deep sub-micrometer semiconductor devices, on-wafer interconnects and coupling, RFIC testing, ultra high speed clock-data-recovery, RF System-on-Chip, RF System-in- Package, Integrated Circuit Package Antenna, and EMC/ EMI in RF integrated circuits and systems. At present there are 6 on-going research projects with an aggregate funding of some $2 million, the major part of the funding comes from external sources. The major research strengths of the group are Ultra Low Power RFIC designs for wireless, mobile and biochips applications. The research activities of the Analog/Mixed-Signal IC group are focussed on data converters, low-voltage low-power mixed signal circuits, and high-performance asynchronous digital signal processors. This group currently has a total research funding of some $2 million. In VLSI Design and Embedded Systems, the research activities cover a diversity of topics pertaining to the development of novel algorithms, efficient hardware architectures and design methodologies towards VLSI and embedded application solutions. The group has 2 major projects with a funding of $700,000. Some of the major projects and significant achievements are described below. 20-GHz High-Frequency CMOS T/R Switch IC Design OBJECTIVE A novel IC design method and topology for CMOS Transmit/Receive switch design towards wideband and 20-GHz high frequency applications have been invented. Its novel design supports a wide range of wireless applications that require broadband and high frequency. The layout technique for switch transistor overcomes drawbacks due to drain-source interconnections. The series-only topology saves chip area and reduces design complexity. The double-well body-floating technique overcomes drawbacks of excessive chip area in LCtuned techniques. The switched body-floating technique overcomes the negative effects of body-floating techniques. The differential topology improves power handling capability and offers better signal quality. A 20-GHZ CMOS T/R Switch

6 33 Intelligent ISFET Sensory System for Water Quality Monitoring OBJECTIVE This project is to research a new intelligent ISFET sensory system dedicated to precision ph sensing function, along with long-term monitoring capability for water quality monitoring in environmental applications whilst not jeopardizing the accuracy by any temperature and time fluctuations. variant compensation algorithm together with hardware and software co-design, the sensing performance of the readout IC is significantly enhanced even using standard ISFET sensing device. Using semiconductor theory and innovative circuit design technique, a novel readout IC has demonstrated that temperature compensation can be accomplished without temperature sensor. Further incorporating generic time- An Intelligent ISFET Water Quality Sensory System Low Power Low Voltage 8 Bit 200 MS/s Pipelined ADC OBJECTIVE The ADC was designed for applications in broadband wireless communications and optimized for IEEE standards. The achievement of high speed and ultra low power operation ( mw) sets a new benchmark in ADC design. The design uses a novel mixed-mode sampling and holding technique which reduces signal swings in the pipelined ADC while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the op amp gain, slew rate, bandwidth and capacitor matching requirements in pipelined ADCs. Thus, single stage op amps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low power consumption. The linearity of the ADC is also improved due to the reduced signal swing. The performance of the ADC is summarized in Table 1. Table 1. Performance Summary Technology 0.18 μm 2P6M CMOS Resolution 8 bits Sampling Rate 200 MS/s Supply Voltage 1.8V Input Range 0.8V pp DNL/INL 0.30 LSB / 0.34 LSB SNDR (ƒ in = 40MHz) 45.2 db SNDR (ƒ in = 99MHz) 44.2 db SFDR (ƒ in = 40MHz) 60.4 db SFDR (ƒ in = 99MHz) 53.4 db Active Area 0.8 mm x 0.4 mm Power Consumption 22 mw A Low Power Low Voltage 8 bit 200 MS/s Pipelined ADC

7 34 Staff Members 1 st Row (From left to right) Head of Division Yeo Kiat Seng Deputy Head of Division See Kye Yak Assistant Head of Division Goh Wang Ling Professor Do Manh Anh 2 nd Row (From left to right) s Chan Pak Kwong Chang Chip Hong Chang, Joseph Sylvester Associate Dean, College of Engineering (1 April March 2007) Gwee Bah Hwee 3 rd Row (From left to right) s Ho Duan Juat Jong Ching Chuen Koh Liang Mong 4 th Row (From left to right) s Lam Ying Hung, Yvonne Lau Kim Teen Program Director, MSc (Consumer Electronics) MSc (IC Design) Lim Meng Hiot

8 35 Staff Members 1 st Row (From right to left) s Ng Lian Soon Ong Keng Sian, Vincent Siek Liter Tan Cher Ming 2 nd Row (From right to left) Zhang Yue Ping Assistant Professors Boon Chirn Chye Tiew Kei Tee Tan Meng Tong 3 rd Row (From right to left) Assistant Professor Yu Yajun Teaching Fellows Alper Cabuk Kong Zhi Hui 4 th Row (From right to left) ial Fellows Chua Hong Chuck@ Chua Hong Chuek Ooi Tian Hock@ Wei Ten Fook Wong Mong Chung, Eddie Tang Hung Kei

9 36 Research Interest 1 Boon Chirn Chye Assistant Professor RFIC Devices, Circuits and Systems Design, PLL Frequency Synthesizer Design, Biomedical Consumer Electronic. 2 Chan Pak Kwong Biomedical Circuits and Systems, Sensor Interfaces, Mixed-Signal Circuits and Systems. 3 Chang Chip Hong Computer Arithmetic, VLSI Design, Design automation, Digital Signal Processing. 4 Chang, Joseph Sylvester Acoustics, Audiology, Electronics, IC Design, Analogue and Digital Signal Processing, Biomedical Engineering, Pyschophysics. 5 Chua Hong Chuck ial Fellow High Density Multilayer PCB Design, System Integration (Noise & signal integrity), Embedded Systems for Security. 6 Do Manh Anh Professor Biomedical Electronics, Digital Communications, R.F. Circuits and Systems, Acoustics. 7 Goh Wang Ling Device Processing, Device Characterization, and IC Design. 8 Gwee Bah Hwee Asynchronous & Digital Class-D Amplifier IC Designs, Acoustic Noise Reduction. 9 Ho Duan Juat Video Coding, System Level Digital Design, ASIC Design. 10 Jong Ching Chuen High-Level Synthesis, Parallel Computation and Reconfigurable Systems. 11 Koh Liang Mong Machine Vision, Energy Saving Electronic Converters. 12 Lam Ying Hung, Yvonne Mixed-signal IC Design, Analogue Design Automation. 13 Lau Kim Teen Low power IC Design, Self-timed CMOS Circuits, Subthreshold CMOS Circuits. 14 Lim Meng Hiot Computational Intelligence, Embedded Systems, AI in Finance, Fuzzy/neural Hardware, Combinatorial Optimization. 15 Ng Lian Soon Analogue CMOS circuits, DAC/ADC, Micropower Circuits, Analogue Bipolar Circuits. 16 Ong Keng Sian, Vincent Materials and Device Characterization, Analysis and Modelling, Electron Beam Techniques, EBIC Metrology. 17 Ooi Tian Hock ial Fellow RF Circuits and Systems, ASIC, DSP in Consumer Electronics Applications, Factory Automation, Quality and Reliabilty, EMC/EMI/EMS. 18 See Kye Yak Computational Electromagnetics, Electromagnetic Compatibility and Signal Integrity. 19 Siek Hsueh Liter Low-power Low-voltage Analog/Mixed Signal CMOS/Bipolar IC Design. 20 Tan Cher Ming Nanoelectronics, ULSI Interconnect Reliability, Wafer Bonding, Reliability and Maintenance Engineering. 21 Tan Meng Tong Assistant Professor VLSI Design, Class D Amplifiers, Analog and Digital Signal Processing, Biomedical Engineering. 22 Tang Hung Kei ial Fellow Technopreneurship, Management of Innovation and Technology.

10 Research Interest Tiew Kei Tee Assistant Professor Analog and Mixed-signal IC Design, Delta-sigma Modulators, Bio-instrumentation. 24 Wong Moon Chung, Eddie ial Fellow Biomedical Instrumentation, Image Processing, Robotics And Automation, Digital Test Generation and DFT Yeo Kiat Seng Yu Yajun Zhang Yue Ping Assistant Professor Device Modeling, RFIC Design, Low-voltage Low-power IC Design. VLSI Digital Signal Processing, VLSI Circuits and Systems Design. Wireless Chip Area Network, Single-chip Radio, and Radio Bioelectronics. PhD & MEng Degrees Awarded in 2007 PhD - S/NO. PROJECT TITLE STUDENT SUPERVISOR/CO-SUPERVISOR 1 Design and implementation of a reconfigurable fuzzy inference processor Cao Qi Lim Meng Hiot 2 Flicker noise fluctuations in deep submicron MOSFETs Chew Kok Wai, Johnny Yeo Kiat Seng 3 Design and implementation of a low energy fast fourier transform/inverse fast fourier transform (FFT/IFFT) processor based on asynchoronous-logic Chong Kwen Siong Gwee Bah Hwee Chang, Joseph Sylvester 4 Performance analysis and integrated circuit design for ultra-wideband transceiver Li Qiang Zhang Yue Ping 5 Novel methodologies for miniaturized filter designs and realization Ma Kaixue Yeo Kiat Seng Miao Jianmin 6 Dual band low-noise amplifier designs for bluetooth and hiperlan applications Mou Shouxian Yeo Kiat Seng 7 Characterization and modeling of on-wafer interconnects for RFICs Shi Xiaomeng Yeo Kiat Seng Li Erping 8 Study of chip scale wireless interconnect systems and their antennas Sun Mei Zhang Yue Ping Guo Lihui Algorithms for synthesis and optimization of multiplierless FIR filters New self-organizing algorithms for topological mapsi Meta-heuristic algorithm development for combinatorial optimization within an integrated problem solving environment Xu Fei Xu Pengfei Xu Yiliang Jong Ching Chuen Chang Chip Hong Lim Meng Hiot 12 Digital image enhancement algorithm for 2-D ultrasound imaging system Zhang Fan Koh Liang Mong 13 Speckle removal in medical ultrasound images by compounding and filtering Zhang Lichen Wong Moon Chung, Eddie MEng - S/NO. PROJECT TITLE STUDENT SUPERVISOR/CO-SUPERVISOR 1 Fast finite field multipliers for public key cryptosystems Satzoda Ravi Kumar Chang Chip Hong 2 An integrated platform for design & verification of digital FIR filters Sharma Udit Jong Ching Chuen

11 38 Selected Publications in 2007 List of Selected Publications Aaron V. Do, C. C. Boon, M. A. Do, K. S. Yeo and A. Cabuk, "A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band", accepted, IEEE Trans. on Microwave Theory and Techniques, K. M. Lim, C. Y. Ng, K. S. Yeo, M. A. Do and C. C. Boon, "A 2.4GHz Ultra Low Power Subthreshold CMOS Low-Noise Amplifier", Microwave and Optical Technology Letters, vol. 49, pp , February P. K. Chan and D. Y. Chen, "A CMOS ISFET Interface Circuit with Dynamic Current Temperature Compensation Technique", Special Issue on Smart Sensors, IEEE Trans. on Circuits and Systems, Part I, vol. 54, no. 1, pp , January J. Peng and P. K. Chan, "Analysis of Nonideal Effects on a Tomography-Based Switched-Capacitor Transducer", IEEE Sensors Journal, vol. 7, no. 3, pp , March J. K. Yin and P. K. Chan, "A Low-Jitter Polyphase Filter Based Frequency Multiplier with Phase Error Calibration", accepted, IEEE Trans. on Circuits and Systems, Part II, F. Xu, C. H. Chang and C. C. Jong, "Design of Low-Complexity FIR Filters Based on Signed-Powers-of-two Coefficients with Reusable Common Subexpressions", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp , October Y. Shao and C. H. Chang, "A Generalized Time-Frequency Subtraction Method for Robust Speech Enhancement Based on Wavelet Filter Bank Modeling of Human Auditory System", IEEE Trans. on Systems, Man and Cybernetics, Part B: Cybernetics, vol. 37, no. 4, pp , August B. Cao, C. H. Chang and T. Srikanthan, "A Residue-to-Binary Converter for a New 5-moduli set", IEEE Trans. on Circuits and Systems, Part I, vol. 54, no. 5, pp , May Z. H. Lu, K. S. Yeo, J. G. Ma, M. A. Do, W. M. Lim, and X. Y. Chen, "Broadband Design Techniques for Trans-impedance Amplifiers", IEEE Trans. on Circuits and Systems I, vol. 54, no. 3, pp , March X. P. Yu, M. A. Do, J. G. Ma, W. M. Lim, K. S. Yeo and X.L. Yan, "Sub-1V Low Power Wide Range Injection-Locked Frequency Divider", IEEE Microwave and Wireless Components Letters, vol. 17, no. 7, pp , July D. D. Chen, K. S. Yeo, M. A. Do and C. C. Boon,"A Fully Integrated CMOS Limiting Amplifier with Novel Offset Compensation Network", IET Electronics Letters, vol. 43, no. 20, pp , September H. Q. Liu, W. L. Goh, L. Siek, Y. P. Zhang and W.M. Lim, "A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator with Coarse and Fine Frequency Tuning", accepted, IEEE Trans. on Very Large Scale Integration Systems, K. S. Chong, B. H. Gwee and J. S. Chang, "Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors", IEEE Journal of Solid State Circuits, vol. 42, no. 9, pp , September C. F. Chong, B. H. Gwee and J. S. Chang, "Asynchronous Control Network Optimization Using Fast Minimum Cycle Time Analysis", accepted, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, K. S. Chong, B. H. Gwee, and J. S. Chang, "Design of Several Asynchronous-Logic Macrocells for a Low-Voltage Micropower Cell Library", IET Proc. Circuits, Devices and Systems, vol. 1, no. 2, pp , April A. Agarwal, M. H. Lim, M. J. Er and T. N. Nguyen, "Rectilinear Workspace Partitioning for Parallel Coverage using Multiple UAVs", Advanced Robotics, vol. 21, no. 1, January Z. Z. Zhao, Y. S. Ong, M. H. Lim and B. S. Lee, "Memetic Algorithm using Multi-Surrogates for Computationally Expensive Optimization Problems", Soft Computing, 11(10), pp , J. Tang, M. H. Lim and Y. S. Ong, "Diversity-Adaptive Parallel Memetic Algorithm for Solving Large Scale Combinatorial Optimization Problems", Soft Computing, 11(9), pp , 2007.

12 Selected Publications in 2007 List of Selected Publications J. Deng and K. Y. See, "In-circuit Characterization of Common-mode Chokes", IEEE Trans. on Electromagnetic Compatibility, vol. 49, no. 2, pp , May K. Y. See, P. L. So and A. Kamarul, "Feasibility Study of Adding a Common-mode Choke in PLC modem for EMI Suppression", IEEE Trans. on Power Delivery, vol. 22, no. 4, pp , October C. M. Tan and A. Roy, "Electromigration in ULSI Interconnects", Materials Science and Engineering R, 58, 1-75, C. M. Tan and Y. Hou, "Lifetime Modeling for Stress-induced Voiding in Integrated Circuit Interconnections", Appl. Phys. Lett., 91(6), , C. M. Tan and N. Raghavan, "A Framework to Practical Predictive Maintenance Modeling for Multi-State Systems", in press, Reliability Engineering and System Safety, K. Ma, K.S. Yeo, J.G. Ma and M.A. Do, "An Ultra-compact Hairpin Band Pass Filter with Additional Zero Points," accepted, IEEE Microwave and Wireless Components Letters, X. M. Shi, K. S. Yeo, J.G. Ma, M. A. Do and E. P. Li, "Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs," accepted, IEEE Trans. on Very Large Scale Integration Systems, August K. Ma, K. S. Yeo, J. G. Ma, and M. A. Do, "An Ultra-Compact Planar Bandpass Filter with Open-ground Spiral for wireless Application," accepted, IEEE Trans. on Advanced Packaging, August Q. Li and Y. P. Zhang, "A 1.5-V GHz Inductorless Low-noise Amplifier in 0.13-μm CMOS," accepted, IEEE Trans. on Microwave Theory and Techniques, vol. 55, no. 10, pp , October A. Poh and Y. P. Zhang, "Design and Analysis of Transmit/Receive Switch in Triple-well CMOS for MIMO Wireless Systems", IEEE Trans. on Microwave Theory and Techniques, vol. 55, no. 3, pp , March Q. Li and Y. P. Zhang, "CMOS T/R Switch Design: Towards Ultrawide-band and Higher Frequency", IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp , March G. Moldovan, P. Kazemian, P. Edwards, V.K.S. Ong, O. Kurniawan and C.J. Humphreys, "Low-Voltage Cross-Sectional EBIC for Characterisation of GaN-Based Light Emitting Devices", Ultramicroscopy, vol. 107, no. 45, pp , O. Kurniawan and V.K.S. Ong, "Investigation of Range-Energy Relationships for Low Energy Electron Beams in Silicon and Gallium Nitride", accepted, Scanning, Y. J. Yu and Y. C. Lim, "Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming", IEEE Trans. on Circuits and Systems, Part I, vol 54, no. 10, pp , October Y. C. Lim, Y. J. Yu, T. Saramäki and K. L. Teo, "FRM Based FIR Filters with Optimum Finite Word Length Performance", IEEE Trans. on Signal Processing, vol. 55, pp , June Y. J. Yu and Y. C. Lim, "Roundoff Noise Analysis of Signals Represented Using Signed Power-of-Two Terms", IEEE Trans. on Signal Processing, vol. 55, pp , May 2007.