Design and Characterization of Semi-Floating-Gate Synaptic Transistor

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1 micromachines Article Design Characterization of Semi-Floating-Gate Synaptic Transisr Yongbeom Cho 1, Jae Yoon Lee 1, Eunseon Yu 1, Jae-Hee Han 2, Myung-Hyun Baek 3, Seongjae Cho 1, * Byung-Gook Park 3, * 1 Department of Electronics Engineering, Gachon University, Gyeonggi-do 13120, Korea; jj2928@naver.com (Y.C.); ldhh1015@nate.com (J.Y.L.); yesemic@naver.com (E.Y.) 2 Department of Energy IT, Gachon University, Gyeonggi-do 13120, Korea; jhhan388@gachon.ac.kr 3 Department of Electrical Computer Engineering, Seoul National University, Seoul 08826, Korea; applewhisky90@gmail.com * Correspondence: felixcho@gachon.ac.kr (S.C.); bgpark@snu.ac.kr (B.-G.P.); Tel.: (S.C.); (B.-G.P.) Received: 14 November 2018; Accepted: 2 January 2019; Published: 7 January 2019 Abstract: In this work, a study on a semi-floating-gate synaptic transisr () is performed verify its feasibility in more energy-efficient hardware-driven neuromorphic system. To realize short- long-term potentiation (STP/LTP) in, a poly-si semi-floating gate (SFG) a SiN charge-trap layer are utilized, respectively. When an adequate number of holes are accumulated in SFG, y are injected in nitride charge-trap layer by Fowler Nordheim tunneling mechanism. Moreover, since SFG is charged by an embedded tunneling field-effect transisr existing between channel drain junction when post-synaptic spike occurs after pre-synaptic spike, vice versa, SFG is discharged by diode when post-synaptic spike takes place before pre-synaptic spike. This indicates that can attain STP/LTP spike-timing-dependent plasticity behaviors. These characteristics of in highly miniaturized transisr structure can contribute neuromorphic chip such that tal system may operate as fast as human brain with low power consumption high integration density. Keywords: semi-floating gate; synaptic transisr; neuromorphic system; spike-timing-dependent plasticity (STDP); highly miniaturized transisr structure; low power consumption 1. Introduction In 2016, AlphaGo, one of results of artificial intelligence (AI) won Go game against p-ranked Go players [1]. Because Go had been considered suitable only for humans, as it requires not only intelligence but also experience, this achievement led a media sensation. Why has AI now attracted public s attention, why has AI research become so active once again? One of reasons is efficiency of AI system. Currently, as AI technology develops, a method for increasing operation speed by using a graphic card in parallel is being adopted [2]. Hence, although amount of necessary computation is large, replicating mimicking activities that humans would carry out for human mental activities have become possible. So far, se operations have been realized in software technologies in von Neumann architecture. However, in order imitate human brain with higher resemblance, which performs great deal of mental activities with very small amount of power consumption, power efficiency should be considered more importantly now in future calling for hardware-driven neuromorphic system. In or words, efficiency should be supported not only by algorithms but also by hardware. In this respect, studies on neuromorphic chips that integrate software hardware are attracting particular interest [3 6]. Micromachines 2019, 10, 32; doi: /mi

2 Micromachines 2019, 10, 32 2 of 10 Micromachines 2019, 10, x FOR PEER REVIEW 2 of 9 In this study, we have focused on synaptic cells shown in Figure 1, which is thought be closely related experiences in human mental activity accumulation of m, as element imitate nervous system [7 10]. This This biological motivation motivation is projected is projected an electronic an electronic component, component, synaptic transisr. synaptic transisr. In order In enable order low-power enable low-power high-speed high-speed operations, operations, a poly-si semi-floating a poly-si semi-floating gate (SFG) structure gate (SFG) with structure a tunneling with field-effect a tunneling transisr field-effect is adopted transisr for realizing is adopted short-term for realizing potentiation short-term (STP), potentiation a SiN charge-trap (STP), layer a is SiN stacked charge-trap on SFG layer foris realizing stacked long-term SFG potentiation for realizing (LTP) operation. long-term Furr, potentiation we have (LTP) obtained operation. spike-timing-dependent Furr, we have obtained plasticity (STDP) spike-timing-dependent characteristic [11 13]. plasticity Finally, we (STDP) propose characteristic a novel synaptic [11 13]. Finally, that has we STP/LTP propose capabilities a novel synaptic with STDP operation that which has STP/LTP are essential capabilities functions with STDP of operation human biological which are synapse. essential functions of human biological synapse. Figure Biological nerve cell element targeted imitate by electron in in this work its its mamatical representation. 2. Device Structure Operation Schemes 2. Device Structure Operation Schemes Figure 2a shows schematic of proposed SFG synaptic transisr () its circuit Figure 2a shows schematic of proposed SFG synaptic transisr () its circuit symbol representation. Although proposed is based on integration of volatile symbol representation. Although proposed is based on integration of volatile nonvolatile memory components in a miniaturized transisr, write/erase operations are analogously nonvolatile memory components in a miniaturized transisr, write/erase operations are analogously termed as potentiation depression from stance of new synaptic functions expected from termed as potentiation depression from stance of new synaptic functions expected from proposed. As shown in Figure 2b, n + /n/p + (drain/channel/sfg) junction is embedded for proposed. As shown in Figure 2b, n + /n/p + (drain/channel/sfg) junction is embedded for low-power high-speed potentiation by hole tunneling in SFG. When first second low-power high-speed potentiation by hole tunneling in SFG. When first second gates are negatively biased drain is positively biased, potentiation occurs as demonstrated in gates are negatively biased drain is positively biased, potentiation occurs as demonstrated in Figure 2c. The fabrication has full Si processing compatibility higher mass producibility. Figure 2c. The fabrication has full Si processing compatibility higher mass producibility. Hole tunneling takes place between drain junction of first gate by Hole tunneling takes place between drain junction of first gate by operation operation of a tunnel field-effect transisr (TFET), by which holes are accumulated in of a tunnel field-effect transisr (TFET), by which holes are accumulated in SFG. This SFG. This accumulation of holes in SFG lowers threshold voltage of accumulation of holes in SFG lowers threshold voltage of increases channel increases channel conductivity eventually. These series of changes in carrier population conductivity eventually. These series of changes in carrier population potential distribution potential distribution make up potentiation process. When biases on two terminals make up potentiation process. When biases on two terminals are reversed, holes are are reversed, holes are discharged from SFG by drift diffusion due turn-on of discharged from SFG by drift diffusion due turn-on of diode part residing between diode part residing between drain junction of SFG. Equivalently, it drain junction of SFG. Equivalently, it can be undersod as electrons are can be undersod as electrons are charged in SFG threshold voltage of is charged in SFG threshold voltage of is elevated. These series of carrier elevated. These series of carrier potential redistributions make depression process happen. potential redistributions make depression process happen. Figure 3 Table 1 show mesh Figure 3 Table 1 show mesh structure parameters of simulated structure parameters of simulated by technology computer-aided design by technology computer-aided design (TCAD) [14]. The meshes are weaved more densely in (TCAD) [14]. The meshes are weaved more densely in SFG, nitride charge-trap layer, near SFG, nitride charge-trap layer, near tunneling sites for achieving higher accuracy in this tunneling sites for achieving higher accuracy in this simulation. In order obtain TCAD simulation. In order obtain TCAD simulation results with higher accuracy credibility, simulation results with higher accuracy credibility, multiple physical models including Fowler multiple physical models including Fowler Nordheim (FN) tunneling model, b--b tunneling Nordheim (FN) tunneling model, b--b tunneling model, nitride charge-trap model, model, nitride charge-trap model, concentration-dependent generation-recombination model, concentration-dependent generation-recombination model, concentration/temperaturedependent mobility models have been activated simultaneously for respective simulation tasks. The concentration/temperature-dependent mobility models have been activated simultaneously for b--b tunneling model has been adjusted with correction facrs empirically suggested by Hurks [15].

3 Micromachines 2019, 10, 32 3 of 10 Micromachinessimulation 2019, 10, x FOR PEER REVIEW respective tasks. The b--b Micromachines 2019, 10, x FOR PEER REVIEW 3 of 9 tunneling model has been adjusted with correction 3 of 9 facrs empirically suggested by Hurks [15]. Figure 2. Device structure potentiation process. (a) Aerial view of proposed synaptic Figure Device Device structure structure potentiation potentiation process. process. (a) (a) Aerial Aerial view view of of proposed proposed synaptic synaptic Figure its circuit symbol representation; (b) Cross-sectional view of ; (c) Conur of hole its circuit symbol representation; (b) Cross-sectional view of ; (c) Conur of hole current its circuit symbol representation; (b) Cross-sectional view of ; (c) Conur of hole current density during potentiation through b--b tunneling. density density during potentiation throughthrough b--b tunneling. current during potentiation b--b tunneling. Figure 3. Mesh structure of simulated with notations of terminals. Figure 3. Mesh structure of simulated with notations of terminals. Table 1. Critical dimensions process parameters in designed semi-floating-gate synaptic Table 1. Critical dimensions process parameters in designed semi-floating-gate synaptic transisr (). Table 1. Critical dimensions process parameters in designed semi-floating-gate synaptic transisr (). transisr (). Region Length (nm) Thickness (nm) Doping Concen Tration (cm 3 ) Region Region 1st Gate 1st Gate 2ndGate Gate 1st 2ndSFG Gate 2nd Gate SFG Source junction SFG Channel Source junction Source junction Drain junction Channel Channel Gate oxide Drain junction Tunneling oxide Drain junction Gate oxide Nitride Gate oxide Tunneling oxide Blocking oxide Tunneling oxide Nitride Nitride Blocking oxide Blocking oxide Length (nm) Length100 (nm) Thickness (nm) Thickness37 (nm) Synaptic Operation Characteristics 3. Synaptic Operation Characteristics 3.1. Short-Term Long-Term Potentiation Operations 3.1. Short-Term Long-Term Potentiation Operations Doping Concen Tration (cm 3) Doping Concen Tration (cm 3)

4 Micromachines 2019, 10, 32 4 of Synaptic Operation Characteristics 3.1. Short-Term Long-Term Potentiation Operations SFG is partially connected channel at end unlike commonly used floating gates which is isolated from channel. By using SFG, holes can be easily sred by tunneling current erased by drift diffusion mechanisms. Here, holes accumulated in SFG region by proper operation voltages but vanish if re is no hold bias. This characteristic can be adopted for realizing STP operation. However, when input pulses are successively provided before holes vanish, tal charges in SFG increase with time. The number of holes in SFG increases as pulses with short time interval are successively applied number of newly generated holes is larger than that of holes disappearing by eir diffusion or recombination. The higher energy states allowed in SFG region were mostly vacant due smaller occupation probabilities since y are located in tail region of Fermi Dirac distribution but now y are occupied by holes accumulated in a large number in SFG. The holes in higher energy states have higher probability of Fowler Nordheim (FN) tunneling in nitride charge-trap layer through tunneling oxide energy barrier deformed a triangular shape under a high electric field. Thus, FN tunneling has predominance in region of large amount of holes accumulated in SFG as shown in Figure 4a. These characteristics make distinction between STP LTP. Figure 4b shows actual results of simulated tal charges in SFG (left) nitride (right) regions after successive potentiating pulses. Here, charges in specified regions identify tal net charges which have been extracted by integration of current over a period of time for an operation. It should be reasonable have an individual look in electron hole densities in order investigate time-varying amount of sred charges in case of conventional floating-gate (FG) memory s. The proposed in this work equips an SFG but re should be conduction of electrons hole in out of floating gate according relation among potential distributions over diode TFET regions linked floating gate. Thus, tal net charge might make a more practical sense in this case Figure 4b conveys tal net charges vs. number of potentiation pulses. Here, a negative value implies that electrons have predominance in population, inversely, a positive one reveals predominance of holes. It is confirmed that more than three pulses are required for transition from STP LTP at bias condition of V GS1 = V GS2 = 1.5 V with a pulse width interval of 1 µs. It is expected that an increased number of pulses will be required for STP transit in LTP as tunneling oxide (TO) becomes thicker. The hole current density after a specific number of pulses is shown in Figure 5. Here, it is Figure 5 that qualitatively demonstrates directions of carrier movements over short- long-term potentiation processes. Holes are injected by operation of TFET functional region near drain for potentiation. The holes are injected in SFG a part of m occupying higher energy states in Fermi Dirac distribution after accumulation of significant amount of holes tunnel in nitride layer.

5 density after a specific number of pulses is shown in Figure 5. Here, it is Figure 5 that qualitatively demonstrates directions of carrier movements over short- long-term potentiation processes. Holes are injected by operation of TFET functional region near drain for potentiation. The holes are injected in SFG a part of m occupying higher energy states in Fermi Dirac distribution after accumulation of significant amount of holes tunnel in Micromachines 2019, 10, 32 5 of 10 nitride layer. Figure 4. Total charges in semi-floating gate (SFG) nitride regions. (a) Qualitative Micromachines explanation Figure 2019, 4. Total 10, of x required FOR charges PEER holes in REVIEW accumulated semi-floating in gate SFG (SFG) region meet nitride regions. condition (a) of Qualitative increased5 of 9 probability explanation of of injection required inholes nitride accumulated charge-trap in layer SFG by region Fowler Nordheim meet (FN) condition tunneling; of increased (b) Total Total charges probability charges in of in SFG injection (left) SFG in (left) nitride nitride (right) nitride charge-trap regions (right) after regions layer series by after Fowler Nordheim of potentiating series of potentiating pulses (FN) astunneling; apulses function as (b) of a function time obtained of time byobtained technology by technology computer-aided computer-aided design (TCAD) design simulation. (TCAD) simulation. Figure5. 5. Hole current density after after successive potentiation pulses, pulses, VGS1 V= GS1 VGS2 = V 1.5 GS2 V. = As 1.5 V. number As of number pulses of increases, pulses increases, holes at holes Fermi at distribution Fermi distribution tail accumulated tail accumulated in insfg region SFG region see see triangular triangular energy energy barrier barrier become become more more probable probable for for injection injection in in nitride nitride by by FN FN tunneling. Figure 6a shows hole distributionsin in simulated synaptic transisr after after potentiation pulses pulses are applied. are applied. The electric The electric field across field across blocking blocking oxide, oxide, nitride nitride charge-trap charge-trap layer, tunneling layer, tunneling oxide, oxide, SFG along SFG along cutline cutline A-A is A-A investigated is investigated Figure in 6b. Figure It is 6b. confirmed It is confirmed by Figure by 6a,b Figure that 6a,b that charge-trap charge-trap layer layer between between tunneling tunneling oxide oxide blocking oxide oxide layershas relatively larger population of holes injected from SFG by tunneling. Consequently, electric field across cutline is increased, with reference at pointa, A, owing holes trappedin in nitride layer.

6 Figure 6a shows hole distributions in simulated synaptic transisr after 1 20 potentiation pulses are applied. The electric field across blocking oxide, nitride charge-trap layer, tunneling oxide, SFG along cutline A-A is investigated in Figure 6b. It is confirmed by Figure 6a,b that charge-trap layer between tunneling oxide blocking oxide layers has relatively larger population of holes injected from SFG by tunneling. Consequently, electric field across cutline is increased, with reference at point A, owing holes trapped in nitride layer. Micromachines 2019, 10, 32 6 of 10 (a) (b) Figure Figure 6. Pulse-number-dependent 6. carrier carrier distribution electric electric field. field. (a) (a) Distribution of hole of hole concentration in in SFG SFG nitride nitride charge-trap layer layer (b) (b) electric electric field field along along cutline cutline A-A A-A in in (a) (a) after after potentiation 20 pulses. pulses. Figure Figure 7 shows 7 shows retention retention characteristics under under a constant a constant read read bias bias condition, condition, V GS1 VGS1 = V GS2 = VGS2 = = V DS VDS = = V, V, after different numbers of pulses are provided. When number of pulses of pulses is 0, is1, 0, 1, 3, 3, drain current decreases as time passes, n, converges in initial state due semi-floating structural characteristic. In contrast, when number of pulses is more than 3, such as 10, 20, 50, drain current converges in a higher value than that of initial state. In particular, when number of pulses exceeds 50, current levels of STP LTP are almost same. As previously mentioned, this is due trapped charges in nitride layer electric field repulsing holes downward. Furr, in both short-term long-term potentiation cases, multi-level states can be realized. Hence, it is confirmed that can distinguish between STP LTP with multi-level current states, which is essence for mimicking synaptic operation which modulates connectivity strength by frequencies. While performing STP operations, accumulated holes vanish by recombination diffusion conduction. When holes are still existing in SFG, threshold voltage of is elevated sensing current increases in accordance. On or h, number of holes in SFG decreases as time passes without successive pulses with a short enough interval time sensing current goes back original low level as result. Thus, pulse time shorter than times for recombination travelling by diffusion can only fluctuate SFG potential sensing current. However, in existence of a large amount of holes accumulated in SFG, without being provided with a long enough pulsing time be released from SFG, holes become very probable occupy higher energy states, see a lower effective energy barrier ward nitride charge-trap layer, can subsequently tunnel in nitride even at a smaller tunneling electric field necessitating a small voltage. Once holes are trapped in nitride, sensing current is semi-permanently decided invariant with time as shown in Figure 7. The additional pulses under LTP condition contribute increasing amount of holes trapped in nitride determine level of constant current, which eventually modulates electrical conductivity of presents multi-level states.

7 a lower effective energy barrier ward nitride charge-trap layer, can subsequently tunnel in nitride even at a smaller tunneling electric field necessitating a small voltage. Once holes are trapped in nitride, sensing current is semi-permanently decided invariant with time as shown in Figure 7. The additional pulses under LTP condition contribute increasing amount of holes trapped in nitride determine level of constant current, which eventually Micromachines 2019, 10, 32 7 of 10 modulates electrical conductivity of presents multi-level states. Figure 7. Retention characteristics undera a constant read bias condition, VGS1 V GS1 = VGS2 = V= GS2 VDS = = V0.5 DS = V 0.5 after V potentiating after potentiating operations operations with different with different numbers numbers of potentiation of potentiation pulses. pulses Spike-Timing-Dependent Spike-Timing-Dependent Plasticity Plasticity (STDP) (STDP) In In order order utilize utilize as a synaptic as a synaptic capable capable of STDP operation, of STDP operation, array architecture array architecture for realizing for realizing artificial spike artificial neural network spike neural (SNN) network hardware (SNN) based hardware on proposed based on proposed with full accommodation with full accommodation of operation of bias schemes operation needs bias schemes be proposed, needs as demonstrated be proposed, as in demonstrated Figure 8. Since in Figure second 8. gate Since second drain gate are tied ger, drain are tied ger, is operated as a three-terminal is operated as. a three-terminal Here, operating. Here, condition operating that biases condition of that first biases second of gates first are opposite second gates each or are opposite makes it possible each or operate makes it possible realizing operate STDP behavior. realizing Figure STDP 9 shows behavior. Figure simulated 9 shows transient simulated STDP characteristics transient STDP of characteristics for a of single triangular for a spike. single If triangular pre-neuron spike. If signal pre-neuron comes in earlier signal than comes in post-neuron earlier than signal, post-neuron time difference signal, has time a difference positive value, has a positive vice value, versa. It is vice confirmed versa. that It is confirmed that follows Hebbian follows learning Hebbian rule successfully. learning rule The successfully. change in Micromachines The weight change increases 2019, 10, in weight as x t FOR PEER increases decreases, REVIEW as Δt decreases, decreases as t decreases increases. 7 of 9 as Δt increases. Figure 8. Array architecture for for artificial artificial spike spike neural neural network network (SNN) (SNN) based based on on proposed proposed with with full accommodation full accommodation of developed of developed bias schemes. bias schemes. This can be also verified by Figure 10, which shows variation in threshold voltage by potentiated or depressed SFG. As briefly mentioned earlier, variation in threshold voltage becomes larger as t gets larger. Finally, Figure 11 shows simulated learning operations as a function of number of potentiation pulses. From results demonstrating that given pre- post-neuron signals potentiate making distinction between STP LTP, it is confirmed that designed is fully functional as a synaptic.

8 Micromachines Figure 2019, 8. Array 10, 32architecture for artificial spike neural network (SNN) based on proposed 8 of 10 with full accommodation of developed bias schemes. Figure 9. Simulated spike-timing-dependent plasticity (STDP) characteristics of after a single triangular spike. Following Hebbian learning rule [16], synaptic change is determined by Δt. This can be also verified by Figure 10, which shows variation in threshold voltage by potentiated or depressed SFG. As briefly mentioned earlier, variation in threshold voltage becomes larger as Δt gets larger. Finally, Figure 11 shows simulated learning operations as a function of number of potentiation pulses. From results demonstrating that given pre- post-neuron Figure 9. signals Simulated potentiate spike-timing-dependent making plasticity (STDP) distinction characteristics between of STP after LTP, a it is single triangular spike. Following Hebbian learning rule [16], synaptic change is determined confirmed that designed is fully functional as a synaptic. by t. Δt. This can be also verified by Figure 10, which shows variation in threshold voltage by potentiated or depressed SFG. As briefly mentioned earlier, variation in threshold voltage becomes larger as Δt gets larger. Finally, Figure 11 shows simulated learning operations as a function of number of potentiation pulses. From results demonstrating that given pre- post-neuron signals potentiate making distinction between STP LTP, it is confirmed that designed is fully functional as a synaptic. Micromachines 2019, 10, x FOR PEER REVIEW 8 of 9 Figure 10. Variation in threshold voltage by potentiated or depressed SFG. After two pulses are Figure 10. Variation in threshold voltage by potentiated or depressed SFG. After two pulses are fed fed with time difference (pre- post-input signals), potentiation depression take place under with time difference (pre- post-input signals), potentiation depression take place under conditions of Δt > 0 Δt < 0, respectively. The shorter time interval between pre- postinput signals, larger becomes variation in threshold voltage. conditions of t > 0 t < 0, respectively. The shorter time interval between pre- post-input signals, larger becomes variation in threshold voltage. Figure Simulated learning learning operations operations of of according according number number of potentiation of potentiation pulses. pulses. 4. Conclusions In this work, a novel synaptic transisr featuring semi-floating gate charge-trap layer has been proposed designed, its essential synaptic operations have been verified through TCAD simulation. The performs both STP LTP operations discriminable by number

9 Micromachines 2019, 10, 32 9 of Conclusions In this work, a novel synaptic transisr featuring semi-floating gate charge-trap layer has been proposed designed, its essential synaptic operations have been verified through TCAD simulation. The performs both STP LTP operations discriminable by number of potentiation pulses. Also, it is confirmed that multiple states, i.e., multiple conductance values can be obtained in LTP, which corresponds modulation in biological synaptic connectivity representing synaptic weight. Based on STP LTP operation capabilities, STDP operation has been verified presumable array architecture in which proposed synaptic transisr operation schemes are converged has been proposed. The proposed miniaturized transisr embedding both volatile nonvolatile memory components can be a promising intelligent component realizing hardware-driven neuromorphic system which is mainly based on semiconducr technology with full Si processing compatibility. 5. Patents (1) Seongjae Cho Yongbeom Cho, Synaptic Semiconducr Device Neural Networks Using Same, - Korean patent filed, , 16 November United States patent filed, 15/892,658, February (2) Byung Gook Park Seongjae Cho, Neuron circuit synapse array integrated circuit architecture fabrication method of same, - Korean patent filed, , 19 May United States patent filed, 15/895,255, 13 February Author Contributions: Y.C. S.C. conceived structure wrote manuscript. Y.C., J.Y.L., E.Y. performed simulations. J.-H.H. exchanged constructive discussions with S.C. confirmed biological analogies. M.-H.B. helped simulation task checked practicability of idea by evaluating process viability of proposed structure. S.C. made direction of manuscript prepared steady-state transient simulation strategies. B.-G.P. conceived hardware-driven neuromorphic system based on conventional well-matured Si complementary metal-oxide semiconducr (CMOS) processing, initiated overall research project, confirmed validities of simulated synaptic operations wards artificial spike neural network. Funding: This work was supported by Nano Material Technology Development Program through National Research Foundation of Korea (NRF) funded by Ministry of Science ICT (MSIT) (Grant No. NRF-2016M3A7B ) by Mid-Career Researcher Program through NRF funded by MSIT (Grant No. NRF-2017R1A2B ). Conflicts of Interest: The authors declare no conflict of interest. References 1. Lee, C.S.; Wang, M.H.; Yen, S.J.; Wei, T.H.; Wu, I.C.; Chou, P.C.; Chou, C.H.; Wang, M.W.; Yan, T.H. Human vs. Computer Go: Review Prospect [Discussion Forum]. IEEE Comput. Intell. Mag. 2016, 11, [CrossRef] 2. Silver, D.; Huang, A.; Maddison, C.J.; Guez, A.; Sifre, L.; Schrittwieser, J.; Annoglou, I.; Panneershelvam, V.; Lanct, M.; Dieleman, S.; et al. Mastering game of Go with deep neural networks tree search. Nature 2016, 529, [CrossRef] [PubMed] 3. Ishiwara, H. Proposal of adaptive-learning neuron circuits with ferroelectric analog-memory weights. Jpn. J. Appl. Phys. 1993, 32, [CrossRef] 4. Kuzum, D.; Yu, S.; Wong, H.-S.P. Synaptic electronics: Materials, s applications. Nanotechnology 2013, 24, [CrossRef] [PubMed]

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