Class DE Inverters and Rectifiers for DC-DC Conversion

Transcription

1 Preprint: Power Electronics Specialists Conf., Baveno, Italy, June 996 Class DE Inverters an Rectifiers for DC-DC Conversion Davi C. Hamill Department of Electronic an Electrical Engineering University of Surrey, Guilfor GU 5XH, Unite Kingom Abstract A new family of Class DE inverters an relate rectifiers is presente. Base on the Class D rf inverter, the circuits feature Class E switching transitions (zero voltage, zero v/t), giving low switching losses espite evice capacitance an store charge, combine with low voltage stress. Matching between inverter an rectifier is consiere, time reversal uality is introuce, an a family of inverters an rectifiers is presente. The circuits shoul fin application in megahertz c-c converters. (a) I. INTRODUCTION This paper escribes a family of inverters an rectifiers featuring zero voltage, zero v/t switching. The inverters are a hybri between the Class D an Class E rf amplifiers. Their switches turn on at zero voltage an zero v/t, giving low switching losses espite intrinsic evice capacitance. The rectifier waveforms are time reverse versions of the corresponing inverter waveforms. The rectifier ioes start to block uner conitions of zero voltage an zero v/t; thus ioe capacitance an charge storage o not have a eleterious effect. After a brief escription of Class D, E an DE rf power amplifiers, a half brige Class DE inverter is stuie from a theoretical stanpoint. Next the corresponing Class DE rectifier is introuce an analyse in a similar way. To form a Class (DE) c-c converter the inverter an rectifier must be combine, an the matching requirements are examine. The concept of time reversal uality is briefly introuce, then some more Class DE inverter an rectifier topologies are presente. The circuits shoul be suitable for use in c-c converters with megahertz switching frequencies. II. CLASSES D, E, AND DE The purpose of a raio frequency power amplifier is to eliver, with reasonable efficiency, a sinusoial signal having low harmonics an other spurious components. Rf power amplifiers are classifie by the operation of their output transistors. Classes A to C use transistors in the active region, so they are (b) Fig. : (a) Class D an (b) Class E inverters, showing parasitic switch capacitances an ioes generally unsuitable for use in power converters, where efficiency is far more important than signal purity. To increase efficiency, the transistors may instea be operate as switches. The earliest example, now known as Class D, ates from 959 []. Shown in Fig. (a), it is a two-switch topology in which the switches conuct on alternate half cycles, each with a conuction angle approaching 80. A series resonant tank converts the square voltage waveform into a sinusoial loa current. The transistors operate with zero current switching (ZCS), turning on an off as the loa current crosses zero. The Class D amplifier is familiar in a power conversion context as the voltage fe half brige series resonant inverter. Although it is theoretically 00% efficient, in practice Class D suffers from switching loss because the inherent evice capacitances must be charge an ischarge every switching cycle, issipating energy an thus reucing efficiency. The effect worsens at higher frequencies, until the low losses expecte from ZCS are no longer achieve. Class E, shown in Fig. (b), was introuce in 975 []. It overcomes the evice capacitance problem by means of zero

2 V I / S D S C s Z I pk i φ/ω t V I / S D S C s i v Matching Network Z Loa V I / v V I / t 0 voltage switching (ZVS). The switch is turne on only when its shunt capacitance has been ischarge by the surrouning circuit. (More recently, ZVS has been wiely applie to quasiresonant c-c converters.) However, in true Class E operation the switch also closes when v/t = 0, giving low sensitivity to the circuit parameters an switching times. A isavantage of the current fe Class E circuit is that it imposes a much higher peak voltage stress on the switches than the voltage fe Class D: in optimum Class E operation the stress is 3.6 times the c input voltage [3], compare to unity for Class D. Both circuits see similar peak currents. A hybri combining the best features of Class D an Class E operation was first propose by Zhukov an Kozyrev in 975 [4], but their work was unknown in the West. In this hybri the sinusoial output current swings the voltage from one c rail to the other uring a short ea time when both switches are open. Steigerwal [5] note the use of zero voltage switching in Class D, but i not analyse it. Recently the ZhukovKozyrev circuit was reiscovere by Koizumi et al. [68]. They employe a uty factor of 5%, an coine the term Class DE for its zero voltage, zero v/t switching. The circuit was also investigate inepenently by El-Hamamsay [9], an a generalise version of the amplifier (with arbitrary uty factor) was analyse by Hamill [0]. III. HALF BRIDGE CLASS DE INVERTER Fig. shows the circuit of a half brige Class DE inverter which will be stuie in etail. For convenience the c input is shown as a centre tappe supply. An ieal switch, a ioe an a capacitor moel each of the two switching evices (in practice, probably MOSFETs). The capacitor inclues the evice capacitance plus any aitional external capacitance. A high Q matching network forces the inverter s output current waveform to be almost sinusoial. A. Operation Fig. : Half brige Class DE inverter circuit Fig. 3 shows the inverter s waveforms. With each switch shunte by capacitance C s, the total capacitance C s is charge by the negative output current i when switch S S S opens at t = 0. The inverter s output voltage v rises from the negative rail towars the positive rail, which it reaches at time t 0. Dioe D S prevents v from rising further, an S is turne on with ZVS at t 0. The other half cycle is similar. B. Analysis conucting D s Let the c input voltages be ± V I / an the inverter s output current be i (t) = I pk sin(ωt φ), where ω/π is the switching frequency an φ [0, π] is a phase angle. (I pk an φ both epen on the matching network an the loa impeance.) For Class E transitions, v /t = 0 at t 0. Since v /t = i /C s, i (t 0 ) = 0 so φ = ωt 0. If each switch operates with a uty factor D s [0, ½], then from Fig. 3, D s = (π φ)/π. To swing v from V I / to V I /, the total switch capacitance C s must be supplie with charge C s V I = i (t) t. Integrating an solving for I pk, I pk = ωc sv I cos φ (Note that a small phase angle φ implies a large peak current.) Substituting for i in v /t = i /C s an integrating, v (t) = V I cos(ωt φ) ( cos φ) ( cos φ) conucting D s Fig. 3: Waveforms of the Class DE inverter, t [0, t 0 ] In Class E analysis an effective impeance approach is often use. Moreover, the quantities are usually normalise with respect to a reference impeance (usually the reactance of the switch capacitance). That approach is aopte here: current i (t) is represente by a phasor, I, an the funamental component of voltage v (t) is represente by another phasor, V. (Only the funamental nee be consiere, as the high Q matching network rejects harmonics.) Hence an effective loa impeance Z = V /I can be calculate. () ()

3 X D s = 0. Class DE locus D s = 0. Z i Ieal tank X L i Z X = 0 v X v C R / ZVS region D s = 0.5 Fig. 5: Matching network for variable resistive loa Fig. 4: Normalise effective loa impeance plane (NELIP) for the Class DE inverter The funamental components of v (t) an i (t) can be foun by Fourier analysis. Suppose some quantity a is perioic with perio : a(t) = fω(t). Its funamental component can be expresse as the phasor A = ω π 0 f ω (t) e jωt t. Since v (t) has similar positive an negative half cycles, the phasor representing it is foun as V = ω π 0 φ/ω v (t) e jωt t φ/ω = VI φcos φ sin φ jφsin φ π( cos φ) Similarly, i (t) can be represente by I 0 D s = 0.4 VI e jωt t = ω π 0 Ipk sin(ωt φ) e jωt t = ωc sv I(sin φ jcos φ) cos φ D = 0.3 s 0 / π R The effective impeance seen by the inverter is Z = V /I = R jx, say. Further, Z is normalise by multiplying by ωc s to give the imensionless quantities R = sin φ π, X φ sin φcos φ = π Normalisation is enote by a prime ( ). The complex plane spanne by the real an imaginary components of Z, i.e. the R X plane, will be esignate the normalise effective loa impeance plane (NELIP). Equations (5) escribe parametrically the locus of Class DE operation in the NELIP; see Fig. 4. (The locus can be shown to be a cycloi, the curve trace out by a point on the circumference of a circle of raius /π as it (3) (4) (5) rolls on the X axis.) Values of the require uty factor D s are also marke, from D s = (π φ)/π. Class DE waveforms have been verifie by simulation an experimental measurement at various points on the locus. C. Moes of Operation The effective loa impeance applie to the inverter affects its moe of operation. Suppose that I pk = α I pk(de), where I pk(de) is the critical value of I pk given by (), an α > 0. If Z is too large, I pk will be less than the critical value (α < ). Then v (t) will peak before it reaches V I / an fall back, so ZVS will not obtaine. This inefficient moe of operation occurs everywhere in the NELIP except for the region boune by the Class DE locus an the axis. X On the other han, with small values of Z, I pk will be greater than the critical value (α > ). The transitions become orinary ZVS (v /t 0). This operation occurs within the region of the NELIP boune by the Class DE locus an the X axis. Now v (t) reaches V I / while i (t) is still negative, forcing ioe D S to conuct, at an angle ψ given by ψ = φ cos (α )cos φ α The ioe comes out of conuction when i (t) reaches zero, at an angle φ as before. There is therefore some latitue in the switch turn-on angle, which may be between ψ an φ. In the critical case of true Class DE operation (α = ), ψ = φ so there is theoretically no latitue. Nevertheless, v (t) stays close to V I / for some time (v /t 0), so the exact turn-on instant is not critical a quintessential property of Class E inverters. D. Matching Network A matching network is place between the inverter an its loa impeance, Z = V /I. This network has two functions: ) it forces the inverter s loa current to be nearly sinusoial, usually by incluing a series resonant tank; ) for any given value of Z it shoul ieally give a value of Z lying within the efficient region of the NELIP. Suppose the inverter is operate with a resistive loa Z = R. The matching network maps each value of R to a (6)

4 v i Z D D C C C O C O V O / V O / I pk i V / O v V / O φ/ω t 0 t point in the NELIP. If the matching network contains only reactive elements, then when R = 0 an R =, Z will be purely reactive too, i.e. the ens of the locus will lie on the X axis. With proper esign, the whole of the locus can be mae to lie within the ZVS area. Fig. 5 shows an example of a simple LC matching network. Suitable normalise reactance values are X L = (π )/π, X C = /π. With a short circuit, R = 0 maps to Z = 0.883j. As R increases, the locus moves away from the X axis until it reaches Z = /π ½ j (on the Class DE locus) when R = /π. It then moves back until, with an open circuit, Z = 0.87j. Thus the locus stays within the ZVS region of the NELIP, close to the Class DE locus, permitting efficient operation with any value of resistive loa. E. Switch Utilisation A utilisation factor for the switches in an ieal power converter may be efine by U = P/(V max I max n), where P is the power throughput, an V max an I max are the voltage an current stresses on each of the n switches. U, which lies between 0 an, is useful for comparing iverse topologies. For Class DE, P = Re V I = V I ωc s π cos φ cos φ Also V max = V I, I max = I pk, given by (), an n =. Hence U = ( cos φ)/4π. Its best value, U = 0.59, is obtaine when φ = 0 (D s = 0.5: classical Class D). The optimum Class E inverter has U = [3], which the Class DE inverter betters with D s > 0.9. In summary, with low voltage stress, low switching loss an acceptable switch utilisation, the Class DE circuit is an attractive inverter for high frequency operation. IV. Fig. 6: Half brige Class DE rectifier circuit HALF BRIDGE CLASS DE RECTIFIER The nee for rectifiers with smooth switching transitions an ZVS has been acknowlege by other workers, e.g. [, ]. The rectifier of Fig. 6 is a close relative of the half brige Class DE inverter [3]. It too is insensitive to capacitive effects, C subsuming the junction capacitance an iffusion (7) D D charge storage that plague real rectifier ioes at high frequencies. A. Operation It is assume that the circuit is fe by a sinusoial current, the ioes are ieal, the two capacitances C are ieal an linear, an the two output capacitances C O are infinite. By symmetry, each C O carries an equal voltage. The c loa is a resistance. Refer to Fig. 7 for waveforms. At t = 0, the input current i becomes positive an D, which was previously conucting, starts to block. The current therefore iverts to charge the total ioe capacitance C. At t = 0, v /t = 0, giving a Class E transition. The input voltage v starts to rise from the negative output rail to the positive one, which it reaches at t 0. Then D comes into conuction, an remains conucting until i changes sign again. The other half cycle is similar. B. Analysis conucting D Let the input current i (t) = I pk sin ωt, an let the voltage across each output capacitor C O be V O /. Integrating v /t = i /C an using the fact that v (0) = V O /, voltage v is foun as I pk v (t) = ωc ( cos ωt) V O At t = 0, v /t = i /C = 0 (Class E). The transition ens at t = t 0, when v (t 0 ) = V O /. Writing φ = ωt 0, from (8) we have cos φ= ωcvo I pk conucting D Fig. 7: Waveforms of Class DE rectifier From Fig. 7 it can be seen that the uty factor of each ioe is D = (π φ)/π, lying between 0 an ½. (8) (9)

5 0 0 / π R D = 0.4 = 0 D = ½ D = 0.3 ½ X = D = 0 = π D = ¼ D = 0. It is useful to know the effective input impeance of the rectifier at the input current frequency. Using Fourier analysis as for the inverter, in phasor form v (t) an i (t) become an V = ω π φ/ω v (t) e jωt V t 0 O φ/ω e jωt t = VO I sin φcos φ φ jφsin φ π( cos φ) (0) = ω π 0 Ipk sin ωt e jωt t = ji pk D = 0. Fig. 8: Normalise effective input impeance of the Class DE rectifier () Substituting for I pk from (9) into (), the effective input impeance is foun as Z = V /I. After normalisation (now using ωc ) this becomes Z = ωc Z = sin φ j(sin φcos φ φ) π Therefore the normalise resistance an reactance are R = sin φ π, X sin φcos φ φ = π () (3) As for the inverter, varying φ traces out a cycloial locus in the Z plane. This is shown in Fig. 8, with several values of the ioe uty factor D also marke. Often it is convenient to work in terms of the circuit quantities, as etermine next. The charge flowing through D into the upper C O reservoir capacitor uring a cycle is Q = i (t) t = I pk φ/ω ω C V O (4) (Aitional charge flows in via the ioe capacitances uring the interval [0, φ/ω], but an equal amount flows out uring [, (π φ)/ω], cancelling out.) The charge flowing through uring a cycle is Q = ()V O /. In the steay state, Q = Q ; hence I pk = V O (π/ ωc ). Substituting into (9) an using the ientity sin φ cos φ =, Writing an Fig. 9: Plot of rectifier output voltage V O as a function of loa resistance. Line: theory; points: PSpice simulation with non-ieal ioes cos φ= π ωcrc π ωc, sin φ= = ωc, (3) yiels R = 8 π R c 4πωC π ωc X = 8 π R π c π R π cos c π c Values of are inclue in Fig. 8. Finally, from (9) the total output voltage may be foun as V O = C. Moes of Operation I pk π ωcrc (5) (6) (7) (8) Unlike the inverter, in which there are three operating moes, the rectifier has only a single moe of operation: Class DE. Whereas the inverter switches can be turne on or off at

6 any esire instant, the ioes, acting as passive switches, have no such freeom: their switching operation is constraine by the voltages an currents in the surrouning circuit to be Class DE, with the requisite uty factor. D. Simulation Results PSpice simulations were performe to verify the analysis. With I pk = A, ω/π = MHz an C = nf, non-ieal ioes were moelle by the statement.model DIODE D(Is=00f Rs=0m Cjo=00p Tt=50n). (The ioe capacitance was aitional to the external C.) Lea inuctance of 0nH was put in series with each ioe. Fig. 9 shows goo agreement between (8) an the simulation results over four ecaes of loa resistance. This being a current fe rectifier, the ioe conuction voltage oes not affect the output voltage. V. MATCHING INVERTER AND RECTIFIER It is interesting to consier a Class DE inverter riving a Class DE rectifier, forming what might be terme a Class (DE) c-c converter. Compare the require loa impeance locus for the inverter, Z (Fig. 4), with the input impeance locus of the rectifier, Z (Fig. 8). They are the same size an shape, but iffer by X =. In the special case where C s = C, the esign of the matching network is particularly simple. Apart from the series resonant tank tune to ω, all that is neee is aitional series inuctance proviing reactance X L =. This will shift the rectifier s impeance locus vertically so it exactly overlies the Class DE locus in the inverter s NELIP. In practice, the extra inuctive reactance can be obtaine simply by increasing the inuctance in the series tank circuit; the matching network simply consists of L an C in series. Subject to the approximations mae in the analysis, this matching network will allow Class DE operation of both the inverter an the rectifier, no matter what the rectifier s c loa. If the inverter s uty factor is properly chosen, both the inverter an the rectifier will enjoy low switching losses. Transformer coupling with an arbitrary primary-toseconary turns ratio N : N is also possible. The values of C s an C must be correctly chosen, viz. to satisfy C Cs = N N (9) The transformer s leakage inuctance can be absorbe into the series tank circuit, while its magnetising inuctance can be cancelle by aing a shunt capacitor to resonate at ω. The Class (DE) c-c converter is a promising caniate for megahertz c-c conversion. Possible methos for controlling the output inclue frequency moulation, asymmetric PWM, phase shift control, an synchronous rectification. VI. TIME REVERSAL DUALITY As evience by Figs. 3 an 7, the waveforms of the Class DE rectifier are time reverse versions of the inverter waveforms. The unerlying relationship connecting the two circuits is time reversal uality [4]. This concept can be touche upon only briefly in this paper. The traitional uality between voltage an current has been well unerstoo for many years. Time reversal uality is a ifferent relationship, in which the corresponing waveforms of two systems are time reverse versions of each other. Time reversal in the context of c-c conversion has been emonstrate or remarke upon by several workers [], [57]; however, they i not explore the relationship further. In fact it applies to a wie variety of physical systems. Suppose D is an n-imensional continuous ynamical system with state vector x Å n, characterise by the vector ifferential equation x t = f [x, t] (0) Given an initial conition x(0), equation (0) may be integrate to generate a state-space trajectory x(t). Now let D # be another ynamical system with state vector x # Å n, such that x # t = f x #, t () an x # (0) = x(0). It can be shown that x # (t) = x(t) for all t, i.e. the corresponing waveforms are time reverse versions of each other. The systems D an D # are time reversal uals. This result can be applie to electrical networks. It turns out that there are four ways to form the time reversal ual of a circuit. Of these, the most intuitive an useful is Type uality, in which the reference irection of all currents is inverte. Suppose an animate film were to show the operation of a circuit with its currents represente by moving charges. Projecte in reverse, the charges woul move backwars, while the voltages woul remain in their original polarity. All waveforms woul be time reverse. Because current is negate but not voltage, power in the time reversal ual circuit is also negate: the irection of energy flow is reverse. This allows a rectifier to be turne into an inverter, for example. To procee further, the theory must be extene to inclue switches an ioes. Certain ifficulties arise with switches, but work is uner way to clarify them. A time reverse ieal ioe may always be replace by an appropriately riven ieal switch. VII. OTHER CLASS DE CONVERTER TOPOLOGIES Time reversal uality forms the basis for transforming Class DE rectifiers into the corresponing inverters. The Class DE rectifier of Fig. 6 can be erive from a simple half wave

7 converters operating in the megahertz frequency range. These shoul offer high efficiency, goo electromagnetic compatibility an the potential for miniaturisation. (a) (b) (c) () (e) (f) Fig. 0: Class DE rectifierinverter pairs. The full brige rectifier (a) transforms uner time reversal uality to the full brige inverter (b), or its egenerate form (c), the asymmetric half brige inverter. The full wave rectifier () transforms to the push-pull inverter (e), or its egenerate form (f), the forwar converter. (Matching networks are not shown.) oubler type rectifier by aing shunt capacitance to the ioes. Time reversal uality allows the synthesis of the corresponing inverter, the half brige inverter of Fig.. It is not ifficult to apply the same principle to other rectifiers an so evise other Class DE ZVS inverters. Examples are shown in Fig. 0. Biirectional converters are also possible. Furthermore, voltagecurrent uality can be applie inepenently, generating ual Class DE converters with ZCS. These may be useful with evices such as IGBTs, or when stray inuctance is problematical. VIII. CONCLUSION This paper has escribe a Class DE inverter an rectifier, whose smooth switching transitions make them suite to high frequency c-c conversion. The rectifier an inverter are linke by a time reversal uality relationship. Applying this to other rectifier circuits permits the synthesis of further members of the Class DE family. With appropriate matching an control circuits, it is hope that they will lea to Class (DE) c-c

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