A Four Level Inverter Based Drive With a Passive Front End.

Transcription

1 A Four Level nverter Base Drive With a Passive Front En. Gautam Sinha EEE Stuent Member Thomas A. Lipo EEE Fellow Department of Electrical & Computer Engineering University of WisconsinMaison 45 Engineering Drive Maison W , USA Tel: (68) / (68) 6 87 Fax: (68) 6 67 E Mail : gautam@cae.wisc.eu / lipo@engr.wisc.eu AbstractÑMultilevel inverters are suite for high power rive applications ue to their increase voltage capability. A four level inverter is able to synthesize better waveforms an attain higher voltages while reucing the evice ratings. While converter evice count an kva are high. a conventional ioe brige rectifier is a low cost multilevel rive solution for the input rectifierif suitable inverter sie c voltage balancing schemes can be evise. This paper investigates the operation of four level rectifier/inverter base rives uner commonly use moulations schemes. Link voltage balancing an output voltage capability are analyze for a four level inverter. Simulation results are presente to verify the link voltage balancing strategy in the absence of any balancing action from the rectifier.. NTRODUCTON. Multilevel inverters are base on the neutral point clampe inverter topology first propose by Nabae et al []. For high power rive applications, three level inverter base rives an control scheme have been extensively stuie [6]. The tren towars a greater number of levels is necessitate by avantages of higher voltage ratings. For example, V evices are normally reuire in a conventional VS with a DC bus voltage of 6V whereas using the same evices an a three level inverter, the DC bus can be rate at V. With a four level inverter, the DC bus voltage can be raise to 8V. Thus, there are clear avantages to using multilevel inverters especially when the voltages can be raise sufficiently high enough to eliminate transformers. Associate with multilevel inverter base rives is the problem of DC link voltage balancing. However, reunant states offer a metho of reistributing the charge amongst the DC capacitors. The severity of the problem varies with the application. n case of static var compensation, voltage balancing is much easier since the power flow is essentially reactive. t is possible to regulate the link voltages using a low freuency switching scheme an properly selecting the reunant states. n rive applications, the availability of reunant states will etermine whether the link voltages can be balance. Also, it is not always possible to balance the link voltages at every switching event. n rive applications, real power flow leas to the rift of the link 'neutral' voltages in a multilevel DC bus. Capacitor voltages can be balance with the help of an active rectifier as iscusse in [7,8,9]. Aitionally, with an active rectifier, the DC voltage is reuce an the inverter moulation is relatively unconstraine by link voltage balancing reuirements. The rawback of this approach is that there are now two active converters which increases the cost of the rive system. Partially active rectifier topologies as in [7] are compromise solutions which have a lower kva rating than a fully active rectifier an a lower power transfer capability. The simplest metho of connecting a multilevel DC bus to the utility is by the ioe brige rectifier ue to its greatly reuce cost. n this paper, the passive solution i.e. a ioe brige rectifier front en is consiere since it represents the simplest configuration of the multilevel rive. For example, a fully active 4 level rectifier/inverter system has a nominal total evice kva rating of 4V c max : a partially active four level rectifier an a four level inverter has a evice kva rating of V c max whereas a ioe rectifierfour level inverter system has a total evice kva rating of 8V c max. For larger rives, the cost benefits of reuce evice kva may prove avantageous especially when utility harmonic currents may be reuce by active filters.. THE FOUR LEVEL NVERTER. Of the three prominent multilevel topologies, the ioe clampe inverter topology has been foun to be suitable for rive applications primarily because of reuce component evice ratings an count [] though the cascae H briges topology [] is extremely moular an robust for practical applications. The four level ioe clampe inverter is the only topology iscusse further. (Fig. ).

2 33 V DC C 3 C C i a i b i c Fig. Four level inverter (ioe clampe topology) Fig. Four level inverter switching states in plane. Fig. shows the switching states of a four level inverter in the plane which are obtaine accoring to the transformation euations: (h a,h b,h c ) = 3 h a h b h c ; (h a,h b,h c ) = h b h c 3 n(h a,h b,h c ) = h a h b h c () 3 Therefore, in a three phase four level inverter there are 64 switching states an can be classifie [] base on their properties as shown in fig. 3. Using the Dirac elta function, the phase A pole voltage can be written in terms of capacitor voltages as: v ao = δ (h a ) δ(h a )( V C ) () δ (h a 3)( V C V C3 ) h a is the phase A switching function. h a =,, or 3. t can be euce by KCL that 3 =. Therefore: δ (h a )δ(h a ) δ (h a ) δ (h a 3) = (3) Phase B an C pole voltages can be expresse similarly. The inverter DC noe currents can then be represente as: DC (t) = H(t) ph (t) (4) [ ] T an [ ] T DC (t) = (t) (t) (t) 3 (t) ph (t) = i a (t) i b (t) i c (t) δ(h a ) δ(h b ) δ(h c ) δ(h a ) δ (h b ) δ (h c ) an H(t)= δ (h a ) δ (h b ) δ (h c ) δ (h a 3) δ(h b 3) δ(h c 3) For a three wire loa i a i b i c =, so (4) is moifie to: DC (t) = M(t)(t) (5) where DC (t) = (t) (t) (t) [ ] T ; (t)= [ i a (t) i b (t)] T an δ(h a ) δ(h c ) δ(h b ) δ(h c ) M(t)= δ(h a ) δ (h c ) δ (h b ) δ (h c ) δ (h a ) δ (h c ) δ (h b ) δ (h c ) S S S S 3 S 3 3 S Fig. 3 nverter switching state classification. The DC capacitor voltages are given by: 3 3 C t v C = F DC (t) (6) [ ] T, C = 3C DC an [ ] T (7) where v C = v C (t) v C (t) v C3 (t) F = ; ; Therefore, from (5) an (6), we get C t v C = F M(t)(t) (8) E. (8) represents a physical system with a variable structure since the matrix M(t) is moulation epenent ( rank(m(t)) ). The ifferential moe component of each capacitor voltage is then given as: V C = V C [ ] T V CM (9) where T = [ ; ; 3 ]T V CM = v C v C v C3 () 3 Since rank(t) =, only two of the three capacitor voltage eviations are inepenent. V CM is the common moe capacitor voltage which can be consiere as resulting from a common charging current. By ifferentiating (9) an substituting (8), one obtains: t v C = T F M(t)(t) () C Capacitor voltage unbalance in an interval t < t < t is minimize when: t v C = C T F M(x)(x) x = minimum () t

3 A necessary conition for this to occur is: v C T F M(t)(t) (3) When (3) is satisfie, the capacitor voltage unbalance is guarantee to not grow. The interval t t is usually the switching interval over which the loa current ynamics o not change appreciably. Hence, at the start of a switching interval, computations can be mae about the switching state to be selecte base on the currently available values of the loa currents. Link voltage balancing then can be formulate as a problem in fining a suitable switching state (h a,h b,h c ) which will satisfy (3). There are 64 switching states an fining a switching state to satisfy (3) is, in general extremely computationally intensive. Simplification of (3) leas to a more insightful version of the voltage balancing conition i.e. v C i C v C i C v C3 i C3 or v C ( ) v C (4) E.(4) can be combine with (4) to etermine the effect of selecting a switching state on the link voltage unbalance.. Therefore, if an S 3 state is selecte, (4) is always satisfie with the euality hence link unbalance, if any, oes not worsen. However, this correspons to the largest voltage vectors being use (two level operation) an consistent selection of such states makes poor utilization of the low THD waveform generation capability of the inverter. To gain a further insight into the nature of link voltage balancing, (4) can be recast into the following form: V V (5) where : V = v C v C an V = v C From (5) it is evient that two neutral voltages nee to be regulate. E. (5) also suggests a strategy as follows: select a switching state which prouces a DC noe current of the polarity opposite that of voltage of the noe into which it flows. For example, if V > an V <, link unbalance is reuce if we select only those states which prouce > an <. t is not however guarantee that such states can be freely selecte expressly for link voltage balancing. n a typical application, the inverter moulation scheme such as sine triangle PWM, current regulation etc. etermine the voltage vector that the inverter must prouce. Also, as shown earlier multiple switching states (n 3 ) prouce the same voltage vectors (3n(n) thereby illustrating the phenomenon of reunant states. Assuming that the inverter is reuire to prouce a voltage vector (v, v ) the switching states that will prouce the reuire voltage vector can be etermine by inverting (). The solutions have to be integers satisfying h a, h b, h c 3. The exact number of reunant states will epen on the magnitue of v an v. When the inverter is reuire to prouce a vector (v,v ), inverter DC currents are evaluate for each constituent switching states using (4). E. (5) is then teste for suitability for link voltage balancing. That switching state is selecte which prouces esirable DC currents.. CAPACTOR VOLTAGE BALANCNG WTH SNE TRANGLE PWM. n the previous section, a mathematical conition for link voltage balancing was erive. Given the freeom to select any switching state from the four level inverter, the link voltages can be riven towars balance at each switching state selection event. However, the inverter operation is constraine by a moulation scheme typical of which is the sine triangle PWM scheme. The four level sine triangle algorithm is base on the multilevel sine triangle PWM scheme first propose in [3]. Fig. 4 shows the isposition of the triangle carrier waves an the reference sinusoi. This scheme prouces at its output the three phase switching functions accoring to: h a = 3 if v a v rc h (t) a h a = Time (msec) Fig. 4 Four level sine triangle PWM scheme. if v rc3 v a v rc = if v rc v a v rc = otherwise The phase switching functions of the other two phases are similarly efine. Supposing that the state (h a,h b,h c ) is the PWM pattern, the number of reunant states, if any, can be etermine from: N re = 3 max(h a,h b,h c )min(h a,h b,h c ) (6) The resulting DC noe currents for each consitutive switching state is evaluate from (4). E. (5) is evaluate for each switching state an that switching state is selecte which prouces the most positive left han sie in (5). n multilevel inverters, visualizing the voltage eviations is not tractable especially for n 3. n orer to obtain a clearer unerstaning of voltage eviation pattern of the four level DC bus we rewrite (5) as: E = V ( X i X i ) V ( X i X i ) (7) X j = δ (h a j) δ(h b j)δ(h c j) (8.i)

4 3 X j = ( δ (h b j) δ(h c j) ); j =, (8.ii) By integrating (7) over one funamental perio, a necessary conition for the link voltages to remain balance can be establishe as: T T V (x) x = V (x) x = (9) This in turn implies that: V ( X ) < an V ( X ) < () The imensionless 'vectors' X an X for a 4 level inverter epen on the voltage vector itself. This representation is useful in etermining the effect of selecting a voltage vector on link voltage balancing. Figs. 57 illustrate the orientation of X an X relative to the voltage vectors for each class of switching states. Consiering fig., it can be seen that the V() X ( ) X (3 ) X ( ) X (3 3) X ( ) X (3 ) X ( 3) X (3 ) X ( ) 6 o X ( ) X ( ) X ( ) X ( ) V( ) 6 o V(3 ) X (3 )=X (3 )= X (3 3)=X (3 3)= Fig. 5 Disposition of S 3, S voltage & X, X vectors. V( ),V(33 ) X ( ) X (3 )= V( ),V(3) X (3 3 )= X ( )= o X ( )= 3 o X (3) 6 o X ( ) X ( ) X ( ) X ( 3) V(),V( 3) o X (33) V( ) V(3 3) Fig. 6 Disposition of S S voltage & X, X vectors. X (3 ) X (3 ) =X (3)= 3.9 o 6.6 o X (3 ) 9. o 9. o V(3) V(3 ) X (3 ) X(3) 35 o X (3) =X (3 )= 38. o 38. o V(3 ) V(3 ) Fig. 7 Disposition of S voltage & X, X vectors. magnitue of the inverter voltages varies with the moulation epth m a. Fig. 8 shows the graphical euivalent of () applie to S states. Accoring to the balancing scheme, for V > an V >, if X (h a,h b,h c ) belongs to region (or = ) then V can be regulate an if X (h a*,h b *, h c* ) belongs to region (or = ) then V can be regulate. n fig. 7, for the loa current vector as shown, state (3) will regulate the DC voltages most effectively. For S states, it is always possible to select a switching state which prouces current of an appropriate polarity through any DC capacitor. A similar graphical euivalence can be erive for each of the switching state classes. X ( ) X (3 ) X ( )= X (3)= X ( ) X ( ) f V( ) Fig. 8 S Switching state selection for voltage balancing. X ( ) X (3 ) X (3 ) o f 3 o s V( ),V(3) X ( ) s Fig. 9 S Switching state selection for voltage balancing. When a voltage vector corresponing to an S state is selecte, it can be shown that for at least one switching state both DC voltages can be regulate. Thus, from fig. 9 it is evient that state (3) will regulate DV an DV. A similar argument hols for S states. For S 3 states, X = X = ientically an so link unbalance never worsens as a result of selecting S 3 states. When an S 3 or S 3 state is selecte, two cases arise as illustrate in fig.. n fig. (a), the selection of state (3) results in an appropriate polarity of current to regulate DV but selection of (3) with the loa current at the same power factor will cause a charging current of the opposite polarity thereby worsening the unbalance. A similar result can be shown to hol for S 3 states. When S 3 states are selecte, as state earlier, the capacitors are charge symmetrically. Thus, when outer hexagon states are use, it follows that unbalance will result. This is the funamental limitation in the link voltage balancing capability of the four level inverter. Note that the limitation arises from the fact that there are now no reunant states available which will regulate the DC voltages. Assuming ieal an balance three phase loa currents, in the limiting case when only the S 3, S 3 an S 3 states are use the average values of the DC currents are given by: = =6 cos f sin( l ) cos(p /3l); () where l = 9. o an is the peak value of the loa phase currents. Also,

5 i C = i C3 = i C3.88 cos f () ( ) = i C3 (3) i C = i C3 Thus, the innermost capacitor tens to ischarge for any real loa because cosf ¹. Also, there is symmetry in the charging of an V C3. Typically, in the absence of any balancing action, V C unergoes inversion leaing to a catastrophic shutown. X (3) X (3)= o f V(3) s o X (3) X (3)= f s V(3) Fig. S 3 Switching state selection for voltage balancing. e un e vn 3 5 C R BRAKE C e wn S UTL TY 4 6 BRAKE C V, 6 H Z 3.7 % nverter ga ti ng sig nal s DC C apa citor Voltag es C ontrol i a i b i c Motor ph ase currents Fig. Four level inverter base rive system. M w r T e V. SMULATON RESULTS. Fig. shows the rive system that has been simulate to verify the theory evelope in the previous sections. This system is currently being constructe at the University of Wisconsin. The loa is a 5 HP 8 pole 46/3V inuction motor. 6V/A GBTs are use as the active switches. The control scheme implemente is base on the scheme outline in the previous section. A four level PWM scheme provies the pulse pattern to a reunant state selector. n [4], a control scheme for such a topology with RL loas only is iscusse.. Fig. shows the block iagram of the control scheme. The reunant state selector performs the link voltage balancing. t shoul be note that the input to this block can be voltage vectors resulting from any control scheme such as m f Fre. ratio f o Ref. Freu ency 8 DC bus voltages (V) V an (V) a (A) m a Mo ula ti on e pth Ca rrier v tr3 Gen. v tr v tr Sine v cref Ref. Gen. v bref v aref Vo ltage Bala nce Ena ble Pulse Pattern Gene rator h c * ENABLE DV C3 DV C D h b * h * a Fig. nverter control scheme. i a i b Ba lan cing Algorithm DV DV h c h b h a To Gate Dri ves V (V) DS Fig. 3 Motor phase voltage an current at 73 RPM. V C V C3 V C Fig. 4 DC bus voltages at low spees (73 RPM) V (V) DS RPM 569 RPM V (V) V (V) QS QS Fig. 5 V s an V s at & 4 Hz. current regulation or fiel orientation. n this particular case, a simple V/Hz control scheme was implemente. Fig. 3 shows the motor phase voltage an current for a low spee operation case. For a low carrier freuency of 4 Hz, the current THD is reasonably low at about %. The actual

6 evice switching freuency varies with the location of the evice in the inverter pole. Depening on the loa currents an link voltages, the actual evice switching freuency can be as high as three times the carrier freuency if at every referencetriangle intersection a transition occurs in all phase switching functions. At low moulation epths states with higher reunancies are selecte. At low moulation epths, as explaine earlier, only S states are being use, hence the link voltages are balance as is shown in fig. 4. Fig. 5 shows the motor an axis voltages in the stationary reference frame when the synchronous freuency is Hz an 4 Hz. As the moulation epth is increase, 35 V (V) DS V (V) 5 3 DS V (V) V (V) 3 5 QS QS 8 88 RPM Fig. 8 V s, V s at 9 an Hz operation. 8 RPM V an (V) 35 8 a (A) DC bus voltages (V) V C V C3 V C Time(ms) 5 Fig. 6 Motor phase voltage an current at 6 Hz Fig. 9 Link voltages at 9 Hz. Te (Nm) 5 V an (V) Fig. 7 Motor torue at 6 Hz rate point. S an S states are selecte as shown in fig. 5(b). n this case, link voltages can be still balance because moulation in this range can be consiere as a superposition of two moulations one using only S states an the other using only S states. For a fixe 'gear ratio', as the synchronous freuency increases at constant V/Hz the current THD improves significantly because the motor leakage reactance is better able to filter the currents. This results in reuce phase current THD (4.4%) at the rate point of the motor as shown in fig. 6. Motor torue at this operating point is trace in fig. 7 which suggests a peak to peak torue of about %. The inverter operates at the limits of its voltage capability while retaining four level inverter operation when m a ³.75 (approx.). Scant use is mae of S 3, S 3 or S 3 states as seen in fig. 8(a) where the synchronous freuency is 9 Hz an the motor prouces 8Nm torue (fiel weakening). Link voltages are still balance as shown in fig. 9. The inuction motor leakage reactance now filters the current further so that the current THD stays low (5.%) even when the carrier a (A) V 5 A V an a Fig. Motor phase current an voltage at 9 Hz. 5A 4 5V Fig. Motor phase voltage an current at Hz. freuency is roppe (fig. ).. Finally, fig. shows the motor phase an current uner no loa conitions when the inverter synchronous freuency is Hz. As seen in fig. 8(b), the inverter moulation makes use of the outermost states (S 3, S 3, S 3 ) since the moulation epth is high (»

7 .33). Also at no loa, the motor impeance is preominantly inuctive so that cosf». Hence, in accorance with ()(3), < C > = < C > = < C3 >» an so the link voltages stay balance. This is reflecte in fig. showing the well regulate DC link voltages. Although the four level inverter cannot satisfactorily balance capacitor voltages for m a ³.75 an eliver real power to the loa, in applications wherein higher voltages are reuire, the inverter can be mae to operate in the two level moe i.e. selecting only S 3 states thereby traing off voltage THD for funamental voltage magnitue. DC bus voltages (V) V C V C3 V C Fig. DC link capacitor voltages at no loa an Hz. [6] T. Takeshita, N. Matsui, "PWM Control an nput Characteristics of Three Phase Multilevel AC/DC Converters", Proc. EEEPESC '9 Conf., pp [7] Y. Zhao, Y. Li, an T. A. Lipo, "Force Commutate Three Level Boost Type Rectifier", EEE Trans. on n. App., Vol. 3, no., Jan./Feb. 995, pp [8] Michael Klabune, Yifan Zhao, T.A. Lipo, " Current Control of a 3 Level Rectifier/nverter Drive System", Proc. EEEAS '94 Conf., pp [9] Gautam Sinha, T.A. Lipo, "A Four Level Rectifiernverter System for Drive Applications", Proc. EEEAS '96 Conf., pp [] Clark Hochgraf, R.H. Lasseter, D.M. Divan, T.A. Lipo, ÒComparison of Multilevel nverters for Static Var Compensation", Proc. EEEAS '94 Conf., pp [] F.Z. Peng, J.S. Lai, ÒA Multilevel VoltageSource nverter With Separate DC Sources", Proc. EEEAS '95 Conf., pp [] Gautam Sinha, T.A. Lipo, "Rectifier Current Regulation in Four Level Drives", Proc. EEEAPEC '97 Conf., pp.. [3] G. Carrara, S. Garella, M. Marchesoni, R. Salutari, G. Sciutto, "A New Multilevel PWM Metho: A Theoretical Analysis", Proc. EEEPESC '9 Conf., pp [4] M. Fracchia, T. Ghiara, M. Marchesoni, M. Mazzucchelli, "Optimize Moulation Techniues for the Generalize N Level Converter", Proc. EEEPESC '9 Conf., pp V. CONCLUSONS Four level inverters base rives with a ioe rectifier front en offer the prospect of reuce total kva ratings. A new methoology for viewing concurrent link voltage balancing an inverter moulation was iscusse. t is possible to obtain low THD voltage waveforms from the four level inverter while retaining aeuate link voltage balancing capability. This makes such rives suitable for applications wherein low spee operation is the ominant moe of operation. The voltage THD can be lowere at lower average evice switching freuencies. Time omain simulations inicate that the control scheme for link voltage balancing outline earlier are viable over the entire motoring region. f necessary, the voltage capability of the four level inverter can be improve by reverting the moulation to a conventional two level scheme. REFERENCES [] A. Nabae,. Takahashi, H. Akagi, "A New Neutral Point Clampe PWM nverter", EEE Trans. on n. App., Vol. A 7, No. 5, September/October 98, pp [] J.K. Steinke, "Control Strategy for a Three Phase AC Traction Drive with Three Level GTO PWM nverter", Proc. EEE PESC '88 Conf., pp [3] Jie Zhang, "High Performance Control of a 3 Level GBT nverter Fe AC Drive", Proc. EEEAS '95 Conf., pp. 8 [4] Satoshi Ogasawara, Hirofumi Akagi, "A Vector Control System Using a NeutralPointClampe Voltage Source PWM nverter", Proc. EEEAS '9 Conf., pp [5] A. Nabae, S. Ogasawara, H. Akagi, "A Novel Control Scheme for Current Controlle PWM nverters", EEE Trans. on n. App., Vol. A, No. 4, July/Aug., '8, pp