Research on Real-time Multi-rate Simulation of High Frequency Converter

Transcription

1 International Forum on Energy, Environment Science and Material (IFEESM 215) Reearch on Real-time Multi-rate Simulation o High Frequency Converter ZhiGuo ZHOU1, a*, MingXin ZHANG1,b RuLiang Lin2,c and Yi Zhang3,d 1 School o Inormation and Electronic, Beijing Intitute o Technology, Beijing 181, China 2 Beijing Aeropace Wanyuan Science&Technology Corporation, Beijing 1176,China 3 State Grid Fujian Electric Power Reearch Intitute, Fujian 357,China a* zhiguozhou@bit.edu.cn, b @qq.com, cjklrl@qq.com, czhangyilcu@163.com Keyword:real-time multi-rate imulation; high requency converter; co-imulation; witching-unction approach; the tate pace method; power electronic Abtract. In order to olve the problem that imulation accuracy and imulation lexibility i diicult to take into account in real-time imulation o high requency converter, a real-time multi-rate imulation method baed on FPGA+PC i propoed. Thi method ully demontrated the imulation principle o multi-rate co-imulation ytem and modeling method, and the proce o hardware architecture deign implementation. In thi paper, a high requency two level voltage ource converter i elected or real-time multi-rate imulation tet. Take o-line accurate imulation reult a benchmark, we demontrated comparion o imulation waveorm, imulation error and imulation error between multi-rate co-imulation platorm and PC real-time imulation platorm. The reult how the validity o thi multi-rate real-time imulation platorm. Introduction In recent year, the development o renewable energy uch a wind energy, high requency converter which can reduce the harmonic ditortion and the ue o power ilter, ha become the maintream o the uture power grid[1-2]. Thi make the power real time imulation or high requency converter ytem become more and more important in the development, teting, engineering deign and other ield[3]. But the development o the high requency converter technology ha brought the challenge o the power electronic real-time imulation. On the one hand, In the ield o automation, indutrial electronic, marine, aeropace propulion, the typical power electronic converter witching requency i 1-2KHz[3-4]. To guarantee the accuracy o the imulation, the power imulation tep i uually required in the power witch cycle o 1/2, requiring nanoecond imulation tep[3]. On the other hand, it i alo needed to have a lexible modeling capability in real-time imulation o controller. At preent, the typical power imulation platorm baed on multi-pc or multi-dsp can reach only a ew microecond[3,5-6], while FPGA which ha high parallel proceing capability and the nanoecond range imulation potential are conidered a the mot promiing reearch direction o power real time imulation[3,7]. The imulation platorm baed on FPGA and DSP i much le lexible in modeling than PC baed imulation platorm. In 24, Pekarek Steven propoed an o-line multi-rate imulation method which combine variable tep with ixed tep[8]. In 29, Tohiji Kato propoed the power electronic multi-rate analyi method or circuit partitioning[9]. Roy Crobie applie real time multi-rate imulation method in hip power[1]. Multi-rate co-imulation baed on multi-proceor i the development trend o power electronic real time imulation platorm. On the bai o the above reearch, thi paper applie the multi-rate imulation method to the real-time multi-rate co-imulation platorm baed on FPGA and PC. In the practical high requency converter ytem, the requency repone o the controller part i relatively low (the ampling period i 1u to m), and the requency repone o the power electronic circuit i ater (1-2kHz)[5]. Thereore, in thi paper, the low repone part uch a controller are imulated by PC, and the imulation o power electronic circuit i completed by FPGA The author - Publihed by Atlanti Pre 676

2 International Forum on Energy, Environment Science and Material (IFEESM 215) Platorm architecture and deign implementation Multi-rate imulation principle and ytem deign.for the imulation ytem, the mot undamental problem i how to model and how to ue integral olution method. In power ytem tranient imulation modeling, the node analyi method and the tate pace method are two main direction, and the tate pace method i widely ued in FPGA real-time imulation. In the integral olution, the ixed tep integration method ha a relatively table calculation quantity, and can guarantee real-time perormance, the vat majority o real-time imulation uing the method. The large cale power ytem including the high requency converter and other witching device include the low repone control part and the at repone circuit. In order to improve the eiciency and lexibility, thi paper ue the multi-rate ixed tep tate pace method. Auming that the PC imulation tep i h, FPGA imulation tep i h. It i required that the low peed imulation tep hould be an integer multiple o the high peed imulation tep. That i: (1) h = N h N Î N The tate pace equation o the correponding multi -rate imulation ytem can be expreed a: dx d é X ù é F ( X, Y, t ) ù = ê ú ú=ê dt dt ë X û ëê F ( X, Y, t ) ûú (2) (3) Y = G ( X ), Y = G ( X ) Where X and X are the tate o high-peed and low peed ubytem. Y and Y are coupling term o high peed and low peed ytem. Whatever the integral olution, it can be written a ormula (4) (5). X (t m +1 ) = p -1 åa X ( t ) + i i = p -1 h (4) å b F ( X ( t ), Y ( t ), t ) i i =-1 ( ) ki r ( ) åa k = F ( X (t ) + h å l k, Y (t + m h ), t + m h ) X tm +1 = X tm + h i i i =1 m m p ij j =1 i m (5) j i Here h and h are high-peed and low peed imulation tep, t m and tm ( m =,1,L) are the ampling time o high-peed and low peed ubytem. When the change o X i much ater than X, it can be et to h = h. By ormula (3), we can calculate the amount o the coupling in each ubytem, and bringing into the ormula (4) (5) to calculate the update value o the tate variable. However, in the real time imulation o high peed ytem and low peed ytem, the ampling rate o the coupling term original data i not conitent with the ampling rate o the tate variable to be olved.so it i neceary to convert rate o coupling term. The paper[13] preent a converion method o coupling term ample rate between dierent rate ubytem in multi-rate imulation hown in igure 1. By h tep ampling and irt order, the low ubytem output Y i tranormed into U,entering at ubytem. By the dynamic mean, h tep ampling and zero order holder,the output Y o the at ubytem i tranormed into U,entering low ytem. The converion error E1 and E2 are introduced into the proce The author - Publihed by Atlanti Pre 677

3 International Forum on Energy, Environment Science and Material (IFEESM 215) Fig. 1 Diagram o data tranmiion between ubytem in multi-rate imulation The paper[13] proved that the converion error brought by the multi-rate imulation method i convergence and very mall when the coupling term amount o interaction between the ubytem i linear, which can meet the demand o the power imulation accuracy. Thi pape combine the multi-rate imulation method with real-time high requency converter ytem imulation application baed on the above imulation theory. The low ubytem i imulated by PC. The at ubytem o power electronic circuit i imulated by FPGA imulation card. Two ubytem orm real-time multi-rate co-imulation. Simulation platorm architecture i hown in igure 2. PC ue indutrial control computer running QNX real-time operating ytem. FPGA ue the ML65, 1MHZ imulation ytem clock requency. Fig. 2 Architecture o FPGA and PC real-time multi-rate co-imulation platorm Clock ynchronization. To carry out FPGA and PC co-imulation, the irt premie i that the FPGA imulation and PC imulation proce have a uniied real-time imulation clock. Thi paper take FPGA a the main control unit o the imulation clock, and FPGA timer generate the correponding imulation clock to the FPGA olver and PC. When the counter o the FPGA low peed part tep reach the et value, the PCIe bu through the TLP meage to the PC peciied memory location to write a time tamp. When the PC detected the time tamp, tarting a tep imulation calculation. Thi ynchronization method can enure that the FPGA and PC are only a ew hundred n tep trigger error, and thi error i relatively table. The imulation tep jitter controlled by thi method i mall enough to meet the requirement o PC high peed real-time imulation. Simulation data interaction. The PC and FPGA co-imulation alo need to be able to complete the real-time data exchange o multi-rate imulation. According to the econd ection o the theory, rom PC to FPGA, it i rom low peed to high peed converion,by the ue o irt order hold(linear extrapolation); rom FPGA to PC,it i rom high peed to low peed converion, by the ue o dynamic mean zero order hold. Data converion eect i hown in igure The author - Publihed by Atlanti Pre 678

4 International Forum on Energy, Environment Science and Material (IFEESM 215) Fig. 3 Diagram o multi-rate imulation data tranmiion Thi part o the data exchange i baed on the PCIe bu uing high-peed data tranmiion control IP core (AXI Datamover) to achieve. A hown in Figure 4, when h i detected each time, MM2S_CMD command and S2MM_CMD command are iued by the data exchange control core to the AXI Datamover control core. The MM2S partial traner channel obtain coupling data Y o the PC imulation ub-model rom the PC hared memory area mapping rom AXI BAR. The data i paed to the irt order holder and i imported into input update regiter o the FPGA high peed ubytem imulation part. The S2MM traner channel interace obtain average value o coupling data Y rom the FPGA imulation ub-model, then write coupling data to the BAR AXI hared memory area on the PC. The data i paed to zero order hold and then enter low peed imulaton ubytem. Y U U Y T T U é X [ k + 1]ù é Adicrete ê Y [k + 1] ú = êc ë û ë dicrete Y Bdicrete ù é X [ k ]ù ê ú Ddicrete û ëu [ k ] úû Fig. 4 Diagram o multi-rate imulation data communication Cae imulation experiment and analyi o the reult Take SimPowerSytem imulation model o the three phae two level inverter cae a a benchmark, hown in Figure 5. The three phae meauring unit i inerted between the AC ide o the inverter bridge and the tranormer Yg terminal to oberve the phae voltage and line current. Set SPWM wave carrier requency 1kHz, the modulation ratio 1. Set imulation tep.5u. The cae i compoed o PC control ub-model, FPGA nonlinear ub-model and FPGA linear ub-model in mulit-rate co-imulation plateprm. Invoking the power_analyze unction, we can convert the linear circuit model to the tate pace equation: 215. The author - Publihed by Atlanti Pre 679

5 International Forum on Energy, Environment Science and Material (IFEESM 215) é. ù éa Bù éx ù êx ú = ê ú ê ú êëy úû ëc D û ëu û (6) i the ytem tate, Y i the ytem output, U i the input o the ytem. The tate pace equation i dicretized by uing the trapezoidal method: X é X [k + 1]ù é Adicrete ê Y [ k + 1] ú = êc ë û ë dicrete Bdicrete ù é X [k ]ù Ddicrete ûú êëu [k ] úû (7) A hown in Figure 5, the nonlinear olver and the linear olver are parallel computing.the input o nonlinet olver i obtained rom the output vector Y o the linear olver, and the output o the nonlinear olver i ed back to the input vector o U the linear olver. In the FPGA imulation board, olving proce o linear circuithe linear i matrix multiplication vector operation hown a (7) in each imulation tep. PC i ued to imulate the control model which generate modulating ignal. Fig. 5 Diagram o three phae two level inverter cae In the multi-rate co-imulation, the control imulation ub-model adopt 1u imulation tep in PC, and the power electronic circuit part (including linear and nonlinear Solver) adopt.5u imulation tep in ML65 FPGA board. Multi-rate co-imulation, SimPowerSytem imulation benchmark and PC real-time imulation (1u) are compared with the reult o Figure 6, 7. Figure 6 i comparion o imulation reult in load phae AB, Figure 7 i the comparion o imulation reult in inverter phae A current. It can be een that the multi-rate co-imulation reult are conitent with the imulation reult, and the PC real-time imulation reult i in large error. Vloadab 6 协同仿真 SimPowerSytem PC实 时 仿 真 4 U/v t/ Fig. 6 Comparion o imulation reult in load phae AB voltage 215. The author - Publihed by Atlanti Pre 68

6 International Forum on Energy, Environment Science and Material (IFEESM 215) Iinva I/A 1 协同仿真 SimPowerSytem PC实 时 仿 真 x t/ Fig. 7 Comparion o imulation reult in inverter phae A current Concluion The FPGA and PC mulit-rate co-imulation platorm deigned by thi paper can carry out analyi o the high requency converter ytem eiciently and in real time. In the imulation tet, it can be een rom the comparion o the imulation waveorm: the imulation accuracy o thi platorm ha a great improvement compared with the PC real-time imulation platorm, and the itting o the electromagnetic tranient i more accurate, and the error i about 1%. Thi imulation platorm ha important igniicance in the power ytem analyi, epecially in the micro grid teting, analyi and other engineering application. Reerence [1] Hartmann M, Round S D, Ertl H: IEEE Tranaction on Power Electronic, 29, vol.24(29), pp [2] Zheng Xu, Hairong Chen: High Voltage Engineering, 27, vol.33(27), pp.1-1(in chinee) [3] Blanchette H F, Ould-Bachir T, David J P: IEEE Tranaction on Indutrial Electronic, vol.59(212), pp [4] Blanchette H F, Ould-Bachir T, David J P: IET Power Electronic, vol.4(211), pp [5] Chang G W, Yu-Jen Liu, Dinavahi V: IEEE Tranaction on Indutrial Electronic, vol.57(21), pp [6] R Crobie: Proceeding o IEEE ESTS, Baltimore MD, USA, 29. [7] Yuan Chen, Dinavahi V: IEEE Tranaction on Indutrial Electronic, vol.58(211), pp [8] Pekarek S, Waynczuk O, Walter E: IEEE Tranaction on Power Sytem, vol.19(24), pp [9] Kato T, Inoue K, Fukutani T: IEEE Tranaction on Power Electronic, vol.24(29), pp [1] Crobie R E, Zenor J J, Word D:Proceeding o IEEE Electric Ship Technologie Sympoium, Alexandria VA, USA, 211, pp The author - Publihed by Atlanti Pre 681