PI90LV031A. 3V LVDS High-Speed Differential Line Drivers. Description. Features. Applications PI90LV027A PI90LV031A PI90LV017A
|
|
|
- Shona Jacobs
- 5 years ago
- Views:
Transcription
1 P90LV03A P90LV027A P90LV07A 3V LVDS High-Speed Differential Line Drivers Features Signaling Rates >400Mbps (200 MHz) Single 3.3V Power Supply Design ±350mV Differential Swing Maximum Differential Skew of 0.4ns Maximum Propagation Delay of 2.0ns Maximum Power Dissipation: 200 MHz/driver Low Voltage TTL (LVTTL) s ndustrial Temperature Operating Range: -40 C to 5 C Meets or Exceeds EEE SC LVDS Standard Meets or Exceeds ANS/TA/EA-644 LVDS Standard Packaging (Pb-free & Green available): P90LV07A & P90LV027A - -pin SOC (W) - -pin MSOP (U) P90LV03A - 6-pin SOC (W) - 6-pin TSSOP (L) Description The P90LV03A, P90LV027A, and P90LV07A are differential line drivers that use low-voltage differential signaling (LVDS) to support data rates in excess of 400 Mbps. These products are designed for applications requiring high-speed, low-power consumption and low noise generation. A low voltage TTL/CMOS input level is translated by the device into a low-voltage (350mV) differential output signal. Exclusive to the P90LV03A quad driver is a power-down mode that 3-states the outputs and places the device in a low-power idle state (3mW typical). Applications Applications include point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 00 ohms. The transmission media can be printed circuit board traces, backplanes, or cables. The P90LV03A, P90LV027A, P90LV07A and companion line receivers (P90LV032A, P90LV02A, and P90LV0A) provide new alternatives to RS-232, PECL, and ECL devices for high-speed, point-to-point interface applications. P90LV027A P90LV03A VCC DN DN Pin U,W DN DN2 D D2 DOUT- DOUT+ DOUT2+ DOUT2- DOUT+ DOUT- DOUT2+ DOUT2- EN DOUT3- DOUT3+ DN3 DN DOUT+ DOUT- DOUT2- DOUT2+ DN Pin L,W EN* VCC DN4 DOUT4+ DOUT4- P90LV07A VCC D NC Pin U,W D NC NC PS422B 09/5/04
2 Function Tables P90LV03A EN Enables EN npu t Output s D OUT + D OUT H X H H L H X L L H X L H H L X L L L H Pin Descriptions Name D O+ D O Descriptio n TTL/CMOS driver input pins Non-inverting driver output pins nverting driver output pins Ground pin V C C Positive power supply pin, +3.3V ±0% L H X Z Z P90LV027A Recommended Operating Conditions Output s M in. T yp. Max. Units P90LV07A D OUT+ DOUT- H H L L L H Output s D OUT+ DOUT- H H L L L H Supply Voltage ( VC C) Operating Free Air Temperature V C Absolute Maximum Ratings (see Note, Page 4) Supply Voltage (V CC ) V to +4.0V Voltage ( ) V to (V CC +0.3V) Enable Voltage (EN, EN*) V to (V CC +0.3V) Output Voltage (D OUT+, D OUT- ) V to +3.9V Short Circuit Duration (D OUT+, D OUT- )... Continuous S Package mW Derate S Package....5mW/ C above +25 C Storage Temperature Range C to +50 C Lead Temperature Range Soldering (4s) C Maximum Junction Temperature C ESD Rating... 6kV Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 PS422B 09/5/04
3 Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2,3,4) Symbol Paramete r Condition s P in M in. T yp. Max. Units V OD V OD Differential Output Voltag e Change in Magnitude of VOD for Complementary Output States mv 4 35 mv V OS V OS V OH Offset Voltag e V DOUT- R L = 00Ω (Fig. ) Change in Magnitude of VOS for D OUT mv Complementary Output States Output Voltage High.3. 6 V OL V H Output Voltage Low Voltage High 2.0 V CC V V L H L Voltage Low Current Current V N V N D N E N 0. = VCC or 2.5V -0 ± +0 = or 0.4V E N* -0 ± +0 µa V CL OS OSD OFF OZ CC CCL CCZ Clamp Voltag e Output Short Circuit Current Differential Output Short Circuit Current Power-off Leakage Output Three-State Current No Load Supply Current Drivers Enabled Loaded Supply Current Drivers Enabled No Load Supply Current Drivers Disabled CL = -ma V E NABLED, (0) VC, DOUT+ = 0V or, D = 0V = C = OUT- ENABLED, V V OD = 0V O UT = 0V or 3.6V, V CC = 0V or Open (0) EN = 0.V and EN* = 2.0V V 0V or V O UT = CC = VCC or R L = 00Ω All Channels, V or (all inputs = C C ) = VC C or, EN =, EN* = V CC DOUT- D OUT+ V CC ± ± ma µa ma 3 PS422B 09/5/04
4 Switching Characteristics V CC = +3.3V ±0%, T A = -40 C to +5 C (Notes 3,9,) Symbol Paramete r C ondition s M in. T yp. Max. Units tphld Differential Propagation Delay High to Low tplhd tskd tskd2 tskd3 tskd4 ttlh tthl tphz tplz tpzh tpzl Differential Propagation Delay Low to High Differential Pulse Skew tphld t - PLHD 5) ( C hannel-to-channel Skew( 6) RL = 00Ω, (7) Differential Part-to-Part Skew CL = 0pF (Figures 2 & 3) 0. 0 ( ) D ifferential Part-to-Part Skew 0. 2 Rise Tim e Fall Tim e Disable Time High to Z Disable Time Low to Z RL = 00Ω, 5 CL = 0pF Enable Time Z to High (Figures 4 & 5) 7 Enable Time Z to Low 7 5 ns tmax M aximum Operating Frequenc y 3) ( MHz Notes:. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. 2. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V OD and V OD. 3. All typicals are given for: V CC = +3.3V, T A = +25 C. 4. The P90LV03A/P90LV027A/P90LV07A are current mode devices and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90Ω to 0Ω). 5. tskd, tphld - tplhd is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 6. tskd2 is the Differential Channel-to-Channel Skew of any event on the same device. 7. tskd3, Differential Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same Vcc and with 5 C of each other within the operating temperature range.. tskd4, Part-to-Part Skew, is the differential Channel-to-Channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tskd4 is defined as Max - Min differential propagation delay. 9. Generator waveform for all tests unless otherwise specified: f = MHz, ZO = 50Ω, tr ns, and t f ns. 0. Output short circuit current ( OS ) is specified as magnitude only, minus sign indicates direction only.. C L includes probe and jig capacitance. 2. All input voltages are for one channel unless otherwise specified. Other inputs are set to. 3. fmax generator input conditions: t R = t F < ns, (0% to 00%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, V OD > 250mV, all channels switching. 4 PS422B 09/5/04
5 Parameter Measurement nformation D OUT+ R L /2 V CC S DN D R L /2 V OS V OD Driver ENABLED D OUT- Figure. Driver V OD and V OS Test Circuit Figure 2. Driver Propagation Delay and Transition Time Test Circuit 5 PS422B 09/5/04
6 Figure 3. Driver Propagation Delay and Transition Time Waveforms Figure 4. Driver Three-State Delay Test Circuit 6 PS422B 09/5/04
7 Figure 5. Driver 3-State Delay Waveform Figure 6. Point-to-Point Application 7 PS422B 09/5/04
8 Packaging Mechanical: 6-Pin SOC (W) x REF SEATNG PLANE BSC DENOTES DMENSONS N MLLMETERS Packaging Mechanical: -Pin SOC (W) x REF SEATNG PLANE BSC DENOTES DMENSONS N MLLMETERS PS422B 09/5/04
9 Packaging Mechanical: 6-Pin TSSOP (L) max..20 SEATNG PLANE BSC BSC DENOTES CONTROLLNG DMENSONS N MLLMETERS Packaging Mechanical: -pin MSOP (U) Gauge Plane.00 5 Max Max REF Detail A MAX Detail A MAX PS422B 09/5/04
10 Ordering nformation Ordering Code Package Code Package Description P90LV07AW W -pin SOC P90LV07AWE W Pb-free & Green, -pin SOC P90LV07AU U -pin MSOP P90LV07AUE U Pb-free & Green, -pin MSOP P90LV027AW W -pin SOC P90LV027AWE W Pb-free & Green, -pin SOC P90LV027AU U -pin MSOP P90LV027AUE U Pb-free & Green, -pin MSOP P90LV03AW W 6-pin SOC P90LV03AWE W Pb-free & Green, 6-pin SOC P90LV03AL L 6-pin TSSOP P90LV03ALE L Pb-free & Green, 6-pin TSSOP Notes:. Thermal characteristics can be found on the company web site at Pericom Semiconductor Corporation PS422B 09/5/04
PI90LV031A PI90LV027A PI90LV017A. 3V LVDS High-Speed Differential Line Drivers. Description. Features PI90LV027A PI90LV031A PI90LV017A
PI90LV03A PI90LV027A PI90LV07A 3V LVDS High-Speed Differential Line Drivers Features Signaling Rates >400Mbps (200 MHz) Single 3.3V Power Supply Design ±30mV Differential Swing Maximum Differential Skew
3V LVDS Quad Flow-Through Differential Line Driver. Features. Description. Block Diagram. Pin Configuration. Truth Table
Features >00 Mbps (20 MHz) switching rates Flow-through pinout simplifies PCB layout Low Voltage Differential Signaling with output voltages of ±30mV into: 00-ohm load (P90LV04) 300ps typical differential
Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663
Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 FEATURES ±15 kv ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential
Single, 3 V, CMOS, LVDS Differential Line Receiver ADN4662
Data Sheet FEATURES ±15 kv ESD protection on input pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 2.5 ns maximum propagation delay 3.3 V power supply High impedance outputs
3 V, LVDS, Quad, CMOS Differential Line Driver ADN4665
3 V, LVDS, Quad, CMOS Differential Line Driver ADN4665 FEATURES ±15 kv ESD protection on output pins 400 Mbps (200 MHz) switching rates 100 ps typical differential skew 400 ps maximum differential skew
Dual, 3 V, CMOS, LVDS Differential Line Receiver ADN4664
Dual, 3 V, CMOS, LVDS Differential Line Receiver ADN4664 FEATURES ±15 kv ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 100 ps channel-to-channel
3 V, LVDS, Quad CMOS Differential Line Receiver ADN4666
3 V, LVDS, Quad CMOS Differential Line Receiver ADN4666 FEATURES ±8 kv ESD IEC 6000-4-2 contact discharge on receiver input pins 400 Mbps (200 MHz) switching rates 00 ps channel-to-channel skew (typical)
3 V LVDS Quad CMOS Differential Line Driver ADN4667
FEATURES ±15 kv ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum
3 V LVDS Quad CMOS Differential Line Receiver ADN4668
3 V LVDS Quad CMOS Differential Line Receiver ADN4668 FEATURES ±5 kv ESD protection on receiver input pins 400 Mbps (200 MHz) switching rates Flow-through pin configuration simplifies PCB layout 50 ps
LVTTL/LVCMOS DATA INPUT 100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES. Maxim Integrated Products 1
19-1991; Rev ; 4/1 EVALUATION KIT AVAILABLE General Description The quad low-voltage differential signaling (LVDS) line driver is ideal for applications requiring high data rates, low power, and low noise.
DS90LV017A LVDS Single High Speed Differential Driver
DS90LV017A LVDS Single High Speed Differential Driver General Description The DS90LV017A is a single LVDS driver device optimized for high data rate and low power applications. The DS90LV017A is a current
UT54LVDM031LV Low Voltage Bus-LVDS Quad Driver Data Sheet September, 2015
Standard Products UT54LVDM031LV Low Voltage Bus-LVDS Quad Driver Data Sheet September, 2015 The most important thing we build is trust FEATURES >400.0 Mbps (200 MHz) switching rates +340mV nominal differential
LVTTL/CMOS DATA INPUT 100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES. Maxim Integrated Products 1
19-1927; Rev ; 2/1 Quad LVDS Line Driver with General Description The quad low-voltage differential signaling (LVDS) differential line driver is ideal for applications requiring high data rates, low power,
UT54LVDS031 Quad Driver Data Sheet September,
Standard Products UT54LVDS031 Quad Driver Data Sheet September, 2012 www.aeroflex.com/lvds FEATURES >155.5 Mbps (77.7 MHz) switching rates +340mV nominal differential signaling 5 V power supply TTL compatible
DS90C031 LVDS Quad CMOS Differential Line Driver
DS90C031 LVDS Quad CMOS Differential Line Driver General Description The DS90C031 is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates.
DS90C032B LVDS Quad CMOS Differential Line Receiver
LVDS Quad CMOS Differential Line Receiver General Description TheDS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
FIN1108 LVDS 8-Port, High-Speed Repeater
Features Greater than 800Mbps Data Rate 3.3V Power Supply Operation 3.5ps Maximum Random Jitter and 135ps Maximum Deterministic Jitter Wide Rail-to-rail Common Mode Range LVDS Receiver Inputs Accept LVPECL,
TOP VIEW. Maxim Integrated Products 1
19-2213; Rev 0; 10/01 Low-Jitter, Low-Noise LVDS General Description The is a low-voltage differential signaling (LVDS) repeater, which accepts a single LVDS input and duplicates the signal at a single
TOP VIEW MAX9111 MAX9111
19-1815; Rev 1; 3/09 EVALUATION KIT AVAILABLE Low-Jitter, 10-Port LVDS Repeater General Description The low-jitter, 10-port, low-voltage differential signaling (LVDS) repeater is designed for applications
UT54LVDS032 Quad Receiver Advanced Data Sheet
Standard Products UT54LVDS032 Quad Receiver Advanced Data Sheet December 22,1999 FEATURES >155.5 Mbps (77.7 MHz) switching rates +340mV differential signaling 5 V power supply Ultra low power CMOS technology
PI5C3384 PI5C3384C. 10-Bit, 2-Port Bus Switch
PI5C3384 PI5C3384C 0-Bit, 2-Port Bus Switch Features: Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra-low quiescent power (0.2μA typical)
ILX485. Low-Power, RS-485/RS-422 Transceivers TECHNICAL DATA
TECHNICAL DATA Low-Power, RS-485/RS-422 Transceivers ILX485 Description The ILX485 is low-power transceivers for RS-485 and RS- 422 communication. IC contains one driver and one receiver. The driver slew
FIN1532 5V LVDS 4-Bit High Speed Differential Receiver
FIN1532 5V LVDS 4-Bit High Speed Differential Receiver General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The
DS90C032 LVDS Quad CMOS Differential Line Receiver
DS90C032 LVDS Quad CMOS Differential Line Receiver General Description TheDS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data
MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER
Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
PI3CH360. Low Voltage, High-Bandwidth, 3-Channel 2:1 Mux/DeMux, NanoSwitch. Features. Description. Block Diagram. Pin Configuration.
Low Voltage, High-Bandwidth, 3-Channel 2:1 Features Near-Zero propagation delay 5Ω switches connect inputs to outputs High signal passing bandwidth (500 MHz) Beyond Rail-to-Rail switching 5V I/O tolerant
800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switch
19-2003; Rev 0; 4/01 General Description The 2 x 2 crosspoint switch is designed for applications requiring high speed, low power, and lownoise signal distribution. This device includes two LVDS/LVPECL
PI5C3253. Dual 4:1 Mux/DeMux Bus Switch
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON ESD Protection up to 2kV HBM Ultra Low Quiescent Power (0.2μA typical) Ideally suited
Description. Table 1. Device summary. Reference SMD pin Quality level Package Lead finish Mass EPPL (1) Engineering model
Rad-hard quad LVDS driver Datasheet - production data Guaranteed up to 300 krad TID SEL immune up to 135 MeV.cm²/mg SET/SEU immune up to 67 MeV.cm²/mg Description Features Ceramic Flat-16 The upper metallic
SPLVDS032RH. Quad LVDS Line Receiver with Extended Common Mode FEATURES DESCRIPTION PIN DIAGRAM. Preliminary Datasheet June
FEATURES DESCRIPTION DC to 400 Mbps / 200 MHz low noise, low skew, low power operation - 400 ps (max) channel-to-channel skew - 300 ps (max) pulse skew - 7 ma (max) power supply current LVDS inputs conform
Description IA 3 IA 2 IA 1 GND. Truth Table (1) H X X Hi-Z Disable S 0-1. L L L I0 S1-0 = 0 L L H I1 S1-0 = 1 Y A to Y B
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs High signal passing bandwidth (300MHz) Beyond Rail-to-Rail switching 5V I/O tolerant with 3.3V supply 2.5V and 3.3V supply voltage
FIN V LVDS High Speed Differential Driver/Receiver
April 2001 Revised September 2001 FIN1019 3.3V LVDS High Speed Differential Driver/Receiver General Description This driver and receiver pair are designed for high speed interconnects utilizing Low Voltage
PI3C V/3.3V, High Bandwidth, Hot Insertion 10-Bit, 2-Port, Bus Switch
2.5V/3., High Bandwidth, Hot Insertion Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth (>400 MHz) Permits Hot Insertion. Rail-to-Rail, 3. or 2.5V ing 5V I/O
PI5C16861 PI5C (25Ω) 20-Bit, 2-Port Bus Switch
PI5C8 PI5C28 (25Ω) Features Near-Zero propagation delay 5Ω or 25Ω switches connect inputs to outputs Direct bus connection when switches are ON 32X384 function with flow through pinout make board layout
Quad LVDS Line Receiver with Flow-Through Pinout and In-Path Fail-Safe
19-2595; Rev 0; 10/02 Quad LVDS Line Receiver with Flow-Through General Description The quad low-voltage differential signaling (LVDS) line receiver is ideal for applications requiring high data rates,
PI5C3253. Dual 4:1 Mux/DeMux Bus Switch
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra Low Quiescent Power (0.2µA typical) Ideally suited for notebook applications
PI3HDMI412-B. 4-Differential Channel, 2:1 Mux/DeMux, DVI/HDMI Compliant Signal Switch based on TMDS Signaling Standard
Compliant Signal Switch based on TMDS Signaling Standard Features 3.3V 4-Differential Channel 2:1 Mux/DeMux DVI, HDMI, 1.2 +1.2 signal compatible Data Rate: 1.65Gbps Supports both AC coupled and DC coupled
Single/Dual LVDS Line Receivers with In-Path Fail-Safe
9-2578; Rev 2; 6/07 Single/Dual LVDS Line Receivers with General Description The single/dual low-voltage differential signaling (LVDS) receivers are designed for high-speed applications requiring minimum
PL High Speed Translator Buffer to LVDS FEATURES PIN CONFIGURATION
FEATURES Differential output Single AC coupled input (min. 100mV swing). Input range from 0 to 1.0GHz. 2.5V to 3.3V operation. Available in 8-Pin SOP or 3x3mm QFN GREEN/RoHS compliant packaging. PIN CONFIGURATION
PI3V514. Low On-Resistance, 3.3V High-Bandwidth 5-port, 4:1 Mux/DeMux VideoSwitch. Description. Features. Pin Configuration.
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs High signal passing bandwidth (400 MHz) Beyond Rail-to-Rail switching 5V I/O tolerant with 3.3V supply 2.5V and 3.3V supply voltage
UT54LVDM055LV Dual Driver and Receiver Data Sheet June, 2016
Standard Products UT54LVDM055LV Dual Driver and Receiver Data Sheet June, 2016 The most important thing we build is trust FEATURES INTRODUCTION Two drivers and two receivers with individual enables >400.0
UT54LVDS032 Quad Receiver Data Sheet September 2015
Standard Products UT54LVDS032 Quad Receiver Data Sheet September 2015 The most important thing we build is trust FEATURES INTRODUCTION >155.5 Mbps (77.7 MHz) switching rates +340mV nominal differential
PI90LV01/PI90LVB01. Features ÎMeets Î or Exceeds ANSI TIA/EIA Standard ÎSignaling Î rates up to 660 Mbps
SOTiny LVDS High-Speed Differential Line Driver Features ÎMeets Î or Exceeds ANSI TIA/EIA-644-1955 Standard ÎSignaling Î rates up to 660 Mbps ÎBus-Terminal Î ESD exceeds 2kV ÎLow-Voltage Î Differential
PI2DBS GHz, Differential Broadband Signal Switch, 2-Differential Channel, 2:1 Mux/DeMux Switch
Features SAS, SATA2, XAUI Switch 2 Differential Channel, 2:1 Mux/DeMux Bandwidth of 2.0 GHz (3dB) Low Bit-to-Bit Skew :
UT54LVDS032LV/E Low Voltage Quad Receiver Data Sheet October, 2017
Standard Products UT54LVDS032LV/E Low Voltage Quad Receiver Data Sheet October, 2017 The most important thing we build is trust FEATURES >400.0 Mbps (200 MHz) switching rates +340mV differential signaling
SN75174 QUADRUPLE DIFFERENTIAL LINE DRIVER
SN Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and RS-8 and ITU Recommendation V.. Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments -State s Common-Mode Voltage
PI3C V/3.3V, High Bandwidth, Hot Insertion 8-Bit, 2-Port, Bus Switch. Description. Features. Pin Configuration. Block Diagram.
Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth Operation (>400 MHz) Permits Hot Insertion 5V I/O Tolerant Rail-to-Rail 3.3V or 2.5V Switching 2.5V Supply Voltage
PI3USB10LP-A. USB 2.0 High-Speed (480 Mbps) Signal Switch Targeted for Battery Powered Applications. Description. Features.
Features USB 2.0 compliant (high speed and full speed) R ON is 5.5Ω typical @ V CC = 3.0V Low bit-to-bit skew Low Crosstalk: 40dB @ 500 Mbps Off Isolation: 35dB @ 500 Mbps Near-Zero propagation delay:
DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver
DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver General Description The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and
! Flow-Through Pinout. ! Guaranteed 500Mbps Data Rate. ! 300ps Pulse Skew (Max) ! Conform to ANSI TIA/EIA-644 LVDS Standards. ! Single +3.
AS1150, AS1151 Quad LVDS Receivers 1 General Description The AS1150 and AS1151 are quad flow-through LVDS (low-voltage differential signaling) receivers which accept LVDS differential inputs and convert
PI2PCIE V, PCI Express Gen2 Compliant, 4-Differential Channel, 2:1 Mux/DeMux Switch
Features 4 Differential Channel, 2:1 Mux/DeMux PCI Express, Gen 2 Performance, 5.0Gbps Low Bit-to-Bit Skew, 7ps max (between '+' and '-' bits) Low Crosstalk: -23dB@3 GHz Low Off Isolation: -23dB@3 GHz
DS96172/DS96174 RS-485/RS-422 Quad Differential Line Drivers
DS96172/DS96174 RS-485/RS-422 Quad Differential Line Drivers General Description The DS96172 and DS96174 are high speed quad differential line drivers designed to meet EIA Standard RS-485. The devices
PI5C Bit, 2-Port Bus Switch. Features. Description. Pin Configuration. Block Diagram. Pin Description. Truth Table (1) Pin Name Description
Features ÎÎNear-Zero propagation delay ÎÎ5-ohm switches connect inputs to outputs ÎÎDirect bus connection when switches are on ÎÎUltra Low Quiescent Power (0.2μA typical) Ideally suited for notebook applications
PI2PCIE2422. PCI Express Gen II Compliant, 8-Differential Channel Switch with 8:4 Mux/DeMux Option. Features. Description. Truth Table.
Features 8 Differential Channel SPST switch with Mux/DeMux option PCI Express Gen II performance Low Bit-to-Bit Skew: 10ps (between +/- signals) Low Crosstalk: -15dB @ 3.0 GHz Low Off Isolation: -26db
CARD 1 CARD 15 CARD 16. Maxim Integrated Products 1
19-2287; Rev 0; 1/02 Quad Bus LVDS Traceiver General Description The is a quad bus LVDS (BLVDS) traceiver for heavily loaded, half-duplex multipoint buses. Small 32-pin QFN and TQFP packages and flow-through
PI5C3384 PI5C3384C PI5C32384 (25Ω)
PI5C3384 PI5C3384C PI5C32384 (25Ω) 0-Bit, 2-Port Bus Switch Features: Near-Zero propagation delay Low noise, 25Ω version (PI5C32384) 5Ω switches connect inputs to outputs (PI5C3384) Direct bus connection
PI3B V, Synchronous 16-Bit to 32-Bit FET Mux/DeMux NanoSwitch. Description. Features. Pin Configuration. Block Diagram.
PI363 3.3, Synchronous 6-it to 3-it FET Mux/DeMux NanoSwitch Features Near-Zero propagation delay. Ω Switches Connect etween Two Ports Packaging: - -pin 40mil Wide Thin Plastic TSSOP (A) - -pin 300mil
PI6CL V/1.5V, 200MHz, 1:4 Networking Clock Buffer. Features. Description. Pin Description
Features High-speed, low-noise, non-inverting 1:4 buffer Maximum Frequency up to 200 MHz Low output skew < 100ps Low propagation delay < 3.5ns Optimized duty cycle 3.3 tolerent input 1.2 or 1.5 supply
LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
19-2392; Rev ; 4/2 LVDS or LVTTL/LVCMOS Input to General Description The 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists
PI5L
Wide Bandwidth Low Voltage LanSwitch Quad 2:1 Mux/Demux Features Replaces mechanical relays High-performance, low-cost solution for switching between different LAN signals Ultra-low quiescent power (0.1
CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS
Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency
±15 kv ESD protected, low-power RS-485/RS-422 transceiver. Description
±15 kv ESD protected, low-power RS-485/RS-422 transceiver Datasheet - production data Features Low quiescent current: 300 µa Designed for RS-485 interface applications - 7 V to 12 V common mode input voltage
SP3486 and SP V Low Power Quad RS-485/RS-422 Line Drivers
SP and SP RS- or RS- Quad ifferential Line rivers Operates from a single +.V supply Interoperable +.0V logic Tri-state Output Control -V to +V Common-Mode Input Voltage Range Common river Enable Control
SN65LVDM31 HIGH-SPEED DIFFERENTIAL LINE DRIVER
HIH-SPEED DIFFERENTIAL LINE DRIVER Designed for Signaling Rates Up to 5 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 7 mv and a -Ω Load Propagation Delay Time of. ns, Typical
ABB3009. High Speed Translator Buffer to LVDS ABB3009 FEATURES PIN CONFIGURATION
FEATURES Differential output Single AC coupled input (min. 100mV swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. DESCRIPTION The is a low cost, high
PI5C32X384/32X384C. 20-Bit, 2-Port Bus Switch. Features. Description. Pin Configuration. Block Diagram. Pin Description
PI5C32X384/32X384C Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra-low quiescent power 32X384 (0.2µA typical) Ideally suited
LVDS/Anything-to-LVPECL/LVDS Dual Translator
19-2809; Rev 1; 10/09 LVDS/Anything-to-LVPECL/LVDS Dual Translator General Description The is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up
PI3L V Quad, 2:1 Mux/DeMux Fast Ethernet LAN Switch w/ Single Enable. Description. Features. Applications. Pin Configuration.
Features R ON is 4Ω typical Low crosstalk: 27dB @ 250 MHz Near-Zero propagation delay: 250ps Switching speed: 9ns Channel On capacitance: 9pF (typical) Operating Range: +3.0V to +3.6V >2kV ESD protection
PI3V312. Low On-Resistance, 3.3V High-Bandwidth 4-Port, 2:1 Mux/DeMux VideoSwitch. Features. Description. Block Diagram. Pin Configuration S 1 Y A 4
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs High signal passing bandwidth (500MHz) Beyond Rail-to-Rail switching 5V I/O tolerant with 3.3V supply 1.8V, 2.5V and 3.3V supply
AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER
AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output
DS91D180/DS91C180 Multipoint LVDS (M-LVDS) Line Driver/Receiver
Multipoint LVDS (M-LVDS) Line Driver/Receiver General Description The DS91D180 and DS91C180 are high-speed differential M- LVDS single drivers/receivers designed for multipoint applications with multiple
Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23
19-1803; Rev 3; 3/09 Single/Dual LVDS Line Receivers with General Description The single/dual low-voltage differential signaling (LVDS) receivers are designed for highspeed applications requiring minimum
DS36950 Quad Differential Bus Transceiver
DS36950 Quad Differential Bus Transceiver General Description The DS36950 is a low power, space-saving quad EIA-485 differential bus transceiver especially suited for high speed, parallel, multipoint,
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS34C87T CMOS Quad TRI-STATE Differential Line Driver General Description
Description. Table 1. Device summary. Reference SMD pin Quality level Package Lead finish Mass EPPL (1) Engineering model
Rad-hard quad LVDS receivers Datasheet - production data Large input common mode: -4 V to +5 V Guaranteed up to 300 krad TID SEL immune up to 135 MeV.cm²/mg SET/SEU immune up to 32 MeV.cm²/mg Description
PI5V330A. Low On-Resistance Wideband/Video Quad 2-Channel Mux/DeMux. Features: Description. Pin Diagram. Block Diagram. Pin Description.
Features: High-performance solution to switch between video sources Wide bandwidth: >360 MHz Low On-Resistance: 3Ω Low crosstalk at 0 MHz: 58dB Ultra-low quiescent power (0.µA typical) Single supply operation:
PI6ULS5V9509 Level Translating I 2 C-Bus/SMBus Repeater with Tiny Package
Features Bidirectional buffer isolates capacitance and allows 400 pf on port B of the device Port A operating supply voltage range of 1.1 V to V CC(B) - 1.0V Port B operating supply voltage range of 2.5
DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver
3V LVDS Quad CMOS Differential Line Receiver General Description The DS90LV048A is a quad CMOS flow-through differential line receiver designed for applications requiring ultra low power dissipation and
DS485 Low Power RS-485/RS-422 Multipoint Transceiver
DS485 Low Power RS-485/RS-422 Multipoint Transceiver General Description The DS485 is a low-power transceiver for RS-485 and RS-422 communication. The device contains one driver and one receiver. The drivers
SN QUADRUPLE HALF-H DRIVER
-A -Current Capability Per Driver Applications Include Half-H and Full-H Solenoid Drivers and Motor Drivers Designed for Positive-Supply Applications Wide Supply-Voltage Range of 4.5 V to 6 V TTL- and
SN75158 DUAL DIFFERENTIAL LINE DRIVER
SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup
4bit LVDS Receiver BU90LV048. LVDS Interface ICs
LVDS Interface ICs 4bit LVDS Receiver BU90LV048 Description LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits range is from 35 to 70.
Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670
Data Sheet Programmable Low Voltage 1:10 LVDS Clock Driver FEATURES FUNCTIONAL BLOCK DIAGRAM Low output skew
PI5C Bit Bus Switch with Individual Enables A 1 B 1 GND. Features. Description. Pin Configuration. Block Diagram.
2-Bit Bus Switch with Individual Enables Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra Low Quiescent Power (0.2μA typical)
DS90LV018A 3V LVDS Single CMOS Differential Line Receiver
3V LVDS Single CMOS Differential Line Receiver General Description The DS90LV018A is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise
DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver
DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver General Description The DS90C402 is a dual receiver device optimized for high data rate and low power applications. This device along with
SP26LV431 HIGH SPEED +3.3V QUAD RS-422 DIFFERENTIAL LINE DRIVER
HIGH SPEED +3.3V QUAD RS-422 DIFFERENTIAL LINE DRIVER JUNE 2011 REV. 1.1.1 GENERAL DESCRIPTION The SP26LV431 is a quad differential line driver that meets the specifications of the EIA standard RS-422
PI90LV9637. LVDS High-Speed Differential Line Receivers. Features. Description. Applications PI90LV9637
LVDS High-Speed Differenial Line Receivers Feaures Signaling Raes >400Mbps (200 MHz) Single 3.3V Power Supply Design Acceps ±350mV (ypical) Differenial Swing Maximum Differenial Skew of 0.35ns Maximum
PI3DBS V High Speed 2 : 4 Differential Mux/Demux
3.3V High Speed 2 : 4 Differential Mux/Demux Features ÎÎ2:4 Differential Multiplexer/Demultiplexer ÎÎBidirectional Operation ÎÎCan be used in à à Single :4 Configuration à à Dual :2 Configuration à à Fan
PI3VeDP212 2-lane DisplayPort Switch/Mux for DP Driven Panels with Triple Control Pins
Features 2 Differential Channel, 2:1 mux/demux that will support 2.7Gbps or 1.62Gbps DP signals 1-differential channel is used for AUX signaling Insertion Loss for high speed channels @ 2.7 Gbps: -1.5dB
MAX9177EUB -40 C to +85 C 10 µmax IN0+ INO- GND. Maxim Integrated Products 1
19-2757; Rev 0; 1/03 670MHz LVDS-to-LVDS and General Description The are 670MHz, low-jitter, lowskew 2:1 multiplexers ideal for protection switching, loopback, and clock distribution. The devices feature
DS485 Low Power RS-485/RS-422 Multipoint Transceiver
Low Power RS-485/RS-422 Multipoint Transceiver General Description The DS485 is a low-power transceiver for RS-485 and RS- 422 communication. The device contains one driver and one receiver. The drivers
PI3CH360 3-Channel 2:1 Mux/DeMux, Enable Low 1.8V/2.5V/3.3V, High-Bandwidth, Hot Plug
1.8V/2.5V/3.3V, High-Bandwidth, Hot Plug Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High signal passing bandwidth (500 MHz) Beyond Rail-to-Rail switching - 0 to 5V switching
Description D2+A D2-A D3+A D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B AUX+ A AUX- A HPD A CAB_DETA/LEDA AUX+ B AUX- B HPD B CAB_DETB/LEDB
High Bandwidth 6-differential Channel, 1:2 Demux Features 4 Differential Channel, 1:2 DeMux that will support 2.7Gbps DP rev 1.1a signals 1-channel 1:2 demux for DP_HPD signal 1-differential channel 1:2
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features F MAX = 500MHz 10 pairs of differential LVPECL outputs Low additive jitter,
PI74STX2G Bit Level Shifting Buffer/Transceiver with Configurable Dual Supply Voltage. Features. Description. Block Diagram
2-Bit Level Shifting Buffer/Transceiver with Features Operation Voltage: 1.65V V DDA 3.6V 2.3V V DDB 5.5V V DDA V DDB High Speed: tpd = 5ns typical into 30pF @ 3V V DD Power down high-impedance inputs
PI3HDMI412FT. 4-Differential Channel, 2:1 Mux/DeMux, DVI/HDMI Compliant Signal Switch with Flow-through Pin Out
Features 4-Differential Channel 2:1 Mux/DeMux DVI, HDMI rev 1.1, and HDMI rev 1.2 signal compatible -3dB BW = 1.5 GHz (3.0Gbps) Crosstalk: -35dB@1.65Gbps Switching speed: 4ns Isolation: -37dB@1.65Gbps
Description Q0+ Q0- Q1+ Q1- Q2+ Q2- VDD Q3+ Q3- Q4+ Q4- CLK_SEL CLK0. nclk0 Q5+ Q5- SYNC_OE Q6+ Q6- CLK1. nclk1 Q7+ Q7- VEE Q8+ Q8- Q9+ Q9-
LVPECL Fanout Buffer with Sync OE Features ÎÎF MAX < 1.5GHz ÎÎ10 pairs of differential LVPECL/ ECL outputs ÎÎLow additive jitter, < 0.03ps (typ) ÎÎSelectable differential input pairs with single ended
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS26LV31T 3V Enhanced CMOS Quad Differential Line Driver General Description
PI74LPT244. Fast CMOS 3.3V 8-Bit Buffer/Line Driver. Features. Description. Block Diagram. Pin Configuration
Fast CMOS 3.3V 8-Bit Buffer/Line Driver Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to