Functional block diagram for SIS8300. Christian Schmidt for the LLRF team Collaboration workshop

Transcription

1 Functional block diagram for SIS8300 Christian Schmidt for the LLRF team Collaboration workshop

2 Outline > Motivation and general comments > Preprocessing LLRF ADC board Block diagram Current status > Working examples > Summary and resuming work Christian Schmidt 1 st XFEL Consortium Meeting Page 2

3 Motivation and general comments > Performance and functionality >> Cost > Reliable and easy maintainable >> Documentation > Generic usage in diff. systems >> Modularity Individual Blocks can be modular plugged together > Upgradability for unforeseen functions >> Ressource margins Reserved FPGA space, server CPU usage, communication bandwidth Code optimization and complexity tradeoff > Test routines, benchmarks, setup procedures > Design concept essential Interface definition Estimation of FPGA space server layout and subsystem integration Christian Schmidt 1 st XFEL Consortium Meeting Page 3

4 DAQ DWC WORD_VS_CHAN_ENA (4) ADC board functional block diagram Field detection SIS8300 utc Att. IF ADC Delay WORD_ADC_FIFO_RESET (4) WORD_ADC_FIFO_DELAY (4) IQ det. Rot.M WORD_SIN (78) WORD_COS (78) 2 Rot.M DC IIR Filter WORD_IIR_COEF[0..9] (14) C1-8 (IQ) Sw. att WORD_ATT_SEL (4) WORD_ATT_VAL (4) Timing WORD_TIMING_FREQ (20) WORD_TIMING_INT_ENA (4) WORD_TIMING_CNT (20) WORD_TIMING_TRG_SEL (4) Diagnostic WORD_STATUS WORD_CLK_CNT WORD_TRG_CNT WORD_LLL_STATUS Configuration WORD_STATUS WORD_CLK_CNT WORD_TRG_CNT WORD_LLL_STATUS WORD_CLK_MUX WORD_CLK_RST WORD_SPI_DIV WORD_ADC_ENA WORD_SPI_ADC WORD_RESET_N WORD_IDELAY_SEL WORD_IDELAY_INC WORD_USER Drift calib AP calc. / Limit WORD_CAV_LIMIT_ACTIVE (4) WORD_CAV_LIMIT (28) + shift PVS (IQ) Limiters switch FW load / Ident DAQ-Mux Memory WORD_FIRMWARE_APP (4) WORD_COMPILATION_APP (4) AREA_BOOT WORD_BOOT_STATUS WORD_DAQ_MUX (20) WORD_DAQ_ENABLE (4) AREA_DMA AREA_DCM DCM Server General Firmware loading / Ident Board Diagnostic Board Configuration Timing Status Signal clock delay Sin/Cos tables for IQ detection Rotation matrix setup IIR coefficients upload VS include Amplitude scaling Cavity limit thresholds Signal chain configuration Subsystem setup Boot / Ident (DCM, Att.) Parameter adjustment DCM reset Attenuator default load Shared memory Cx.Ampl (Probe/Forw/Refl) Cx.Phase (Probe/Forw/Refl) Partial VS (IQ, Probe) Ch 0,9 for readout Raw signal (ADC readout) Amplitude limit/pre-limit DCM readback / time traces Christian Schmidt 1 st XFEL Consortium Meeting Page 4

5 System block brief status overview Processing block status comment Doc DWC att. tested DWC update needed at ACC1, characterization ADC delay IQ detection commissioned commissioned Fine compensation for signal delays, align Probes and for virtual probe Down sampling and sliding window depending on application DCM rotation implemented CMTB next chance for commissioning IIR Filter Partial VS AP calculation Limits ADC RAW commissioned commissioned commissioned tested commissioned Motivated by cavity mode bandstop, but multipurpose use Variable bit shift register, need higher bandwidth on LLL for higher bit representation Precision to be verified, tradeoff concerning delay, reuse on utc, cordic method Pre-limiters to be done, could be shifted to utc if regular LLRF setup Debugging purpose, does block the slow DAQ data readout Christian Schmidt 1 st XFEL Consortium Meeting Page 5

6 Calibrated by measuring system and controller gain A (rms) FB gain vs. Delay scan without applied filter Instability area 1/T ~ 800 khz > Initial delay is given by digital processing Christian Schmidt 1 st XFEL Consortium Meeting Page 6

7 FB gain vs. Delay scan with filter Instability area 1/T ~ 3 MHz > Higher feedback gain, now 7/9Pi mode visible >> suppression needed Christian Schmidt 1 st XFEL Consortium Meeting Page 7

8 Sweeping excitation for 7/9-Pi mode > Sinusoidal excitation on FF signal, measured amplitude response for all cavities > Comparable pattern (location of modes) to 8/9-Pi mode resonance frequencies > Possible beam excitation is to be tested (Filtering on/off on first stage with MIMO) Christian Schmidt 1 st XFEL Consortium Meeting Page 8

9 Measurements to be done > Processing delay measurement (full system and components) > Characterization of delay, sw. Attenuators > Beam based signal calibration Compare with VME system Excitation of fundamental modes in the system > Drift compensation with DCM >.. Christian Schmidt 1 st XFEL Consortium Meeting Page 9

10 Server revisions to be done next > Properties have to be reviewed Cross Check all naming's for unification, necessity and correct location e.g. PFOR.POWER -> PFORW.AMPL.TD, VFORW.AMPL.TD, VFORW.PHASE.TD Check set EGU/XEGU, xscalings RF info server for property limits? > Ref is not correctly displayed (DMA transfer to be checked) > Power readout is not working / scaling coefficients don t have an impact > Notch filter coefficient upload lead sometimes to instabilities > RAW data readout Remapping of server properties needed, normal DAQ is stopped (Mux) > Delay settings Sometimes internal counter which sets delays seems to not loop correctly Christian Schmidt 1 st XFEL Consortium Meeting Page 10

11 Resuming points > Implementation/Integration of DCM module > Distinguish between NC and SC signal preprocessing Processing speed (9 MHz -> 62.5 MHz), system bandwidth, pulse length Signal character different (less channels of comparable signals) Short loop circuit with RTM control > Signal bit level to be send through LLL > Data transfer to server, conversion to 16 bit and rescaling > Individual scaling for other monitoring signals > ADC overflow notification Christian Schmidt 1 st XFEL Consortium Meeting Page 11

12 Summary > Fixed firmware design for front end board for LLRF Tested and commissioned most of processing functionalities Minor additions are still to be done, documentation on the way > Migration to new SIS8300L board Do we have a chance to synthesize/test code before board arrives? Who is going to maintain the firmware during this stage? > Changes / different firmware layout for NC applications Beneficial for other systems like EBPM, REGAE (laser control) Is a server subversion sufficient for this application? Functionality upgrades >> own regulation loop with corresponding RTM Thanks for you attention Christian Schmidt 1 st XFEL Consortium Meeting Page 12

13 A [dbfs] stable area 8/9-pi mode 8/9-pi mode Filtering unwanted signal contributions stable area > Low-pass / band-stop filters are implemented > Reduction of unwanted modes > General signal filtering (LP) Filtered signal f [khz] Christian Schmidt 1 st XFEL Consortium Meeting Page 13

14 Measurements of beam induced transients Sliding window ADC samples Processing samples > Use delay for alignment of individual cavity transient readouts for e.g. VS calibration, beam loading compensation Christian Schmidt 1 st XFEL Consortium Meeting Page 14

15 A [dbfs] Filtered cavity transient response Jump on SP.Ampl (FB) Applied notch filter > Typial step down in amplitude done for multi pulse operation > Broadband excitation leads to oscillation in particular of of the 8/9-pi mode > Impacts from beam loading / pre-limiter setpoint reduction Christian Schmidt 1 st XFEL Consortium Meeting Page 15

16 Cavity notch filters Filter fc + 30 khz Christian Schmidt 1 st XFEL Consortium Meeting Page 16