TC7136 TC7136A. Low Power 3-1/2 Digit Analog-To-Digital Converters FEATURES GENERAL DESCRIPTION TYPICAL APPLICATIONS ORDERING INFORMATION

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1 A Low Power -/2 Digit Analog-To- FEATURES Fast Overrange Recovery, Guaranteed First Reading Accuracy Low Temperature Drift Internal Reference ppm/ C Typ. A... 5ppm/ C Typ. Guaranteed Zero Reading With Zero Input Low Noise... 5 µ P-P High Resolution % Low Input Leakage Current... pa Typ. 0pA Max Precision Null Detectors With True Polarity at Zero High-Impedance Differential Input Convenient 9 Battery Operation With Low Power Dissipation µW Typ. 900µW Max TYPICAL APPLICATIONS Thermometry Bridge Readouts: Strain Gauges, Load Cells, Null Detectors Digital Meters: oltage/current/ohms/power, ph Digital Scales, Process Monitors Portable Instrumentation ORDERING INFORMATION PART CODE A or blank* R (reversed pins) or blank (CPL pkg only) * "A" parts have an improved reference TC Package Code (see below): X X XXX Package Temperature Code Package Pin Layout Range CKW 44-Pin PQFP Formed Leads 0 C to 70 C CLW 44-Pin PLCC 0 C to 70 C CPL 40-Pin PDIP Normal 0 C to 70 C AAILABLE PACKAGES GENERAL DESCRIPTION The and A are low-power, -/2 digit with liquid crystal display (LCD) drivers with analog-todigital converters. These devices incorporate an "integrator output zero" phase which guarantees overrange recovery. The performance of existing TC726, TC726A and ICL726-based systems may be upgraded with minor changes to external, passive components. The A has an improved internal zener reference voltage circuit which maintains the analog common temperature drift to 5ppm/ C (typical) and 75 ppm/ C (maximum). This represents an improvement of two to four times over similar -/2 digit converters. The costly, spaceconsuming external reference source may be removed. The /A limits linearity error to less than count on 200m or 2 full-scale ranges. Roll-over error the difference in readings for equal magnitude but opposite polarity input signals is below ± count. High-impedance differential inputs offer pa leakage currents and a 0 2 Ω input impedance. The differential reference input allows ratiometric measurements for ohms or bridge transducer measurements. The 5µ P-P noise performance guarantees a "rock solid" reading. The auto-zero cycle guarantees a zero display readout for a 0 input. TYPICAL OPERATING CIRCUIT ANALOG INPUT MΩ 0.0 µf 80 kω 0.5 µf µf 4 C C 99 IN 2225 IN A POL ANALOG BP 28 BUFF 0.47 µf 6 29 C AZ INT OSC 2 OSC OSC 9 8 C OSC 40 R 50 pf OSC 560 kω SEGMENT DRIE 20 MINUS SIGN kω 0 kω LCD BACKPLANE 9 CONERSION/SEC TO ANALOG (PIN 2) 40-Pin Plastic DIP 44-Pin Plastic Quad Flat Package Formed Leads 44-Pin Plastic Chip Carrier PLCC -6 0/8/96

2 A ABSOLUTE MAXIMUM RATINGS* Supply oltage ( to )...5 Analog Input oltage (Either Input) (Note )... to Reference Input oltage (Either Input)... to Clock Input... TEST to Package Power Dissipation (T A 70 C) (Note 2) Plastic DIP...2W Plastic Quad Flat Package...00W PLCC...2W Operating Temperature Range C Devices... 0 C to 70 C I Devices C to 85 C ELECTRICAL CHARACTERISTICS: -6 0/8/96 2 Storage Temperature Range C to 50 C Lead Temperature (Soldering, 0 sec) C *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. S = 9, f CLK = 6 khz, and T A = 25 C, unless otherwise noted. Symbol Parameter Test Conditions Min Typ Max Unit Input Zero Input Reading IN = ± Digital Full Scale = 200 m Reading Zero Reading Drift IN = 0, 0 C T A 70 C 0.2 µ/ C Ratiometric Reading IN =, = 00m / Digital Reading NL Nonlinearity Error Full Scale = 20 m or 2 ±0.2 Count Max Deviation From Best Straight Line Roll-Over Error IN = IN 200m ±0.2 Count e N Noise IN = 0, Full Scale = 200m 5 µ P-P I L Input Leakage Current IN = 0 0 pa CMRR Common-Mode Rejection CM = ±, IN = 0, 50 µ/ Ratio Full Scale = 200 m Scale Factor Temperature IN = 99 m, 0 C T A 70 C 5 ppm/ C Coefficient Ext Ref Temp Coeff = 0ppm/ C Analog Common CTC Analog Common 250 kω Between Common and Temperature Coefficient 0 C T A 70 C A 5 75 ppm/ C "C" Commercial Temp ppm/ C Range Devices 25 C T A 85 C A 5 00 ppm/ C "I" Industrial Temp ppm/ C Range Devices C Analog Common oltage 250 kw Between Common and LCD Drive SD LCD Segment Drive oltage to = P-P BD LCD Backplane Drive oltage to = P-P Power Supply I S Power Supply Current IN = 0, to = 9 (Note 6) µa NOTES:. Input voltages may exceed supply voltages when input current is limited to 00µA. 2. Dissipation rating assumes device is mounted with all leads soldered to PC board.. Refer to "Differential Input" discussion. 4. Backplane drive is inphase with segment drive for "OFF" segment and 80 out-of-phase for "ON" segment. Frequency is 20 times conversion rate. Average DC component is less than 50m. 5. See "Typical Operating Circuit". 6. A 48kHz oscillator increases current by 20 µa (typical). Common current not included.

3 A PIN CONFIGURATIONS A B C D NC OSC OSC 4 OSC 42 TEST 4 HI 40 HI LO C C COM IN HI AZ BUFF INT NC OSC 2 OSC D C B NC CKW ACKW (PQFP) G 2 C 0 A 29 G 28 BP 27 POL 26 AB 4 25 E 24 F 2 B D 2 C 2 B 2 A 2 F 2 E 2 D IN LO F 7 9 LO G 8 8 C E 9 7 C D C2 5 IN HI NC 2 CLW 4 NC B ACLW 2 (PLCC) IN LO A2 4 2 AZ F2 5 BUFF E2 6 0 INT D NC NC TEST OSC 5 6 B F E AB 4 POL NC BP G A C G 2 A F G E D 2 NORMAL PIN CONFIGURATION 40 9 OSC OSC2 OSC OSC2 2 REERSE PIN CONFIGURATION 40 9 D 's C B A F OSC TEST OSC TEST C B A F 's G 7 4 C C 7 4 G 0's E D2 C 2 B 2 A 2 F CPL ACPL (PDIP) C ANALOG IN IN CAZ BUFF C ANALOG IN IN C AZ BUFF RCPL ARCPL (Reversed) PDIP E D 2 C 2 B 2 A 2 F 2 0's E 2 D INT INT E 2 D 000's 00's B F E AB 4 POL (MINUS SIGN) G2 C 00's A G BP (BACKPLANE) G2 C 00's A G BP (BACKPLANE) B 00's F E AB 4 000's POL (MINUS SIGN) NC = NO INTERNAL CONNECTION -6 0/8/96

4 A /A PIN DESCRIPTION Pin No. 40-Pin PDIP Normal (Reverse) Name Description (40) Positive supply voltage. 2 (9) D Activates the D section of the units display. (8) C Activates the C section of the units display. 4 (7) B Activates the B section of the units display. 5 (6) A Activates the A section of the units display. 6 (5) F Activates the F section of the units display. 7 (4) G Activates the G section of the units display. 8 () E Activates the E section of the units display. 9 (2) D 2 Activates the D section of the tens display. 0 () C 2 Activates the C section of the tens display. (0) B 2 Activates the B section of the tens display. 2 (29) A 2 Activates the A section of the tens display (28) F 2 Activates the F section of the tens display. 4 (27) E 2 Activates the E section of the tens display. 5 (26) D Activates the D section of the hundreds display. 6 (25) B Activates the B section of the hundreds display. 7 (24) F Activates the F section of the hundreds display. 8 (2) E Activates the E section of the hundreds display. 9 (22) AB 4 Activates both halves of the in the thousands display. 20 (2) POL Activates the negative polarity display. 2 (20) BP Backplane drive output. 22 (9) G Activates the G section of the hundreds display. 2 (8) A Activates the A section of the hundreds display. 24 (7) C Activates the C section of the hundreds display. 25 (6) G 2 Activates the G section of the tens display. 26 (5) Negative power supply voltage. 27 (4) INT The integrating capacitor should be selected to give the maximum voltage swing that ensures component tolerance buildup will not allow the integrator output to saturate. When analog common is used as a reference and the conversion rate is readings per second, a 0.047µF capacitor may be used. The capacitor must have a low dielectric constant to prevent roll-over errors. See Integrating Capacitor section for additional details. 28 () BUFF Integration resistor connection. Use a 80kΩ for a 20 m full-scale range and a.8mω for 2 full-scale range. 29 (2) C AZ The size of the auto-zero capacitor influences the system noise. Use a 0.47µF capacitor for a 200m full scale, and a 0.µF capacitor for a 2 full scale. See paragraph on Auto-Zero Capacitor for more details. 0 () IN The low input signal is connected to this pin. (0) IN The high input signal is connected to this pin. 2 (9) ANALOG This pin is primarily used to set the analog common-mode voltage for battery operation or in systems where the input signal is referenced to the power supply. See paragraph on Analog Common for more details. It also acts as a reference voltage source. -6 0/8/96 4

5 A /A PIN DESCRIPTION (Cont.) Pin No. 40-Pin PDIP Normal (Reverse) Name Description (8) C See pin 4. 4 (7) C A 0.µF capacitor is used in most applications. If a large common-mode voltage exists (for example, the IN pin is not at analog common), and a 200 m scale is used, a µf capacitor is recommended and will hold the roll-over error to 0.5 count. 5 (6) See pin 6. (5) The analog input required to generate a full-scale output (999 counts). Place 00 m between pins 5 and 6 for 99.9 m full scale. Place between pins 5 and 6 for 2 full scale. See paragraph on Reference oltage. 6 (4) TEST Lamp test. When pulled HIGH (to ) all segments will be turned ON and the display should read 888. It may also be used as a negative supply for externally-generated decimal points. See paragraph under Test for additional information. 7 () OSC See pin (2) OSC 2 See pin () OSC Pins 40, 9 and 8 make up the oscillator section. For a 48kHz clock ( readings per second) connect pin 40 to the junction of a 80 kω resistor and a 50pF capacitor. The 80kΩ resistor is tied to pin 9 and the 50pF capacitor is tied to pin 8. GENERAL THEORY OF OPERATION (All Pin designations refer to 40-Pin Dip) Dual-Slope Conversion Principles The /A is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed /A operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: () Input signal integration (2) Reference voltage integration (deintegration) The input signal being converted is integrated for a fixed time period (t SI ), measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (t RI ). In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "rampdown." A simple mathematical equation relates the input signal, reference voltage, and integration time: t SI R t RI IN (t) dt =, RC 0 RC 5 Figure. Basic Dual-Slope Converter where: R = Reference voltage t SI = Signal integration time (fixed) = Reference voltage integration time (variable). t RI ANALOG INPUT SIGNAL OLTAGE INTEGRATOR OUTPUT FIXED SIGNAL INTEGRATE TIME For a constant IN : IN = R. INTEGRATOR SWITCH DRIER POLARITY CONTROL DISPLAY ARIABLE ERENCE INTEGRATE TIME t [ RI t SI ] C INT COMPARATOR PHASE CONTROL CONTROL LOGIC COUNTER IN FULL SCALE IN.2 FULL SCALE CLOCK -6 0/8/96

6 A NORMAL MODE REJECTION (db) t = MEASUREMENT PERIOD 0./t /t 0/t INPUT FREQUENCY Figure 2. Normal-Mode Rejection of Dual-Slope Converter The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. Noise immunity is an inherent benefit. Noise spikes are integrated, or averaged, to zero during integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50 Hz/60 Hz power line period. deintegrate phase. The count lasts from to 40 counts for non-overrange conversions and from to 640 counts for overrange conversions. Auto-Zero Phase During the auto-zero phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on C AZ compensates for device offset voltages. The auto-zero phase residual is typically 0µ to 5µ. The auto-zero duration is from 90 to 2900 counts for non-overrange conversions and from 00 to 90 counts for overrange conversions. Signal Integration Phase The auto-zero loop is entered and the internal differential inputs connect to IN and IN. The differential input signal is integrated for a fixed time period. The /A signal integration period is 000 clock periods or counts. The externally-set clock frequency is divided by four before clocking the internal counters. The integration time period is: 4 t SI = 000, f OSC ANALOG SECTION In addition to the basic integrate and deintegrate dualslope cycles discussed above, the /A designs incorporate an "integrator output-zero cycle" and an "auto-zero cycle." These additional cycles ensure the integrator starts at 0 (even after a severe overrange conversion) and that all offset voltage errors (buffer amplifier, integrator and comparator) are removed from the conversion. A true digital zero reading is assured without any external adjustments. A complete conversion consists of four distinct phases: () Integrator output-zero phase (2) Auto-zero phase () Signal integrate phase (4) Reference deintegrate phase Integrator Output-Zero Phase This phase guarantees the integrator output is at 0 before the system-zero phase is entered. This ensures that true system offset voltages will be compensated for even after an overrange conversion. The count for this phase is a function of the number of counts required by the -6 0/8/96 6 where f OSC = external clock frequency. The differential input voltage must be within the device common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, IN should be tied to analog common. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. Reference Integrate Phase The third phase is reference integrate or deintegrate. IN is internally connected to analog common and IN is connected across the previously-charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is

7 A IN ANALOG IN 2 TYPICAL SEGMENT OUTPUT 0.5 ma 2 ma SEGMENT OUTPUT LCD /A INTERNAL DIGITAL GROUND C C C BUFF R INT C AZ C INT INT LCD SEGMENT DRIERS 0 µa 4 6 ZI & AZ 5 ZI & AZ ZI INTEGRATOR AZ TO DIGITAL SECTION 7 SEGMENT DECODE 7 SEGMENT DECODE DATA LATCH 7 SEGMENT DECODE INT DE DE () () COMPARATOR THOUSANDS HUNDREDS TENS UNITS DE () DE () AZ & DE (±) 2.8 LOW TEMPCO TO SWITCH DRIERS FROM COMPARATOR OUTPUT CLOCK f OSC 4 CONTROL LOGIC INT 26 INTERNAL DIGITAL GOUND TH = OSC OSC 2 OSC R OSC C OSC BP W 7 26 TEST Figure. A Block Diagram 7-6 0/8/96

8 A INT 000 EXTENDED PERIODS. The display font and segment drive assignment are shown in Figure 6. DENT 2000 DISPLAY FONT ZI AZ 's 00's 0's 's 4000 Figure 4. Conversion Timing During Normal Operation Figure 6. Display FONT and Segment Assignment INT DEINT ZI AZ Figure 5. Conversion Timing During Overrange Operation between 0 and 2000 internal clock periods. The digital reading displayed is 000 DIGITAL SECTION The /A contains all the segment drivers necessary to directly drive a -/2 digit LCD. An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 800. For three conversions per second the backplane frequency is 60Hz with a 5 nominal amplitude. When a segment driver is in-phase with the backplane signal, the segment is OFF. An out-of-phase segment drive signal causes the segment to be ON, or visible. This AC drive configuration results in negligible DC voltage across each LCD segment, ensuring long LCD life. The polarity segment driver is ON for negative analog inputs. If IN and IN are reversed, this indicator would reverse. On the /A, when the TEST pin is pulled to, all segments are turned ON. The display reads 888. During this mode the LCD segments have a constant DC voltage impressed. DO NOT LEAE THE DISPLAY IN THIS MODE FOR MORE THAN SEERAL MINUTES. LCDS MAY BE DESTROYED IF OPERATED WITH DC LEELS FOR -6 0/8/ IN System Timing The oscillator frequency is divided by 4 prior to clocking the internal decade counters. The four-phase measurement cycle takes a total of 4000 counts, or 6,000 clock pulses. The 4000-count cycle is independent of input signal magnitude. Each phase of the measurement cycle has the following length: () Auto-zero phase: 000 to 2900 counts (200 to,600 clock pulses) (2) Signal integrate: 000 counts (4000 clock pulses) This time period is fixed. The integration period is: t SI = 4000 ( ), f OSC where f OSC is the externally-set clock frequency. () Reference integrate: 0 to 2000 counts (4) Zero integrator: to 640 counts The is a drop-in replacement for the TC726 and ICL726. The A offers a greatly-improved internal reference temperature coefficient. Minor component value changes are required to upgrade existing designs and improve the noise performance. COMPONENT ALUE SELECTION Auto-Zero Capacitor (C AZ ) The C AZ capacitor size has some influence on system noise. A 0.47µF capacitor is recommended for 200m fullscale applications where LSB is 00µ. A 0.µF capacitor is adequate for 2 full-scale applications. A Mylar-type dielectric capacitor is adequate.

9 A Reference oltage Capacitor (C ) The reference voltage, used to ramp the integrator output voltage back to zero during the reference integrate phase, is stored on C. A 0.µF capacitor is acceptable when is tied to analog common. If a large commonmode voltage exists ( analog common) and the application requires a 200m full scale, increase C to µf. Roll-over error will be held to less than 0.5 count. A Mylar-type dielectric capacitor is adequate. Integrating Capacitor (C INT ) C INT should be selected to maximize integrator output voltage swing without causing output saturation. Analog common will normally supply the differential voltage reference this case, a ±2 full-scale integrator output swing is satisfactory. For readings per second (f OSC = 48kHz) a 0.047µF value is suggested. For one reading per second, 0.5µF is recommended. If a different oscillator frequency is used, C INT must be changed in inverse proportion to maintain the nominal ±2 integrator swing. An exact expression for C INT is: (4000) f OSC C INT ( ) ( FS RINT ) =, Component alue INT where: f OSC = Clock frequency at pin 8 FS = Full-scale input voltage R INT = Integrating resistor INT = Desired full-scale integrator output swing. C INT must have low dielectric absorption to minimize roll-over error. A polypropylene capacitor is recommended. Integrating Resistor (R INT ) The input buffer amplifier and integrator are designed with Class A output stages. The output stage idling current is 6µA. The integrator and buffer can supply µa drive currents with negligible linearity errors. R INT is chosen to remain in the output stage linear drive region, but not so large that PC board leakage currents induce errors. For a 200m full scale, R INT is 80kΩ. A 2 full scale requires.8mω. Nominal Full-Scale oltage 200m NOTE: fosc = 48kHz ( readings per sec). R OSC = 80kΩ, C OSC = 50pF. 2 C AZ 0.47µF 0.µF R INT 80kΩ.8MΩ C INT 0.047µF 0.04µF 9 Oscillator Components C OSC should be 50pF. R OSC is selected from the equation: 0.45 f OSC =. RC Note that f OSC is 4 to generate the A's internal clock. The backplane drive signal is derived by dividing f OSC by 800. To achieve maximum rejection of 60Hz noise pickup, the signal integrate period should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 20kHz, 80kHz, 60kHz, 40kHz, etc. should be selected. For 50 Hz rejection, oscillator frequencies of 200kHz, 00kHz, 66-2/kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings per second) will reject both 50Hz and 60Hz. Reference oltage Selection A full-scale reading (2000 counts) requires the input signal be twice the reference voltage. Required Full-Scale oltage* * FS = m 2 00m In some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a pressure transducer output for 2000 lb/in. 2 is 400m. Rather than dividing the input voltage by two, the reference voltage should be set to 200m. This permits the transducer input to be used directly. The differential reference can also be used when a digital zero reading is required when IN is not equal to zero. This is common in temperature measuring instrumentation. A compensating offset voltage can be applied between analog common and IN. The transducer output is connected between IN and analog common. DEICE PIN FUNCTIONAL DESCRIPTION Differential Signal Inputs IN (Pin ), IN (Pin 0) The /A is designed with true differential inputs and accepts input signals within the input stage commonmode voltage range ( CM ). The typical range is to. Common-mode voltages are removed from the system when the A operates from a battery or floating power source (isolated from measured system), and IN is connected to analog common ( COM ). (See Figure 7.) -6 0/8/96

10 A SEGMENT DRIE LCD GND POWER SOURCE MEASURED SYSTEM GND BUF C AZ INT POL BP OSC A ANALOG 9 OSC OSC 2-6 0/8/96 Figure 7. Common-Mode oltage Removed in Battery Operation With IN = Analog Common In systems where common-mode voltages exist, the 86 db common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large positive CM exists in conjunction with a full-scale negative differential signal. The negative signal drives the integrator output positive along with CM (see Figure 8.) For such applications, the integrator output swing can be reduced below the recommended 2 full-scale swing. The integrator output will swing within 0. of or without increased linearity error. Differential Reference (Pin 6), (Pin 5) The reference voltage can be generated anywhere within the to power supply range. To prevent roll-over type errors being induced by large common-mode voltages, C should be large compared to stray node capacitance. IN CM INPUT C I BUFFER R I I INTEGRATOR T I = I [ CM R IN Where: I C I 4000 T I = Integration time = fosc C I = Integration capacitor R I = Integration resistor Figure 8. Common-Mode oltage Reduces Available Integrator Swing ( COM IN ) [ 0 The /A offers a significantly improved analog common temperature coefficient. This potential provides a very stable voltage, suitable for use as a voltage reference. The temperature coefficient of analog common is typically 5 ppm/ C. ANALOG (Pin 2) The analog common pin is set at a voltage potential approximately below. The potential is guaranteed to be between 2.7 and.5 below. Analog common is tied internally to an N-channel FET capable of sinking 00µA. This FET will hold the common line at below if an external load attempts to pull the common line toward. Analog common source current is limited to µa. Analog common is therefore easily pulled to a more negative voltage (i.e., below ). The /A connects the internal IN and IN inputs to analog common during the auto-zero phase. During the reference-integrate phase, IN is connected to analog common. If IN is not externally connected to analog common, a common-mode voltage exists, but is rejected by the converter's 86dB common-mode rejection ratio. In battery operation, analog common and IN are usually connected, removing common-mode voltage concerns. In systems where IN is connected to the power supply ground or to a given voltage, analog common should be connected to IN. The analog common pin serves to set the analog section reference, or common point. The A is specifically designed to operate from a battery or in any measurement system where input signals are not referenced (float) with respect to the A power source. The analog common potential of gives a 7 end of battery life voltage. The common potential has a 0.00%/% voltage coefficient. With sufficiently high total supply voltage ( > 7),

11 A analog common is a very stable potential with excellent temperature stability (typically 5 ppm/ c). for A This potential can be used to generate the A's reference voltage. An external voltage reference will be unnecessary in most cases because of the 5 ppm/ C temperature coefficient. See A Internal oltage Reference discussion. TEST (Pin 7) The TEST pin potential is 5 less than. TEST may be used as the negative power supply connection for external CMOS logic. The TEST pin is tied to the internally-generated negative logic supply through a 500Ω resistor. The TEST pin load should not be more than ma. See the Applications Section for additional information on using TEST as a negative digital logic supply. If TEST is pulled high (to ), all segments plus the minus sign will be activated. DO NOT OPERATE IN THIS MODE FOR MORE THAN SEERAL MINUTES. With TEST =, the LCD segments are impressed with a DC voltage which will destroy the LCD. A Internal oltage Reference The analog common voltage temperature stability has been significantly improved (Figure 9). The "A" version of the industry-standard device allows users to upgrade old systems and design new systems without external voltage references. External R and C values do not need to be changed; however, noise performance will be improved by increasing C AZ. (See Auto-Zero Capacitor section.) Figure 0 shows analog common supplying the necessary voltage reference for the /A. ANALOG TEMPERATURE COEFFICIENT (ppm/ C) GUARANTEED MAXIMUM TYPICAL A Figure 9. Analog Common Temperature Coefficient GUARANTEED MAXIMUM TYPICAL NO MAXIMUM SPECIFIED TYPICAL ICL A ANALOG SET = /2 FULL SCALE 240 kω 0 kω Figure 0. A Internal oltage Reference Connection APPLICATIONS INFORMATION Liquid Crystal Display Sources Several manufacturers supply standard LCDs to interface with the A -/2 digit analog-to-digital converter. Representative Manufacturer Address/Phone Part Numbers * Crystaloid 5282 Hudson Dr. C55, H555, Electronics Hudson, OH 4426 T55, SX AND 720 Palomar Ave. FE 020, 050 Sunnyvale, CA FE 020, FE 220 GI, Inc. 800 ernon St. Ste. 2 I048, I26 Roseville, CA Hamlin, Inc. 62 E. Lake St. 902, 9, 90 Lake Mills, WI * NOTE: Contact LCD manufacturer for full product listing/specifications. Decimal Point and Annunciator Drive The TEST pin is connected to the internally-generated digital logic supply ground through a 500Ω resistor. The TEST pin may be used as the negative supply for external CMOS gate segment drivers. LCD annunciators for decimal points, low battery indication, or function indication may be added without adding an additional supply. No more than ma should be supplied by the TEST pin: its potential is approximately 5 below. -6 0/8/96

12 A Ratiometric Resistance Measurements The A's true differential input and differential reference make ratiometric readings possible. In ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. No accurately-defined reference voltage is needed. The unknown resistance is put in series with a known standard and a current passed through the pair. The voltage developed across the unknown is applied to the input and the voltage across the known resistor applied to the reference input. If the unknown equals the standard, the display will read 000. The displayed reading can be determined from the following expression: R UNKNOWN R STANDARD Displayed reading = 000. The display will overrange for R UNKNOWN 2 R STANDARD. Simple Inverter for Fixed Decimal Point or Display Annunciator A BP TEST A BP Multiple Decimal Point or Annunciator Driver DECIMAL POINT SELECT GND TO LCD DECIMAL POINT TO LCD BLACK PLANE TO LCD DECIMAL POINTS R STANDARD R UNKNOWN 0.7%/ C PTC Figure 2. Low Parts Count Ratiometric Resistance Measurement 60 kω 00 kω 00 kω N448 SENSOR R 2 50 kω Figure. Temperature Sensor 5.6 kω 60 kω N448 R 20 kω R R 50 kω R 2 20 kω IN IN A ANALOG IN IN IN IN LCD 9 A 9 A TEST 400 GND -6 0/8/96 Figure. Decimal Point and Annunciator Drives 2 Figure 4. Positive Temperature Coefficient Resistor Temperature Sensor

13 A PACKAGE DIMENSIONS 44-Pin PQFP 7 MAX..0 (0.80) TYP. PIN.08 (0.45).02 (0.0).98 (0.0).90 (9.90).557 (4.5).57 (.65).009 (0.2).005 (0.).04 (.0).026 (0.65).98 (0.0).90 (9.90).557 (4.5).57 (.65).096 (2.45) MAX..00 (0.25) TYP..08 (2.0).075 (.90) 40-Pin PDIP PIN.555 (4.0).50 (.46) (52.45) (5.49).60 (5.49).590 (4.99).200 (5.08).40 (.56).50 (.8).5 (2.92).040 (.02).020 (0.5).05 (0.8).008 (0.20) MIN..0 (2.79).090 (2.29).070 (.78).045 (.4).022 (0.56).05 (0.8).700 (7.78).60 (5.50) Dimensions: inches (mm) -6 0/8/96

14 A PACKAGE DIMENSIONS (Cont.) 44-Pin PLCC PIN.695 (7.65).685 (7.40).656 (6.66).650 (6.5).050 (.27) TYP..02 (0.5).0 (0.).02 (0.8).026 (0.66).60 (6.00).59 (5.00).656 (6.66).650 (6.5).695 (7.65).685 (7.40).020 (0.5) MIN..20 (.05).090 (2.29).80 (4.57).65 (4.9) Dimensions: inches (mm) -6 0/8/96 4

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