UNIVERSITY OF CINCINNATI

Transcription

1 UNIVERSITY OF CINCINNATI A. DATE: November 12, 2003 I, B. Vincent Stenger, hereby submit this as part of the requirements for the degree of: C. PhD in: D. Electrical Engineering It is entitled: E. Vertical Multimode Interference Optical Waveguide Taps for Silicon CMOS Circuits F. G. H. I. Approved by: J. Dr. Fred R. Beyette, Jr. K. Dr. Joseph Boyd L. Dr. Peter Kosel M. Dr. Andrew Steckl N. Dr. Stephen Clarson

2 VERTICAL MULTIMODE INTERFERENCE OPTICAL WAVEGUIDE TAPS FOR SILICON CMOS CIRCUITS A dissertation submitted to the Division of Research and Advanced Studies of the University of Cincinnati in partial fulfillment of the requirements for the degree of DOCTORATE OF PHILOSOPHY (Ph.D.) In the Department of Electrical and Computer Engineering and Computer Science of the College of Engineering 2003 by Vincent Stenger B.S. University of Cincinnati, 1991 M.S., University of Cincinnati, 1994 Committee Chair: Dr. Fred R. Beyette, Jr. Committee Members: Dr. Joseph Boyd Dr. Andrew Steckl Dr. Peter Kosel Dr. Stephen Clarson

3 ABSTRACT A compact, low loss, optical tap technology is critical for the incorporation of optical interconnects into mainstream CMOS processes. An asymmetric, vertical multimode interference effect based device is investigated that has the potential for very high speed and optically efficient performance in a compact geometry and in a CMOS compatible process. 2-D and 3-D device simulations have confirmed a low excess optical loss on order of 0.2 db, and a nominal 40% (2.2 db) optical coupling into the CMOS circuitry over a wide range of guide to substrate distances. Simulated devices are on the order of 25 to 30 µm in length and as narrow as 1 µm for channel guide based designs. High temperature, hybrid polymer materials used for commercial CMOS inter-metal dielectric layers were targeted for optical waveguide and tap fabrication and were incorporated into the models. Tap structures, based on 5 µm wide ridge waveguides with 1 µm thick cores, were fabricated on silicon substrates at guide to substrate spacings up to 6 µm. Devices were optically tested for polarization sensitivity and insertion losses, with the experimental results showing good agreement with theory. Low excess losses on order of 0.3 db were confirmed, as was the effectiveness of a thick isolating spacer layers. Low cost, silicon CMOS based processing makes the new tap technology especially suitable for computer multi-chip module and board level interconnects, as well as for metro fiber to the home (FTTH) and fiber to the desk telecommunications applications.

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5 ACKNOWLEDGEMENTS I would like to acknowledge my advisor, Dr. Fred R. Beyette, Jr., for his assistance in my selection of a thesis topic, as well as for his continued technical input and support of the thesis project development. His patience and support of my work despite my somewhat unique circumstances is greatly appreciated, and I hope that this work will in some way contribute to his goals, and provide topics for future research in his group at UC. I would like to acknowledge both Dr. Beyette and our Department head, Dr. Thomas Mantei, for allowing me to carry out my research work with both corporate and academic bases of operation. This gave me access to equipment that would otherwise not have been available to me. I also acknowledge Dr. Joseph Boyd, Dr. Andrew Steckl, Dr. Peter Kosel, and Dr. Stephen Clarson, for serving on my thesis committee. I wish to acknowledge Ron Flenniken for his assistance during the fabrication phase of the project. I wish to acknowledge Auxora, Inc. for contributions to this work. Auxora provided access to equipment for thin film characterization, e-beam deposition, and other clean room processes, as well as providing the lithography mask, optics components, and instrumentation for the final test phase of the project. I want to acknowledge my lab mates at UC for their technical and personal support during this project as well. Special mention goes to Chris Baker, Don Abeysinghe, and Anish Saran, who were great sources for discussion and ideas during this project, as well as being good friends. Prashant Bhadri and all the other PSDL members made sure I felt at home at UC no matter how long I might be away. Bob Hudgins and others in Dr. Steckl s lab also assisted in the progress of this project. I d like to acknowledge Vu Phan of UC Irvine s integrated nanosystems research facility (INRF) clean room, as well as others from the INRF lab staff, for their technical support and friendships. Finally, I d like to acknowledge my friends and family for their patience and personal support of my thesis work.

6 TABLE OF CONTENTS 1. INTRODUCTION 1.1. Optical Interconnects and Electronics Optical Tap Applications Optical Waveguide Tap Technologies Goals for this Work 8 2. OPTICAL WAVEGUIDE TAP DESIGN 2.1. Candidate Tap Design Approaches Design Constraints The Vertical Multimode Interference Tap Symmetric vs. Asymmetric Tap Design The Spacer Layer The Extended Well Tap Integration with Traveling Wave Photodetector Cascaded Tap Signal Power Equalization Wavelength Demultiplexing Extension of the Tap Structure to Other Functions Optical modulation Optical Interconnects SIMULATIONS Definitions of terms Waveguide Design Material Selection 34 i

7 Waveguide dimensions Lower Cladding Thickness Calculations D TAP Simulations The Symmetric MMI Tap The Asymmetric MMI Tap The extended well Asymmetric Tap Spacer Layer Thickness Effects Validation of the 2-d BeamProp Results D SIMULATIONS Baseline 2-D Simulations D Channel Tap Simulation D Ridge Tap Simulation Well Width Effect in Ridge Guide Taps Conclusions and Final Designs WAVEGUIDE TAP FABRICATION 4.1. Mask Design Process Description General Process Flow Process Evolution Detailed Process Description DEVICE TEST AND ANALYSIS Test Set-Up Description Fabricated Device Modeling 120 ii

8 Fabricated Device Test Results Data Format and Definitions of Terms Data Analysis Parameters Waveguide Analysis Data Analysis Results Conclusions CONCLUSIONS Summary of this Work Future Work Contribution of this Work 141 BIBLIOGRAPHY 142 APPENDIX A - Insertion Data 148 iii

9 LIST OF TABLES Table 3.1: Summary of tap designs with estimated performance 80 Table 4.1: Coupler lengths for ridge guide based tap couplers 85 Table 4.2: Material properties for spin-on products acquired for this work. 88 Table 4.3: Deposition parameters for layers in this fabrication work 99 Table 5.1: Summary of physical and material properties of test samples 125 Table 5.2: Summary of measurements, and comparison to simulated (theoretical) results 134 iv

10 LIST OF FIGURES Fig. 1.1: Optical clock distribution using a holographic pattern 4 Fig. 1.2: Alternative technique to the holographic distribution technique, using a beam splitter and waveguides to distribute a vertically directed clock beam 6 Fig. 1.3: Example optical waveguide taps, based on diffraction gratings, applied to optical clock signal distribution 7 Fig. 2.1: Initial design of a single mode waveguide based tap based on vertical symmetric multimode interference 16 Fig. 2.2: Final optimized design for the vertical MMI optical waveguide tap 17 Fig. 2.3: Extension of the tap well thickness by ½ the guide thickness to achieve sufficient guide to substrate isolation without a spacer layer. 20 Fig. 2.4: Top and cross-sectional views of the complete vertical MMI optical waveguide tap design based on channel waveguides 22 Fig. 2.5: Top and cross-sectional views of the complete vertical MMI optical waveguide tap design utilizing ridge guides for lateral optical confinement 23 Fig. 2.6: Approaches for tap signal equalization over a series cascade of tap devices. (a) fixed spatial period, (b) segmented couplers with terminating taps, and (c) fixed segment lengths for non-terminating taps 24 Fig. 2.7: Design for grating-based WDM waveguide taps 27 Fig. 2.8: Optical modulation scheme using either absorption or index modulation of an isolated silicon layer (SOI) 28 Fig. 2.9: Use of the asymmetric vertical MMI tap structure with an electro-optic tap well material for optical modulation 29 Fig. 2.10: Application of the invention to vertical interconnects in a multi-metal layer electronic chip (or printed circuit board) process 31 Fig. 3.1: Two lateral confinement geometries for the vertical multimode interference optical waveguide tap; (a) low lateral confinement ridge guide case, and (b) high lateral confinement channel guide case. 38 Fig. 3.2: Plots of TE and TM optical loss to the bare Silicon substrate as a function of lower cladding thickness 40 v

11 Fig.3.3: Basic structure for the hybrid polymer based ridge guide on a CMOS circuit 41 Fig. 3.4: Simulated TE mode response of the isolated symmetric tap structure 43 Fig. 3.5: Simulated response to increasing the tap length by 4 x unit length to 96 µm 44 Fig. 3.6: Simulated TE mode response of the symmetric tap over a silicon substrate. Note poor mode recovery 45 Fig. 3.7: Simulated TM response for the structure of Fig Fig. 3.8: Plot of simulated transmission as a function of exit guide offset for the symmetric tap well on a silicon substrate. 47 Fig. 3.9: Simulated TE mode response to a symmetric well tap with an exit guide offset of 0.3 um (30%) 48 Fig. 3.10: TM mode simulation for the structure of Fig Fig. 3.11: Simulated TE response of the symmetric tap over silicon substrate with the addition of an index matching 1µm thick spacer layer 50 Fig. 3.12: Simulated TM response for the structure of Fig Fig. 3.13: Simulated TE response of the isolated asymmetric MMI tap structure 52 Fig. 3.14: Simulated TE response to a 4 x unit length isolated asymmetric MMI tap structure 53 Fig. 3.15: TE mode response of the asymmetric MMI waveguide tap structure on silicon substrate 54 Fig. 3.16: TM response of the structure in Fig Fi.g 3.17: TE response for a 3 x unit length asymmetric tap on silicon substrate 56 Fig. 3.18: TM response of the structure of Fig Fig. 3.19: Isolated extended well tap structure TE response 58 Fig. 3.20: TE response of the extended well, asymmetric MMI tap structure on silicon substrate 59 Fig. 3.21: TM response of the structure of Fig Fig. 3.22: Plots of TE and TM transmission and excess loss responses as a function of well depth 61 Fig. 3.23: TE response of the asymmetric MMI tap on silicon with a 2 µm spacer layer. vi

12 63 Fig. 3.24: TM response of the structure in Fig Fig. 3.25: Case of very thick 10 µm spacer 64 Fig. 3.26: Plots of TE and TM transmission as a function of spacer thickness for the standard well depth asymmetric MMI tap structure on a silicon substrate 66 Fig. 3.27: Plot of wavelength and polarization sensitivity for case of no spacer, and for case of near-equalized TE and TM spacer thickness of 2 µm 67 Fig. 3.28: FDTD 2-D simulation of TE response of the asymmetric vertical MMI tap 68 Fig. 3.29: FDTD 2-D simulation of TM response of the asymmetric vertical MMI tap 69 Fig. 3.30: 2-D simulation of the isolated tap under reduced Pade order of 1,1 and nonvector mode : 2-D TE simulations of the absorbing spacer/substrate at reduced simulation parameters of Pade Order = 1,1 and vector mode = none. 72 Fig. 3.32: 3-D simulation of TE light in the isolated, channel guide tap 73 Fig. 3.33: 3-D simulation of TE light in the channel guide tap over absorbing spacer 74 Fig. 3.34: 3-D BeamProp simulation of TE light in the isolated ridge guide MMI tap 75 Fig. 3.35: 3-D BeamProp simulation of TE light in the ridge guide MMI tap over the absorbing spacer substrate 76 Fig. 3.36: Poor 3-D mode recovery loss of an isolated ridge guide tap with tap well width W T = ridge width W R = 5 µm 77 Fig. 3.38: Case of W T = 3W R 78 Fig. 3.39: Plot of transmission and mode recovery loss over well width of an isolated ridge tap structure 79 Fig. 4.1: Overall view of the mask Layout 83 Fig. 4.2: Composite pattern showing ridge guide test devices for cascaded in-line tap devices 84 Fig: 4.3: Test structures for segmented ridge guide tap couplers 84 vii

13 Fig. 4.4: Test structures for continuous coupler devices 85 Fig. 4.5: Process envisioned for fabrication of tap structures on device populated silicon substrates 87 Fig. 4.6: Index and thickness results of various mixes of spin-on polymer materials 90 Fig. 4.7: Pocess used for fabrication of tap device test structures on silicon substrates 94 Fig. 4.8: Mounting of 3 wafer sample in preparation for polishing 104 Fig. 4.9: Approximately linear polish pattern used for this work 105 Fig. 4.10: Earlier ridge guide based tap well (microscope images) 108 Fig. 4.11: Ridge guide based (wide) planarized tap well. 108 Fig. 4.12: Channel guide based (narrow) tap well. 109 Fig. 4.13: Sectioning of the samples after completion of ridge waveguide tap structures 111 Fig. 4.14: Sample cleaved ridge guide facets 112 Fig. 4.15: Completed ridge tap device alongside a reference waveguide 113 Fig. 4.16: A segmented coupler tap device. 113 Fig. 4.17: A continuous coupler tap. 114 Fig. 5.1: Test set-up for insertion loss and spectral response tests of fabricated optical ridge waveguide tap devices 117 Fig. 5.2: Optical test set-up for fabricated ridge tap devices 118 Fig. 5.3: Close-up of optical test set-up 119 Fig. 5.4: Schematic layout of tap and guide devices measured in this work 120 Fig. 5.5: Tap model for fabricated devices 121 Fig. 5.6: Effect of the well polish step parameter s well on transmission loss for the isolated tap case 121 Fig. 5.7: Alignment criteria for ridge tap devices 122 Fig. 5.8: Maps of TE mode loss data for samples R1, R2 isolated ridge tap devices 130 Fig. 5.9: TM loss data for sample R1 130 viii

14 Fig. 5.10: Map of loss data for sample R3 extended well depth ridge tap devices 131 Fig. 5.11: Map of loss data for sample R4 standard well depth (thick cladding) ridge taps 131 Fig. 5.12: Map of loss data for sample R6, thick spacer/extended well ridge tap devices 132 Fig. 5.13: Visible (top) and infrared (bottom) CCD images of an isolated tap device (R1) under injection of 840 nm light. 137 Fig. 5.14: Visible (top) and IR (bottom) images for a tap that is close to the unit (optimum) length. 138 ix

15 CHAPTER 1 INTRODUCTION In this chapter, the background for this thesis work is described, including the general advantages of optics over electronics for signal interconnections, and the role of optical tap devices in optical interconnects. Applications of optical taps are discussed with an emphasis toward configurations that benefit from integrated optic waveguide based taps. The chapter finishes with a summary of the goals for this thesis work. 1.1 OPTICAL INTERCONNECTS AND ELECTRONICS Integration of optical components and electronics for networking, sensing, and displays has been an ongoing process for many years. Much success has been met in the area of long distance fiber optic telecommunications, though discrete electro-optical, and specialty electronic component packaging in current fiber optic technologies can be costly. Since long distance optical links serve many users, the cost can be justified. However, as optical networks advance closer to the end user, such as in metropolitan and local area networks, the cost of discrete packaging of bulk optical and electronic components becomes prohibitive. Single chip integration of optics and electronics at the transmitting and receiving ends is an enabler for low cost, high performance, local area optical networking and distributed (parallel) computing [1]. The ultimate speed of a computer system, whether it is a single processor system or a distributed network of computers, is typically limited by the rate at which information processing blocks can be clocked, synchronized, and linked 1

16 to other processing blocks. Optical links have inherently higher bandwidth than electrical ones by virtue of their high optical carrier frequencies, low loss, and low dispersion guide technology. What is sought in metropolitan, local, board, and chip level optical links is an optical interconnect technology that is compact, economical, and that can be readily incorporated into existing electronic chip processes. With high yield, low cost processes, optical links at the computer board and chip levels can be made feasible. Chip level optical links, based on integrated optic guide technologies, have been proposed to replace metal electrical data paths in cases where high frequencies make electrical traces impractical. This is especially relevant to high-speed clock signals, which represent the highest frequencies in a computer or communication system. As silicon CMOS circuit technology is scaled higher in speed to the GHz range and beyond, implementation of clock traces over large chip and board areas becomes especially troublesome due to the skin effect and to finite electrical conductivity. It is also difficult to isolate the metal traces at high frequencies while maintaining a correspondingly dense layout, resulting in clock spurs appearing throughout the circuit. Clock skew, or phase shifts over the various clock distribution points can lead to timing errors in data communication between circuit blocks, which can ultimately limit the processing speed of the entire circuit. Various solutions to the metal trace problem have been introduced. Electrical solutions to the problem include implementation of matched transmission line structures, repeater stages, higher conductivity copper traces, low-k dielectric layers, and lower capacitance, silicon-on-insulator (SOI) based circuitry. Each of these approaches can offer perhaps a factor of 30% in gain-bandwidth to power performance improvement. 2

17 The trade-offs are typically in terms of chip real estate, and increased processing costs. In the case of SOI, floating body effects, noise, and thermal effects must be taken into account. In contrast to the electrical approach, optical based interconnects fundamentally have many orders higher available bandwidth due to the extremely high carrier frequencies of optical signals (over 100 THz). In addition, optical signals can be carried over low-loss, low-latency, optical traces or waveguides, and experience very little or no crosstalk effects. These waveguides can carry many signals, in the form of multiple wavelengths, in parallel over a single optical trace. Since signal processing is usually more efficient with electronics, the core enabling components for optical interconnects in an electronic environment are the optoelectronic transmitter and receiver. These devices convert the electronic signal to an optical one for transmission over the optical link, and then back to an electrical one for further processing. The optical tap is a special case of an optoelectronic receiver, whereby some portion of the light is collected at each tap device, and the remainder is typically passed on to other taps in a series fashion. 1.2 OPTICAL TAP APPLICATIONS The variable coupling feature of the optical tap makes it ideal for high speed clock distribution, whereby an optical clock signal is distributed via optical paths to multiple tap points on an electronic circuit board or chip. A good review of optical clock distribution techniques may be found in [2]. Both free space (holographic and grating) and guided wave approaches are reviewed, although the guided wave approaches would likely be more compatible with planar CMOS chip processes. The holographic approach 3

18 toward clock distribution is shown in Fig This represents the near-ideal case in terms of synchronizing the multiple circuit blocks to a single clock. By simple ray tracing analysis, a slight variation in phase between the center circuit block and the outer ones will occur due to a path length difference. Issues with the holographic technique primarily include optical efficiency and packaging, with packaging being the primary drawback. The 3-D designs significantly increases vertical headroom, as well as blocking off large volumes of metal interconnect regions to make room for the optical beam vias. Fig. 1.1: Optical clock distribution using a holographic pattern Although it may not always be practical for certain applications, it is important to note that free space coupling approaches have their applications. In image processing 4

19 applications, arrays of devices called smart pixels are arranged on multiple, vertically stacked, free space beam coupled planes. Pixels in one plane collect normal incident light beams, process them electronically, and then generate new light signal beams which are passed on to the next smart pixel plane for further processing. Such an approach applied to the optical interconnection of circuit planes is described in [3]. A specific architecture for free space VLSI optical interconnects is reported in [4]. Such approaches may be useful for vertically arranged board to board interconnects. Unfortunately, for chip level interconnects, free space approaches would likely incur too much chip area loss to be practical. An alternative technique to holographic optical signal distribution uses a single vertical beam to a center chip location, where the beam is split laterally to multiple tap points on the chip. Each tap point would consist of a grating or other lateral tap device to couple the beam into the detector for signal conversion. This approach is shown in Fig The waveguides could be integrated within the metallization layers of the CMOS circuit using standard inter-metal dielectric (IMD) processes. The use of waveguide gratings in this particular case would add an expense in terms of chip real estate due to typical grating lengths being on order of millimeters for such devices. Although chip lateral real estate could potentially be better conserved with improved waveguide tap techniques, the vertical coupling would still incur a 3-D headroom penalty. One technique for branching of the light at the chip surface using surface relief polygonal gratings has been reported in [5], with combined optical efficiency given as 65%. However, the central beam splitting grating was operated in transmission mode, with the substrate backside acting as a mirror to redirect the diffracted beam to the 5

20 detector at a laterally shifted point on the substrate top surface. Obviously, at the operating wavelength, the substrate would need to be transparent and the detector would need to be absorbing. Given the 1.3 µm wavelength used in that work, the authors apparently planned to use Germanium doped silicon, or bump bonded III-V based detectors for the tap function. This would increase complexity and make the design less compatible with standard CMOS processes. Fig. 1.2: Alternative technique to the holographic distribution technique, using a beam splitter and waveguides to distribute a vertically directed clock beam An all-integrated optic approach to clock distribution is shown in Fig Here, the modulated light is inserted laterally via the guide end facets and distributed to multiple diffraction points on the electrical circuit board or chip. Again, gratings are shown as the most common optical tap method for redirecting the light to the photodetectors. The gratings can be made wavelength sensitive to provide wavelength 6

21 demultiplexing functionality, though at the expense of increased scatter losses and relatively large lateral size. Diffraction Gratings CMOS Circuits Optical Clock Optical Waveguides Fig. 1.3: Example optical waveguide taps, based on diffraction gratings, applied to optical clock signal distribution Another key application of optical taps is optical channel monitoring, whereby a small portion of the light at specific wavelengths (channels) is collected at very low excess loss for signal monitoring and equalization purposes. By increasing the tap light collection and making it wavelength selective, channel add and drop functionality can be attained. Optical add/drop refers to the wavelength or channel selective optical signal insertion onto, and extraction from, an optical path. The optical add/drop module (OADM) is a core component to any multi-channel optical network. 7

22 1.3 OPTICAL WAVEGUIDE TAP TECHNOLOGIES Despite the level of interest indicated by a number of journal letters and conference papers, there is much yet to be done in implementing practical board and chip level optical interconnects. This especially applies in the case of efficient optical waveguide taps on silicon CMOS circuits, where complex surface features can complicate the problem of integrating low loss optical waveguides. To date, optical interconnects are typically multimode, and are routed over smooth surfaces [6], [7], [8]. Integrated optic tap schemes often incorporate diffraction gratings such as in Fig. 1.3 to redirect a portion of the laterally propagating light toward a surface-normal direction for photodetection. Although this allows a thicker isolation layer under the guide, even blazed diffraction gratings can be relatively inefficient, with 30% or more excess loss typical. Other schemes utilize prisms or integrated 45-degree mirrors to realize the 90- degree coupling bends [9] [10] [11]. These schemes can introduce alignment and headroom issues. Still other approaches simply terminate the guide into a detectormesa device [12] [13]. However, these three dimensional devices are usually not compatible with planar CMOS fabrication processes. 1.4 GOALS FOR THIS WORK Based on the literature survey, it was soon apparent that a new approach to the optical tap would be required to implement practical devices on CMOS circuits. The design would have to exhibit low excess loss, and to be adaptable to fully exploit the available optical bandwidth. The tap design would also have to minimize speed limitations stemming from the optical to electrical conversion process. Any tap design would need to 8

23 be compact and compatible with standard CMOS processes if it was to be adopted by the semiconductor industry. After the basic tap design was established, other issues such as material selection, optical power equalization, and fabrication process features and limitations would need to be addressed. Low-loss polymer or hybrid polymer single-mode guides and directional couplers were the first choices for the transport and equalization of the optical signal in single mode over a series cascade of waveguide taps. Application of single mode coupler technology would allow ready integration of wavelength multiplexing Bragg reflector elements for maximum optical bandwidth utilization. Polymers or hybrid polymers were targeted for fabrication due to their low optical loss at short wavelengths, low cost, and to their excellent planarization properties on pre-processed CMOS chips. The complete tap design was to incorporate a traveling wave silicon photodetector to virtually eliminate lumped RC effects and to extract the maximum possible optoelectronic speed from the CMOS technology. The optical to electrical speed potential of commercial silicon CMOS based photodetectors has been explored in a recent review paper [14], with 1 Gbps performance reported for lumped model devices. As of the time of this writing, it is likely that these devices now could reach the 3-4 Gbps rates commonly found in the latest desktop computers. Ultimately, the goal for the technology developed in this work was the realization of a high performance optical signal distribution technology for CMOS chips, using CMOS processes, which was at the same time economically feasible. As will be theoretically and experimentally proven, the tap design that came out of this thesis work achieves all of these objectives by incorporating a unique, yet simple, vertical multimode interference 9

24 tap structure integrated with traveling wave photodetection for compact and efficient high speed optical to electrical coupling on semiconductor surfaces. 10

25 CHAPTER 2 OPTICAL WAVEGUIDE TAP DESIGN INTRODUCTION In the early stages of this work, research was done to determine the state of the art for optical waveguide tap technologies. Based on these investigations, limitations to the existing approaches were identified and a set of design constraints were assembled. This chapter starts out with a summary of this preliminary work and outlines the design constraints resulting from these studies. Later sections serve to document the evolution and basic theory of operation for the new tap design for various design configurations. More detailed simulation results are deferred to chapter 3. The final section describes how the new optical tap structure may be slightly modified to serve the other basic chip level functions of modulation and vertical interconnection for implementing complete integrated optic transceiver links at the monolithic chip level. 2.1 CANDIDATE TAP DESIGN APPROACHES There were several candidate design approaches initially considered in the course of determining an optimum optical waveguide tap for CMOS circuits. This section summarizes each approach in terms of their viability as a solution to the practical CMOS based optical waveguide tap. 1. Simple, multimode, core-shifting taps [8] offer simple fabrication and design, and would be more compatible with large core multimode fiber. However, the use of 11

26 multimode guides incurs much higher guide to substrate and circuit feature and tap well scatter losses. Multimode guides also make the approach largely impractical for highly multi-channel wavelength demultiplexing applications, nullifying most of the optical bandwidth potential inherent to optical signals. 2. Highly multimode to single mode couplers use a multimode guide of one material and size, and another single mode guide of a different material and size. Certain modes from the multimode guide will match and couple to the single mode guide, leaving the other modes to bypass the device. Such an approach would be asymmetric, and place serious constraints on material selections and geometries. Finally, the multimode guide would take up too much real estate and exhibit high scatter losses on CMOS surfaces. An example of a highly multimode to single mode coupler used for optical modulation is [15]. 3. Diffraction grating approaches such as in [16] for tapping light from integrated optical guides were ruled out as too inefficient (high excess loss), and as consuming too much chip real estate. Gratings typically exhibit 70% efficiency at best, and are on order of millimeters in length for useful devices. 4. Vertically integrated asymmetric and grating assisted directional couplers [17], [18], [19] had the potential for implementing both wavelength demultiplexing and tapping in a single multi-layered structure. However, the vertical complexity and size was deemed impractical for integration into multi-metal layer CMOS circuits, where vertical real estate can be as valuable as surface real estate. 12

27 5. Anti-resonant reflecting optical waveguide (ARROW) devices also seemed to consume too much chip area to be practical for chip level applications [20], [21] with SiO 2 and Ta 2 O 5 based devices in the 1 mm and 1 cm regime reported. 6. Termination of waveguides either directly into detector mesas or through strong evanescent coupling would not satisfy the requirements of the optical tap function, whereby a variable portion of the light must bypass the device. Mesa designs also would introduce three dimensionality to the device, adding to the complexity, and generally making it incompatible with planar CMOS circuits. Examples of detector mesa type devices may be found in [12], [13], [22], [23]. 7. Recent work on photonic band gap structures have shown promise for lateral routing of light [24], but as yet have not been considered in a vertical sense for CMOS applications. It is likely that hybrid confinement structures will evolve for on-chip optical interconnects, with photonic band gap lateral confinement being combined with refractive (dielectric waveguide) vertical confinement. Based on these research findings, a set of design constraints could now be assembled for a completely new optical waveguide tap design. 2.2 DESIGN CONSTRAINTS Based on the limitations of the established waveguide tap approaches described in the thesis introduction and in section 2.1, it was evident that a new approach was required for implementing practical taps on CMOS circuits. Based on these research findings, the design requirements for the new tap structure were as follows: 13

28 1. The optical signal is guided in single mode through a series of tap points. This affords lower scattering (cladding mode) losses and also allows integration of wavelength multiplexing elements for maximal use of optical bandwidth. 2. At each tap, an adjustable fraction of the guided light is coupled vertically into a Silicon CMOS compatible photodetector, with minimal scatter. 3. Upon exiting the tap structure, the light profile must match the single mode input guide for transport to the next tap in the series. This minimized reflection related noise and losses. 4. For maximum bandwidth, the photodetectors should be of the terminated, traveling wave transmission line type. This would ensure that the optical to electrical conversion gain-bandwidth performance would be scalable and not RC limited, regardless of the length of the detector region. 5. The device must be able to operate at an arbitrary distance from the substrate. This would allow the needed guide to substrate isolation when routing optical signals over very complex and rough CMOS circuitry surfaces. Although not required, desirable characteristics for the tap design would include: 6. For simplicity and compatibility with CMOS processes, it was considered desirable to make the device simple, and as planar and rectangular in geometry as possible. 7. The device should be stackable, affording vertical interconnection ability 8. The final tap in the series should allow for total termination of the light so as to avoid back-reflection effects. 14

29 2.3 THE VERTICAL MULTIMODE INTERFERENCE TAP Based on the design constraints of section 2.2, the first tap structures based on multimode interference (MMI) were conceived and simulated. At that time, MMI in lateral optical splitter structures was already established [25]. Indeed, current arrayed waveguide grating (AWG) wavelength multiplexer/demultiplexers (WDMs) utilize large lateral MMI sections to split up the light into n guides to serve as the n channels of the demultiplexer and for multiplexing multiple channels into a common output port guide [26], [27]. The big advantages of MMI design for such applications is the splitting up or reshaping of a single mode light profile into multiple spatially or phase separated modes in a very compact and rectangular geometry structure. The question at the beginning of this thesis study was whether the MMI principle could be used in a vertical mode on a high index substrate in an optical tap application SYMMETRIC VS. ASYMMETRIC TAP DESIGN The first design for the optical tap utilized the principle of multimode interference (MMI) in a symmetric vertical direction to split up and direct half of the input single mode light toward the substrate as shown in Fig The fundamental and higher order modes are excited symmetrically in this design. Since the higher order modes have different confinements, they propagate at different velocities through the thick multimode tap section. The phase and intensity mismatches that arise as the modes propagate give rise to the interference profile shown in the figure. After some interference oscillation length, the modes return back to approximate the input single 15

30 mode profile, and exit through the single mode output guide. The spacer layer would provide more guide to substrate isolation, and is discussed more in section Single Mode Multimode Interference Single Mode Light In Upper Cladding Lower Cladding Spacer Light Out Beam Profiles CMOS Photodetector Metal/PolySi Interconnects Fig. 2.1: Initial design of a single mode waveguide based tap based on vertical symmetric multimode interference. One half of the mode profile is directed toward the substrate. It is worth noting that although lateral MMI was well known for implementing rectangular geometry optical splitters in passive integrated optics [25], vertical operation and tap functions as yet had not been reported. Simulations indicated that this design would indeed provide useful guide to substrate optical coupling albeit with some scatter loss upon single mode recovery over high index substrates. The device was found to be very compact at about µm length typical for 1 µm waveguide thicknesses and 850 nm wavelength light. It was apparent that single mode recovery loss stemmed from the presence of the high index substrate, which made the device optical field modes asymmetric. This asymmetry would have a stronger effect on the lesser confined higher 16

31 order modes. It was also clear that only one half of the dual lobe light profile would experience any coupling to the substrate, making the upper limit of coupling at 50%. Based on the results of the symmetric MMI tap, the simpler asymmetric design of Fig. 2.2 was considered and simulated. Here, the thick tap well region was set to exactly twice the single mode guide core thickness to generate 2 modes. This new design had the benefit of reducing the number of modes, and directing more light toward the substrate for stronger guide to substrate coupling. From the figure, a single, stronger, multimode intensity lobe is present at the center of the tap well. The device can also be seen to be more planar, further simplifying fabrication. Single Mode Input Multimode Interference Single Mode Recovery Light In Upper Cladding Lower Cladding Beam Profiles Spacer CMOS Photodetector Light Out Core Thickness Tap Well Depth = 1 x Core Thickness Fig. 2.2: Final optimized design for the vertical MMI optical waveguide tap. Removal of the top portion makes the device asymmetric, with a single light intensity lobe directed toward the substrate. The vertical size is also reduced by 1/3 with this design. 17

32 Simulations indicated that tap coupling for the new design would be from 30% to 60%, depending on the spacer thickness and the polarization state of the light. From Fig. 2.2, the optical waveguide can be seen to serve as the optical analog to a metal trace. The waveguide can occupy part of an existing metal layer, or can even make up a separate optical layer. Based on studies of existing CMOS process technology, it was apparent that the tap structure would be compatible with existing CMOS via and planarization processes. In these processes, inter-metal dielectrics (IMDs) were already in use that could serve the optical waveguide fabrication requirements THE SPACER LAYER The purpose of the spacer layer was to maintain optical coupling between the tap and substrate as the lower cladding thickness was increased. A sufficiently thick lower cladding would yield the requisite isolation to route light over high roughness CMOS circuit features. Simulations indicated that adjustment of the spacer thickness could also be used to control the coupling ratio and polarization sensitivity of the tap device. From calculations, it was found that through proper selection of the spacer thicknesses, coupling for the optimized design of Fig. 2.2 could be equalized at about 50% for both transverse electric (TE) and transverse magnetic (TM ) light polarization states. Since the design involved a single optical pass, the tap device could thus be sufficiently polarization insensitive over a fairly large wavelength range. As coupling through the spacer is an interference based phenomenon, there would be many spacer thickness solutions for a given TE/TM coupling ratio. In particular, simulations indicated that TM coupling would be strongest (60%) and TE coupling weakest (30%) when the spacer 18

33 thickness was set to zero. Increasing the spacer optical thickness (index times physical thickness) on order of one quarter wavelengths of light made the coupling ratio continuously vary from 60/30 (no spacer) to 30/60, and back again. This behavior is fully documented in chapter THE EXTENDED WELL TAP In the interest of simplicity, alternatives to the spacer were sought. In cases where the first interconnect metal or polysilicon electrical interconnect layer was sufficiently thin, it was considered that a simple extension to the tap well depth beyond the 1 x core thickness configuration could be sufficient. Simulations showed that the MMI tap excess loss performance was minimally reduced at a tap well extension of one half the single mode guide thickness. This is shown in Fig The principle effect was to increase the tap oscillation or unit length by a percentage approximately equal to the well extension percentage (50% in this case). The fact that the optical mode profile was not significantly affected was attributed to the assumption that the 1 st and 2 nd order modes would dominate over the 3 rd order mode. 19

34 Single Mode Input Multimode Interference Single Mode Recovery Light In Upper Cladding Light Out Beam Profiles CMOS Photodetector Core Thickness Tap Well Depth = 1.5 x Core Thickness Fig. 2.3: Extension of the tap well thickness by ½ the guide thickness to achieve sufficient guide to substrate isolation without a spacer layer INTEGRATION WITH TRAVELING WAVE PHOTODETECTOR The optical tap function would not be complete without the capture and conversion of photons into a useful electrical signal. To accomplish this in a CMOS process, the design of Fig. 2.4 was conceived. As can be seen with this optical guide geometry, a distributed photodetector electrode pattern could be realized in a standard CMOS process. In the Fig. 2.4 configuration, channel type waveguides are shown, and represent the preferred embodiment of the vertical MMI optical waveguide tap. The detector structure is a traveling wave type, with the termination component serving as an impedance matching electrical load for maximum electrical bandwidth performance. If the optical and electrical waves are approximately velocity matched along the length of the tap, the conversion bandwidth is limited only by the transit time of carriers in the p-n junction region. The transit time would consist of drift times of minority carriers in the reverse 20

35 biased detector diode depletion regions, and of the diffusion times of minority carriers generated within a diffusion length of the depletion region. For unit tap length devices on order of um, the velocity match between the optical tap modes and the electrical strip-line is not critical. However, as lengths are extended to 500um or beyond (for more light collection), and with certain material selections such as those found in CMOS processes, the matching becomes important. For example, the optical guide material may be oxide based with a propagation index of 1.45 in the tap well region. For the electrical transmission line on silicon, the relative permittivity of the oxide guide/cladding over-layer is about 3.9 and the silicon is For a coplanar strip-line pattern, the effective permittivity would be in the 6.75 (geometric mean) regime for an electrical index of 2.6. For an f = 100GHz signal intensity rate and an L = 25 um tap length, the phase mismatch φ between optical and electrical signal intensity would be: φ = 2πf n L c (rad) [1] Where n = = 1.15, resulting in a phase mismatch of 0.06 radians or 3.45 degrees. Assuming a linear relation, and a half power (3 db bandwidth) at φ = π/4 (45 degrees), the maximum tap length would be 13 x 25 um unit lengths or 325 um. Thus, even at this velocity mismatch, it is clear that carrier transit times and metal conductivity losses would dominate. This is especially true in light of the 100 GHz design frequency, which is at least an order of magnitude higher than the electronic switching frequency currently possible in silicon technology. 21

36 TOP VIEW END VIEW Channel Guide V BIAS Spacer Electrodes Optical Coupling Region Light In V OUT Light Out Tap Well Channel Guide n + n- well p + Spacer n - well /p - substrate Electrodes Termination Depletion Region Light In Spacer Light Out SIDE VIEW Silicon p - Substrate Optical Absorption Fig. 2.4: Top and cross-sectional views of the complete vertical MMI optical waveguide tap design based on channel waveguides An alternative to the channel waveguide approach is the ridge confined guide design shown in Fig As will be discussed in chapter 3, ridge devices require more lateral real estate, and require some lateral structural modification to preserve low excess optical loss operation. The primary advantages to the ridge structure are ease of fabrication, reduced guide sidewall optical scatter loss, and the larger power handling afforded by the increased photodetection volume. 22

37 TOP VIEW END VIEW Ridge Guide Light In V BIAS V OUT Light Out Electrodes Spacer n + Optical Coupling Region n - well Spacer n - well /p - substrate Termination Ridge Guide Tap Well p + Depletion Region Spacer Light In Light Out SIDE VIEW Silicon p - Substrate Optical Absorption Fig. 2.5: Top and cross-sectional views of the complete vertical MMI optical waveguide tap design utilizing ridge guides for lateral optical confinement. 2.4 CASCADED TAP SIGNAL POWER EQUALIZATION One issue that is typical of optical taps is that optical losses accumulate along a series of waveguide taps. This can cause differential signal levels and time responses between successive taps, and can lead to gross inefficiencies for larger tap arrays. There are both optical and electrical approaches toward power equalization in a single channel (nonwavelength multiplexed) tap design. For optical equalization, it would be a fairly simple matter to increase the detector lengths (by integer unit lengths) for each successive tap [8]. However, this leads to a non-uniform design, which does not lend itself well to 23

38 CMOS circuit layouts. An electronic approach would be to simply vary the electronic gain at each tap to accommodate the variation in photocurrents. A more elegant optical equalization approach is to incorporate symmetric directional-coupled guides as shown in Fig. 2.6a. Here, the taps are placed at different points along the coupled guide depending on the degree of coupling desired. The spacing of the two guides determines the coupling oscillation spatial period. Typical coupling lengths are in the 250 to 500 µm range. For arbitrarily spaced terminating taps, segmented coupled guides may be incorporated as shown in Fig. 2.6b. If the taps cannot totally terminate the incoming light, then the design of Fig. 2.6c would be required. An advantage to all of these designs, which will soon be apparent, is that they are directly compatible with Bragg grating based WDM elements. This enables the maximum possible bandwidth to be extracted from the optical carrier. Single mode guides (a) Periodic Tap Wells (b) Arbitrary Sets coupling ratio (c) Arbitrary Fig. 2.6: Approaches for tap signal equalization over a series cascade of tap devices. (a) fixed spatial period, (b) segmented couplers with terminating taps, and (c) fixed segment lengths for non-terminating taps 24

39 The coupling ratio of the distribution structures for a series of taps follows a simple rule to maintain equal signal at each tap. For N taps, the coupling ratio C for the nth tap in the series is: 1 C n = n [ 1,2.. N] [2] N n + 1 So, the coupling ratio to the first tap would be 1/N, and to the last (Nth) tap would be unity, or 100%. For 5 taps, the first coupling ratio would be 1/5 (20%), the second 1/4 (25%), and so on. This places no termination restriction on the taps. It simply ensures that each tap will see the same amount of input power, and thus generate the same photocurrent. If each tap couples A% of input light signal power, the total light collected will then be the total number of taps (N) multiplied by the power collected by any one of the taps. Using the first tap as the simplest case, the total optical power collected (P t ) relative to the total input power P in is simply: P t = A 1 Pin 100 N N A = P in [3] 100 Where the bracketed term represents the power collected by the first tap in the series. Thus, if each tap couples A = 30% of tap input light, then 30% of the total light will be collected by N taps, with 70% of light continuing along the waveguide. 25

40 2.5 WAVELENGTH DEMULTIPLEXING Up to this point, only a single amplitude modulated optical signal has been assumed. However, the optical domain has extremely large bandwidth by virtue of the high carrier frequency (100 s of THz) of light in the near infrared wavelengths. Wavelength multiplexing/demultiplexing (WDM) refers to the distribution of many source signals into a multitude of wavelength channels. WDM is what makes optical fiber communications so effective at handling large data bandwidths. Going multi-channel on the baseline, single channel, optical tap design has two potential motivations. The most obvious motivation is to exploit more of the available optical bandwidth by transmitting multiple signals as separate optical frequencies (or wavelengths) over each waveguide. Another reason is to use wavelength selectivity to equalize optical power to each tap via spectrum sampling. As discussed previously, the single channel tap design is readily compatible with Bragg WDM elements by virtue of the single mode waveguide design. The Bragg grating based approach to wavelength selective symmetric tap coupling is shown in Fig The gratings are designed such that the reflecting Bragg wavelengths couple backward about a pivot point at roughly half the forward coupling length. With sufficient length, the outof-band forward wave couples back into the source guide to eliminate the requirement for lateral stepping of the waveguides. The grating itself is a periodic effective index modulation at odd integer multiples of one half the Bragg wavelength in the guide. Each of the grating pitches shown in the figure has a different Bragg wavelength to make up the individual channels. This periodic index could be implemented via corrugated ( relief ) type etched structures along the length of the guide or by UV laser induced 26

41 index variations in a photosensitive guide material. Grating based couplers and filters have been demonstrated in polymers [28] [29], although grating lengths tended to be in the multiple millimeter length range. These longer gratings yielded narrower optical channel wavelength spacing often on order of sub-nanometers. For CMOS based taps, wider channel spacing could be targeted, allowing much shorter gratings and better resistance to channel wavelength drift with time and temperature. Single mode guides Pitch 1 Pitch 2 Pitch 3 Tap Regions Fig. 2.7: Design for grating-based WDM waveguide taps 2.6 EXTENSION OF THE TAP STRUCTURE TO OTHER FUNCTIONS OPTICAL MODULATION The structure of Fig. 2.2 can readily be adapted for functions other than the optical tap. In general, a device that functions as a detection device may also be adapted for modulation purposes. If the absorption of the detection volume is modulated, then the light output intensity of the optical tap will also be modulated. As an example, the detection volume could be thermo-optically [49] or plasma dispersion tuned [30] index or absorption of a silicon on insulator (SOI) layer. This approach is shown in Fig. 2.8, where the length of the tap would determine the optical modulation depth for a given material 27

42 index or absorption modulation. Thermal time constants would be smaller, given the thermal isolation afforded by the SiO 2 insulator layer, making the device faster than bulk silicon based devices. Of course the method and speed of removal of thermal energy would need to be taken into consideration. Simple index and/or absorption modulation of the SOI layer could also be achieved by current injection. Single Mode Input Multimode Interference Single Mode Recovery Light In Upper Cladding Lower Cladding Spacer Light Out SiO 2 (Insulator) n and/or k modulation Si Substrate Fig. 2.8: Optical modulation scheme using either absorption or index modulation of an isolated silicon layer (SOI). A potentially higher speed modulation approach would utilize SiGe technology to achieve heterostructures suitable for electro-absorption modulation [31]. In either case, the asymmetric vertical MMI tap structure would provide the coupling between the optical signal and the modulated layer. In cases where the optical guide material can be made electro-optic, the modulation could be realized using phase induced intensity 28

43 modulation in Mach Zehnder devices. This technique has the largest modulation bandwidth potential, since slower electronic carrier absorption mechanisms are not involved. However, the trade-off would likely be device size, as the non-linear effect is usually very small, and thus requires long guide lengths to achieve sufficient phase shifts. The phase modulation based scheme is shown in Fig. 2.9, where a longer device (more MMI oscillations) would yield the higher optical modulation depth. Placing the MMI tap structure near a non-absorbing high index layer (such as Si 3 N 4 or Ta 2 O 5 ) would make the overall device length shorter for the same sensitivity. Voltage 1 = Phase 1 Light (blocked) Light In Voltage 2 = Phase 2 Light (passed) Phase 2 light Passed Light Out Substrate Modulation Voltage Signal Electrodes Phase 1 light Scattered/Blocked Light In Light Out Common (GND) Fig. 2.9: Use of the asymmetric vertical MMI tap structure with an electro-optic tap well material for optical modulation 29

44 2.6.2 OPTICAL INTERCONNECTS The scheme used to direct the light toward the substrate in the waveguide tap application also makes the approach suitable for interlayer optical interconnects at the chip or printed circuit board level. The vertical interconnection of optical layers is somewhat analogous to multi-metal electrical trace layers. However, the ability to vertically interconnect optical layers is vital for optical signal routing, since large rapid lateral deviations of optical signals cannot be achieved with refractive confined waveguide structures. The asymmetric vertical multimode interference structure can be used for vertical interconnection as shown in Fig As shown, multiple vertical MMI tap structures can be used in a stepped fashion to shift the light profile between layers over a very short distance. For the example shown, this distance is equal to one characteristic unit tap length for each layer level shift. This unit length is typically um for typical inter-metal layer dielectric materials. It is important to note that with the channel guide tap geometry, the lateral routing can be achieved in the same fashion. However, the tap unit length and the guide thickness limit branching angles. 30

45 Optical guide and Interconnect layers Metal Layers Light In Light Out Substrate Fig. 2.10: Application of the invention to vertical interconnects in a multi-metal layer electronic chip (or printed circuit board) process. For channel guide cases, this could also be readily realized in a lateral structure. 31

46 CHAPTER 3 SIMULATIONS INTRODUCTION In this chapter, detailed simulations are presented that predict the vertical MMI optical tap device performance in terms of optical loss, polarization sensitivity, wavelength sensitivity, and size. These parameters are treated for the various design configurations reviewed in chapter 2, including the initial symmetric tap design, the asymmetric tap, spacer integration, deep well tap, and vertical interconnection configurations. Most 2-D numerical simulations were conducted in Rsoft s BeamProp software version 5.0a with full transparent boundary conditions, and at Pade orders of (4, 4). The Pade order corrects for the paraxial, low index contrast assumptions of the standard BeamProp method. As a check of the 2-D BeamProp results, the tap structure was also run under Rsoft s Fullwave software, which is a more general, finite difference time domain (FDTD) numerical approach. The 3-D BeamProp simulations were limited to Pade orders of (1, 1) and thus were of limited value in terms of accuracy of the results on high index layers. However, important trends for low optical loss tap operation with a wide ridge guide structure were revealed during these runs. 32

47 3.1 DEFINITIONS OF TERMS There are several terms used in this chapter that must be defined to properly interpret the results. They include the following: Optical or Insertion Refers to the total optical loss of light passing through the device. This includes both light absorbed in the substrate and scattered throughout the structure. Excess Optical Refers only to the light lost from scattering that is not absorbed in the substrate as useful photocurrent. Polarization Refers to the polarization state of light in the guide or tap device. Transverse electric (TE) light is light electric field intensity that is oriented parallel to the plane of the substrate. Transverse Magnetic (TM) light is light electrical intensity that is oriented vertical to the substrate. Polarization Dependant (PDL) refers to the polarization sensitivity of the optical loss to polarization. Birefringence The difference in material optical index or waveguide optical propagation index between TE and TM polarized light. Indicated by n or n eff. Unit Tap Length This is the oscillation period length of the MMI tap for given layer refractive indices, thicknesses, and optical wavelength. The light intensity profile shifts to the substrate and back to the entrance/exit guide level in this distance. Taps can be extended in length by approximate integer multiples of this length to attain more optical coupling to the substrate. 33

48 Mode Recovery This refers to the recovery of the multimode profile in the tap structure to a mode profile close to that of the entrance single mode waveguide for low loss exit from the tap device. 3.2 WAVEGUIDE DESIGN Before tap device simulations could be carried out, the waveguide properties needed to be established. Upon selection of the guide materials and wavelength of operation, the single mode layer thicknesses and lateral dimensions could then be determined MATERIAL SELECTION Given the basic design of Fig. 2.3, it was clear that a planarizing material, not unlike those used for via formation in multi-metal layer CMOS circuits, would be preferred to fill the tap wells. As a result, the preliminary guide material choices were narrowed down to either polymers or hybrid polymers (e.g. flowable oxides). Hybrid polymer materials have been widely studied for their low dielectric constant properties [32], [33] and are now being used as inter-metal dielectrics in CMOS processes [34], [35]. General sol-gel hybrid polymer applications and chemical bonding theories are discussed further in [36]. These hybrid materials have also attracted interest for waveguide applications [37], [38], [39], with guide losses in the 0.1 db/cm or better regime commonly reported. One report of 0.04 db/cm HMDS based guides dates as far back as 1972 [40]. Although less compatible with high temperature CMOS fabrication processes, some polymers can withstand chip operating temperatures, making them promising for application to post-processed CMOS chips. The status of polymers in integrated optics 34

49 may be found in a more recent review paper by L. Eldada [41], with losses in the 0.01 db/cm reported for 850 nm (local networking) light, and 0.1 db/cm being reported for 1550 nm (long haul) light. Polymer based waveguides have been widely studied, with optical losses typically in the 0.5 db/cm typical [42], [43], [44]. Another advantage to polymer materials includes their capacity to be electrically poled when heated and doped with an appropriate impurity. This makes the material electro-optic, and enables modulation functions, which can in turn be used to implement transmitters. Electro-optic modulator devices based on such materials have been reported [15] with one work specifically targeting VLSI circuit applications [45]. Polymers would also have superior local and global planarization properties, especially under reflow process conditions. Unfortunately, local temperatures in excess of 100 o C (common in recent processor chips) of CMOS circuits make the use of most polymers generally unfeasible. On the other hand, flowable spin-on oxides and glasses such as Dow Corning s FoX and SiLK, and Honeywell s Flare product lines, are designed to handle these chip temperatures, and are already incorporated into major chip makers processes. The Spin on technique is one way to implement thin films of hybrid polymers and glasses. Spin on dielectrics have a number of advantages over conventional chemical vapor deposition (CVD) processes. For semiconductor purposes, the latest generation of spin-on and flowable dielectric materials are designed to (a) reduce the electrical k and permittivity values, and thus reduce lumped parasitic capacitances and transmission line propagation delays, (b) gap fill and planarize metal features as inter-metal layer dielectrics (IMD) for more reliable multi-metal layer isolation and via contacts, (c) simplify, speed up, and reduce the IMD process time, and (d) reduce maintenance costs 35

50 and yield losses associated with more conventional chemical vapor deposition (CVD), etch-back, and chemical mechanical polishing (CMP) planarization processes. From an optics standpoint, lower k and permittivity values typically translate to lower refractive indices and thus lower optical propagation delays. Porous SiO 2 layers can have the lowest k and refractive index values, albeit at the expense of increased optical scatter losses. For CMOS circuits, the biggest drawbacks to spin-on dielectric materials in general, and organic containing materials in particular, are the temperature and mechanical robustness of the layers. The introduction of organic content in the form of hybrid polymers, and the spin-on process in general, has both benefits and drawbacks for optical applications. Advantages include the potential for non-linear optical properties and index tuning, while retaining much of the temperature resistance of non-organic films. In addition, the spin on process enables the realization of smooth low scatter spin-on interfaces. The primary disadvantages include potentially higher optical absorption loss, reduced or even absence of reflow ability, and polarization sensitivity of the tensile stressed spin-on and baked films. The stress comes from the inherent shrinkage of the film volume as solvents are baked out. For the purposes of initial simulations, it was assumed that hybrid spin-on materials would be used for both the cladding and core materials. Based on review of available materials, Honeywell (then Allied Signal) 412 and Hosp series spin on glasses were assumed for the cladding material. Honeywell Flare and Accuspin 720 (methylsilsesquioxane based) materials had higher post-baked organic content, better planarization properties, and higher cracking thickness thresholds, making them better 36

51 candidates for the core and tap well materials. Ultimately, index values of 1.40 and 1.46 were assumed for the cladding and core materials respectively WAVEGUIDE DIMENSIONS As mentioned previously, there were two waveguide tap structures considered in this work: one based on the ridge guide and the other based on the channel guide. These two structures are shown in Fig Given the material refractive indices of 1.46 and 1.40, the single mode condition could then be applied: k d 2 2 π o n1 n2 < [4] 2 2 where: k o = 2π/λ o n 1 = core index n 2 = cladding index d = core thickness For n 1 and n 2 material indices equal to 1.46 and 1.40 respectively, the cut-off d value for single mode at λ o = 850 nm wavelength was 1.0 µm. This yielded simulated slab propagation (effective) indices of and for TM and TE respectively (birefringence about 0.001). The multimode tap region d value would simply be double (2 µm) to support two modes at the 850 nm wavelength. 37

52 d d well n 2 n 1 n 2 Side View Substrate/Detector H R Substrate (a) W R Tap Region Top View W T End View d d well n 2 n 1 n 2 Side View Substrate/Detector H C Substrate (b) W C Tap Region Top View End View Fig. 3.1: Two lateral confinement geometries for the vertical multimode interference optical waveguide tap; (a) low lateral confinement ridge guide case, and (b) high lateral confinement channel guide case. 38

53 For lateral confinement, the channel guide structure would have the same lateral dimension as the vertical (H c = W c = 1 µm). In the case of a ridge guide, a shallow ridge structure was to be etched to allow single mode operation over a 5 µm ridge guide width. By the same single mode constraint above, the 5 µm wide ridge would require cladding effective indices n eff of and for TM and TE light respectively for a n eff = relative to the slab guide indices. This occurred for a ridge height of about 100nm (10% of core thickness). The simulated 3-D propagation index was for TE polarized light LOWER CLADDING THICKNESS CALCULATIONS For simulating the substrate effects, the index for Silicon at 850 nm was taken as 3.75 and the n k value (imaginary part of index) was assumed as [46]. To achieve a minimum 0.2 db/mm (95.5% transmission) TE mode loss to the substrate, a minimum cladding thickness of 1.5 µm between the guide and the silicon substrate was determined through BeamProp simulation. At this cladding thickness, simulated TM mode loss was 1.15 db/mm for a polarization dependant loss (PDL) of almost 1 db/mm. Increasing the lower cladding thickness to about 1.9 µm reduced the TM loss to 0.2 db/mm, the TE loss to db/mm, and the PDL to db/mm. A plot of the simulated guide to substrate loss for TE and TM modes is given in Fig

54 1.E+01 Waveguide to Substrate Guide (db/mm) 1.E+00 1.E-01 1.E-02 1.E-03 TM Light TE Light 0.2 db/mm 1.E Lower Cladding Thickness (µm) Fig. 3.2: Plots of TE and TM optical loss to the bare Silicon substrate as a function of lower cladding thickness For the case of guide routing over electrode patterns, aluminum was assumed, which has an n of 2.5 and an n k value of 8.2 at the 850 nm wavelength [47]. Fig. 3.3 shows the ridge waveguide structure fabricated on top of a CMOS circuit with an arbitrary metal trace pattern. For simulation purposes, a continuous electrode pattern was considered at a metal height T METAL of 0.5 um. Using the same target loss of 0.2 db/mm for TE light, a minimum lower cladding thickness T LC of 1.17 µm above the CMOS electrode surface was determined via 2-D BeamProp simulations. The fact that this isolation requirement is much less than the silicon case is due to the mirror effect and poor optical coupling into the metal layer. In reality, the electrode pattern would not be continuous, and any mode 40

55 overlap of the electrodes would be scattered and lost. Together with the finite optical roughness of the electrode layer surfaces, scatter losses would dominate to make the isolation requirement similar to that for the bare silicon case. In addition, simulated TM loss was very large at about 33 db/mm, with 0.2 db/mm TM loss cladding thickness at over 2.5 um. Thus, for both bare silicon and populated cases, additional spacing between guide and substrate well beyond the 1 x guide core thickness (1 µm this case) would be required. Mode Profiles W R Light Propagation H R T UC n = 1.4 T CORE T LC n = 1.46 n = 1.4 Z Y X T METAL Metal: n = j Silicon: n = j Fig.3.3: Basic structure for the hybrid polymer based ridge guide on a CMOS circuit D TAP SIMULATIONS As mentioned previously, the software used for all simulations was Rsoft s BeamProp and Fullwave version 5.0a. For 2-D simulations, full transparent boundary conditions at 41

56 Pade orders of 4,4 and full vector modes were used for both TE and TM polarizations. This section details the initial 2-D simulation results that were used to determine tap lengths for various layer configurations. Configurations included isolated (no substrate), deep (extended) well, standard well depth, and thick spacer taps. Finite difference time domain (FDTD) simulation of the basic 2-D tap was also included to validate the 4,4 order BeamProp results for high index substrates. In all cases, launch mode profiles were based on the actual calculated mode profiles for the guide. The core index values were 1.46, the cladding index was 1.4, the wavelength was 850 nm, and where applicable, the substrate index value was j. The n k value was increased from to 0.07 in order to reduce the simulation space with minimal effect on the result. Since the substrate extended far beyond the right hand boundary, it was fair to assume that any light entering the substrate would be ultimately absorbed, and not contribute to any interference effects in the tap well. With this n k increase, the magnitude of the substrate index was minimally perturbed % from to Simulations with both and 0.07 n k values confirmed that no significant change in response would be incurred by the n k increase THE SYMMETRIC MMI TAP The symmetric MMI structure is the early version of the MMI tap, and is shown in Fig First, we consider the case of no substrate. The multimode thickness is 3x core thickness. The simulation result is shown in Fig The darker plot trace is the total power while the lighter one represents the single mode power of the upper guide. In the well region, this upper guide power will drop as the light profile shifts toward the 42

57 substrate, and increases as the light returns to the upper guide. The light propagates in the +z direction. Note that the x direction in these 2-D cases is actually the substrate surface normal y direction. In the figure, both slice and intensity views clearly show the shift in the mode profile from the single mode input profile to a dual lobe multimode profile in the tap well, and back to a single mode profile at z = 34. The tap unit length here is 24 µm. Here we see incomplete mode recovery with a transmission of 95.0% ( db). A TM mode simulation was subsequently carried out, with the result being similar to the TE response for this isolated symmetric tap case. Fig. 3.4: Simulated TE mode response of the isolated symmetric tap structure (no substrate). 43

58 Increasing the tap length by integer multiples confirmed the oscillatory nature of the MMI effect. Figure 3.5 shows the simulation result for a tap of length 4 x 24 µm unit length = 96 µm. Note there is no change in the peak transmission at each oscillation period, and that the integer multiple rule appears to be valid for this isolated tap case. Fig. 3.5: Simulated response to increasing the tap length by 4 x unit length to 96 µm. Note the regular oscillatory nature of the MMI effect. The next case was the non-isolated tap structure positioned over a silicon substrate. As expected, there was a clear difference in response between TE and TM polarization modes. The TE and TM simulation results are shown in Fig. 3.6 and 3.7 respectively. Here, the recovered mode transmission from the tap well was 75.1% (-1.24 db) and 57.2% (-2.43 db) for TE and TM modes respectively. From the figures, the total power 44

59 can be seen to gradually approach the guide mode power. This simply represents the gradual exit of unrecoverable scattered light from the simulation space, and not necessarily light that is usefully coupled into the substrate. This can be clearly seen from the intensity plot. The TM plot also shows a gradual decline in mode power in z. This stems from the coupling of TM power from the waveguide into the substrate for this 1um lower cladding thickness. This loss slope would be absent under thicker lower cladding configurations, such as with the spacer layer. Fig. 3.6: Simulated TE mode response of the symmetric tap over a silicon substrate. Note poor mode recovery. 45

60 Fig. 3.7: Simulated TM response for the structure of Fig. 3.6 From the slice plots in Figs. 3.6 and 3.7, it can be seen that the single mode recovery appears offset from the center of the symmetric tap structure. This is due to the asymmetric nature of the structure when in the presence of the high index silicon substrate. Simulation of the transmission as a function of this offset yielded the plot of Fig Here, a clear maximum in transmission, and thus minimum scatter loss, occurs for an offset of 0.3 um. The simulation results for this offset condition are given in Fig. 3.9 and Fig From the intensity plots, the scatter loss can be seen to be reduced significantly. The transmission values were 84.5% (-0.73 db) and 66.6% (-1.7 db) for TE and TM respectively. This represented a 0.51 db and 0.73 db improvement for TE and TM modes respectively. In addition, the output guide would be more isolated from the substrate, as evidenced by the much reduced TM loss slope of the guide after exiting the 46

61 tap well. Unfortunately, Fig. 3.9 indicated that much of the loss was still scatter induced, occurring beyond the tap well and photodetector region, and thus would not translate into useful signal. Furthermore, the offset of the exit guide represented a clear loss of planarity and simplicity of the design, and would be impractical for series cascades of taps. 0.0 Transmission vs. Exit Guide Offset Transmission (db) TE Light TM Light Exit Guide Offset (um) Fig. 3.8: Plot of simulated transmission as a function of exit guide offset for the symmetric tap well on a silicon substrate. 47

62 Fig. 3.9: Simulated TE mode response to a symmetric well tap with an exit guide offset of 0.3 um (30%). Note the reduced scatter loss, and increased recovered mode power. Fig. 3.10: TM mode simulation for the structure of Fig

63 Based on the results of section 3.3.2, it was considered that a lower index spacer layer could reduce the effect of the high index substrate sufficiently to eliminate the need for the exit guide offset. Adding the spacer layer would also eliminate the inherent guide loss (especially TM mode loss) from the thin 1µm lower cladding. Using a 1µm thick spacer layer with index 2.3 (about the geometric mean of substrate and guide material index values) yielded simulated results shown in Figs and Here, the transmitted powers are seen to be comparable to those for Figs. 3.6 and 3.7. Optimization of the exit guide offset to 0.2 um resulted in transmission characteristics comparable with Figs. 3.9 and Thus, the spacer layer did not eliminate the need for exit guide offset. This was also verification that the spacer layer would provide good coupling between the tap well and the substrate. The final conclusion was that, even with exit guide offset, this symmetric tap structure would not have sufficient mode recovery (excess loss) performance for the applications considered in this work. 49

64 Fig. 3.11: Simulated TE response of the symmetric tap over silicon substrate with the addition of an index matching 1µm thick spacer layer Fig. 3.12: Simulated TM response for the structure of Fig

65 3.3.2 THE ASYMMETRIC MMI TAP Based on the results for the symmetric tap structure, it was clear that an alternative design would be required to realize low excess loss MMI tap devices on high index silicon substrates. The asymmetric design of Fig. 2.2 proved to be the solution to the symmetric MMI tap problems. Fig shows simulated TE response for an isolated asymmetric tap structure with a well depth of 1µm. Here, we see excellent mode recovery, and large shift of power to the well region, as evidenced by the less than 20% mode power in the upper guide at the center of the tap well. The recovered mode power is 97.1% (-0.13 db), which is almost one half the 0.22 db loss of the isolated symmetric tap structure. However, the tap structure in the figure had a unit length of 34.5 µm, which was over 40% longer than the 24 µm long symmetric tap well case. TM response was also simulated, with no significant difference from TE response observed. The exception was the unit length, which was about 0.5 um shorter (less than 1.5%) than for the TE case. 51

66 Fig. 3.13: Simulated TE response of the isolated asymmetric MMI tap structure. Note the improved mode recovery and excess loss performance over the symmetric design of Fig. 3.4 Increasing the tap length by four times yielded the expected oscillatory behavior shown in Fig Transmission was 96.7% ( db), which represented a minimal loss increase to the unit length tap case. Simulated TM response was found to be comparable to the TE case. 52

67 Fig. 3.14: Simulated TE response to a 4 x unit length isolated asymmetric MMI tap structure For tap operation, the asymmetric tap would be coupled to a high index substrate. The substrate coupled results for TE and TM light are shown in Fig and 3.16 respectively. Here, unlike the symmetric MMI structure, we see that the asymmetric tap mode profiles are not adversely affected by the presence of the substrate. No significant offset of the exit mode can be observed. However, the shifted mode profile in the center of tap well can be seen to be offset relative to the isolated case. This is apparently due to the higher negative index mode confinement in the presence of the high index substrate. The polarization dependent coupling of the device is seen to be large with TE transmission of 80.0% (-0.97 db) and TM transmission of about 28% (-5.5 db). This translated to a PDL of about 4.5 db. The unit length was 26.2 um for TE light. Although 53

68 this length was suitable for TM light as well, the optimum TM length was about 25 um. This was attributed once again to the stronger coupling into the high index substrate. Again, as evidenced by the guide TM loss slope outside the tap region, it was clear that the 1 µm lower cladding would not be sufficient to isolate the TM guided light from the substrate. Fig. 3.15: TE mode response of the asymmetric MMI waveguide tap structure on silicon substrate. Note excellent mode recovery in monitor plot as evidenced by total (light trace) and mode (dark trace) power levels meeting at exit guide position. 54

69 Fig. 3.16: TM response of the structure in Fig Note the increased coupling of light into the substrate, at the expense of slightly degraded mode recovery. The multiple unit length case was also simulated to determine the effect of the substrate on the integer length rule. In the isolated tap case, Fig showed that 4 x the unit length had no noticeable effect on the mode recovery. This indicated a high uniformity of the MMI response along the z direction. The case of 3 x unit lengths for the asymmetric tap on substrate is shown in Fig and 3.18 for TE and TM response respectively. Here we see excellent MMI uniformity for TE light. Overall TE transmission is about 54.0 % which is close to the 80% 3 = 51% expected for the cascaded case. For TM light, the coupling into the substrate can be seen to be so large as to render MMI irrelevant (10% or -10 db transmission) after the second unit length. By the third unit length, the TM transmission is about 3.5% (-14.6 db), making this structure suitable 55

70 for termination of TM light. Taking the unit length case again and cubing yields 28% 3 = 2.2%. Thus, even for the TM case, the integer length rule seemed to apply fairly well. Fi.g 3.17: TE response for a 3 x unit length asymmetric tap on silicon substrate. Note uniform oscillatory behavior along propagation axis z 56

71 Fig. 3.18: TM response of the structure of Fig Note strong coupling of over 96% (about 15 db), making this structure ideal for termination of TM light THE EXTENDED WELL ASYMMETRIC TAP As discussed in section 3.2.3, a minimum lower cladding thickness of 1.5 um would be desirable to minimize the guide to substrate excess TE mode loss to 0.2 db/mm. The extended well structure of section was thus considered to achieve this lower cladding condition without the insertion of a spacer layer. The TE result for the 1.5 µm (1.5 x guide thickness) well depth isolated tap case is shown in Fig The lengthening of the tap to 43 µm (from 34.5 µm for standard well depth) represented an almost 25% longer device. For this isolated case, the excess loss was also very high at 1.08 db (78% transmission) compared to about 0.15 db for the standard well depth case. 57

72 This could be attributed to the degraded MMI performance in the extended tap well. The extension of the well without the presence of the substrate introduced more modes that adversely affected the asymmetric MMI performance. TM simulation results were found to be comparable to the TE case. Fig. 3.19: Isolated extended well tap structure TE response. Note the poor mode recovery and high excess loss for this isolated device case. Placing the extended well tap structure over the high index substrate gave markedly better results than for the isolated case. The responses for TE and TM light are given in Figs 3.20 and 3.21 respectively. The transmission can be seen to be 75.8% for TE (-1.20 db) and 25.0% (-6 db) for TM light. TE mode recovery shows 75.8% out of 79% total power, or 0.18 db mode recovery loss. Similarly, TM mode recovery shows 25% mode 58

73 power out of 28% total power, or 0.5 db mode recovery loss. Recall that for the standard well depth case, mode recovery loss was not evident, especially for the TE mode. The 79% TE and 28% TM total powers closely matched the 80% and 28% powers seen for the standard well depth case. This indicated that the substrate couplings were very comparable to the 1 x guide thickness case. Fig. 3.20: TE response of the extended well, asymmetric MMI tap structure on silicon substrate. Note vastly improved mode recovery over the isolated case of Fig

74 Fig. 3.21: TM response of the structure of Fig About 25% transmission is observed The trend of increased excess loss of the extended well tap structure was confirmed by simulating the structure for various well depths. The results are given in Fig The mode powers ( mode P ) are the net optical powers coupled into the exit guide of the tap out of the total power (designated total P ) available. Here we can see a more drastic recovery loss effect for the TE mode as the well depth increases. As a balance, a value of 1.5 x guide thickness (1.5 µm this case) was chosen for these extended well devices. At this depth, the guide isolation loss for TE light was previously calculated to be 0.2 db/mm, and the TE recovery loss was found to be about 0.15 db. From Fig. 3.22, TM loss is seen to be fairly linear over well depth, which is a result of the different mode structure of the less confined, highly substrate coupled TM light. The tap unit length can be seen to increase approximately in a 1:1 relationship to the well depth multiple. For 60

75 example, 50% increase in well depth (depth = 1.5) from the 1 x guide width case can be seen to result in about a 50% increase in the tap length. Transmission (%) Recovery Excess (db) Tap Unit Length (µm) TM excess loss TE excess Effect of Well Depth TE total P TM total P TE mode P TM mode P TE length TM length Well Depth (x guide thickness) Fig. 3.22: Plots of TE and TM transmission and excess loss responses as a function of well depth. The third plot shows the approximately linear increase of tap unit length as a function of well extension. 61

76 3.3.4 SPACER LAYER THICKNESS EFFECTS In cases where more substrate isolation is required, such as in cases where TM light must also be supported, a spacer layer must be inserted between the tap well and the substrate. Inserting a roughly index matching layer of index 2.3 between tap well and substrate was expected to yield the simplest coupling layer. It was expected that the coupling response would be spacer thickness sensitive. For these simulations, the thickness of the spacer was varied from 0 to 10 um to determine the effects of spacer thickness, and whether an optimum thickness existed. The TE and TM results for a 2 µm spacer layer are shown in Figs and 3.24 respectively. At this spacer thickness, the TE and TM responses are seen to be nearly equalized at 48% for TM and 51% for TE light. For thicker spacers, the spacer had to be extended in z well beyond the tap length so as to complete the coupling of light trapped in the spacer into the substrate. In general, a spacer extension in z of 3 to 4 times the spacer thickness was found to be suitable for the coupling of spacer residual light energy. The case of a very thick spacer of thickness 10 µm is shown in Fig Here, the presence of residual light in the spacer beyond the tap well is clearly seen. 62

77 Fig. 3.23: TE response of the asymmetric MMI tap on silicon with a 2 µm spacer layer. Fig. 3.24: TM response of the structure in Fig Note the nearly equalized polarization response for this 2 µm spacer case. 63

78 Residual Power in Spacer Fig. 3.25: Case of very thick 10 µm spacer. Residual light in the spacer can be clearly seen. The power plot confirms the completion of this energy absorption along z into the substrate as the total power level meets the guide power level. As expected, there was an oscillatory behavior in tap coupling as a function of spacer thickness. TE and TM light exhibited different transmissions over spacer thickness, as could also be expected given the large PDL and birefringence of the substrate coupled asymmetric MMI tap structure. The behavior for 850 nm light is shown in Fig. 3.26, where it is clear that specific thicknesses can exist whereby the polarization dependence can be zero at the given wavelength. Using the spacer thickness = 2 µm case, the transmission over wavelength is plotted in Fig Here it can be seen that with the 64

79 spacer, the device is somewhat sensitive to wavelengths supported by the waveguide. By making the spacer a multilayer dielectric stack composed of high and low index materials, the tap device could possibly be made wavelength sensitive enough for coarse wavelength division multiplexing applications. From Fig. 3.27, it can be seen that with no spacer, the device is very insensitive to wavelength. Spacer thickness effects were also simulated for the deep well (1.5 µm well depth) tap structure. Both spacer thickness and wavelength sensitivity results were very similar to Fig. 3.26; the only difference being that the levels were shifted down by 0.22 db (5% drop). 65

80 Spacer Thickness Effect on Transmission 90 Transmission (%) TE Mode TM Mode Spacer Thickness (µm) Transmission (%) TE Mode TM Mode Spacer Thickness (µm) Fig. 3.26: Plots of TE and TM transmission as a function of spacer thickness for the standard well depth asymmetric MMI tap structure on a silicon substrate. Note presence of polarization equalization solutions for thicknesses less than 2 µm. 66

81 Transmission Dependance on Wavelength Transmission (%) TE Mode - No Spacer TE Mode - 2 µm Spacer TM Mode - 2 µm Spacer TM Mode - No Spacer Wavelength (nm) Fig. 3.27: Plot of wavelength and polarization sensitivity for case of no spacer, and for case of near-equalized TE and TM spacer thickness of 2 µm VALIDATION OF THE 2-D BEAMPROP RESULTS The BeamProp technique is commonly used for low index contrast and paraxial (low propagation angle) problems. Since the substrate index was very high relative to the guide and tap well in these simulations, it was thus important to verify the general MMI behavior of the 2-D BeamProp results. For this, Rsoft s Fullwave 5.0a software was used, which represented a rigorous finite difference, time domain (FDTD) approach. A 1 µm spacer was modeled for this case. Qualitative comparison of Fullwave intensity results can be made in Figs and 3.29 below. In the Fullwave simulations, the intensity peaks of the light waves in space can be seen, with the overall mode profiles and power levels matching the BeamProp case. As a reminder, note from the plots that x 67

82 represents the vertical direction, which is the y direction for 3-D models. Thus, Ey and Hy represent TE and TM light respectively. From the intensity plots, the MMI behavior was confirmed, and preferential TM light substrate coupling could also be observed. The interference in the spacer layer was clearly visible in the TE case, with 4 modes visible for this 1 µm spacer layer thickness case. Fig. 3.28: FDTD 2-D simulation of TE response of the asymmetric vertical MMI tap 68

83 Fig. 3.29: FDTD 2-D simulation of TM response of the asymmetric vertical MMI tap. Note increased coupling of TM light relative to the TE case of Fig As another check of the BeamProp results, the Pade order was decreased from 4,4 to 3,3. Any resultant change in the tap length would give an indication of the sensitivity and accuracy of the model. For the tap on the silicon substrate, the tap length did not change between Pade Orders of 4,4 (maximum available)) and 2,2. For the case of the isolated (low index contrast model) tap case, no change in tap length occurred between Pade orders of 4,4 and 1,1. This indicated that Pade orders of 2,2 and 1,1 would be suitable for substrate coupled and isolated tap cases respectively D SIMULATIONS The results of the 2-D simulations proved that the tap could work for the slab guide case. The goal for the 3-D simulations was to verify the basic multimode interference 69

84 (MMI) tap operation under both vertical (y) and lateral (x) confinement. The general channel and ridge tap 3-D geometries, representing high and low lateral confinement respectively, have previously been introduced in Fig Due to the reduced Pade orders of 1,1 available for 3-D simulations, the high index silicon substrate and electrodes were generally not included in the 3-D models. The high index substrate was not required to observe vertical MMI operation in the 2-D simulations. This was also assumed to be the case for the 3-D simulations. To model coupling over a high index substrate, a high loss spacer layer was included in some of the 3-D simulations. This spacer layer yielded a much lower index contrast model for more rapid and accurate simulations. In the case of such an absorbing spacer, the tap coupling was compared to the 2-D case, with an absorbing lower index spacer taking the place of the high index Silicon substrate. The coupling into such an effectively infinite spacer layer was expected to approach the average value of the oscillations seen in Fig. 26 for large spacer thicknesses. These values were 65% for TE light, and about 38% for TM light. Since TM light could not be simulated with the 3-D model in Rsoft s 3-D BeamProp 5.0a software, only TE response could be compared between 2-D and 3-D models BASELINE 2-D SIMULATIONS To compare 2-D and 3-D results, the 2-D TE light simulations were run at equal Pade orders of 1,1 and non-vector mode so as to match the conditions of the 3-D simulations. Fig shows TE simulation results for the isolated (no substrate) case and Fig 3.31 shows the result for the absorbing spacer substrate case; both being run under the reduced 70

85 simulation parameter values. Note that the x dimension will become the y dimension for the 3-D models. Fig. 3.30: 2-D simulation of the isolated tap under reduced Pade order of 1,1 and nonvector mode. Behavior is essentially identical to the earlier Fig result. 71

86 Fig. 3.31: 2-D TE simulations of the absorbing spacer/substrate at reduced simulation parameters of Pade Order = 1,1 and vector mode = none. The unit length of the isolated tap was found to be 34.5 µm and thus was not affected by the reduced parameters. For the absorbing spacer case, the spacer/substrate index was set at 2.3, and the spacer n k value was set to 0.1. Simulating the absorbing spacer/substrate case under full 4,4 Pade order and full vector mode resulted in a 2-D tap unit length of 26.5 µm, while the reduced parameters yielded a 27.5 µm length. The coupling transmission and losses in all cases were found to be unchanged with the new simulation parameters. Transmission for the isolated tap was seen to be 97.2% (-0.12 db). As can be seen from the 2-D results of Fig. 3.31, the tap transmission for the absorbing spacer/substrate case was 66.9% (-1.74 db), which agreed with the expected value of about 65% for TE light. 72

87 D CHANNEL TAP SIMULATION For the 3-D simulations, the cases of isolated and non-isolated channel guide tap structures are shown in Figs and 3.33 respectively. The lower cladding thickness was 1 µm, causing some guide to substrate loss in the non-isolated case. The same simulation grid and other parameters were used as in the 2-D cases of Figs and The 3-D channel tap lengths were 39 µm for both isolated and non-isolated cases. This was in stark contrast to the 2-D tap lengths of 34.5 µm and 27.5 µm for isolated and nonisolated cases respectively. The 3-D model transmission was 92.6% (-0.33 db), with 5.4% (-0.24 db) of exit mode recovery loss. It was assumed that the higher confinement of the channel tap case made the 3-D model results so different from the 2-D slab case. Mode Recovery Fig. 3.32: 3-D simulation of TE light in the isolated, channel guide tap. Note higher mode recovery loss and 13% longer tap length over the 2-D case. 73

88 Mode Recovery Fig. 3.33: 3-D simulation of TE light in the channel guide tap over absorbing spacer. Note 42% longer tap length over the 2-D case, with comparable transmission levels, and slightly higher mode recovery loss D RIDGE TAP SIMULATION The ridge guide based tap results for TE light in both isolated and non-isolated structures are shown in Figs and 3.36 respectively. Note that the tap well width of 15 µm was considerably wider than the ridge width of 5 µm. This lateral adjustment to the 3-D geometry was found to be critical to maintain low recovery loss in the low lateral confinement ridge guide tap. The isolated 3-D ridge tap length was 34.5 µm, which was identical to the length for the 2-D slab case. This was not surprising, given that the low lateral confinement would make the shallow ridge structure much closer to the 2-D slab case than the channel guide case. The transmission of 95.4% and mode recovery loss of 74

89 4.2% (0.19 db) were similar to the 2-D case of 97.2% transmission. The case of the high index absorbing spacer yielded a 3-D ridge tap length of 35.5 µm, which was in contrast to the 27.5 µm length for the 2-D case. However, the length was closer to the 2-D case than was the 39 µm long channel guide tap. Once again, this was assumed to stem from the more 2-D slab-like weak confinement of the ridge device. Transmission of the absorbing spacer substrate ridge tap case was 65.3%, with a recovery loss of 3.7% (0.16 db). The 2-D case was 66.9 % transmission, with nearly negligible recovery loss. Thus, differences in 2-D and 3-D transmission results could be attributed primarily to 3-D mode recovery loss. From these results, it was apparent that 2-D BeamProp models at higher Pade orders could be used to predict ridge confined device response on high index substrates by adding a 3-D mode recovery loss factor of about 0.16 db. Mode Recovery Fig. 3.34: 3-D BeamProp simulation of TE light in the isolated ridge guide MMI tap 75

90 Low Mode Recovery Fig. 3.35: 3-D BeamProp simulation of TE light in the ridge guide MMI tap over the absorbing spacer substrate. Note about 65% transmission, which compares well with the 2-D case of Fig The extended well tap was also modeled in 3-D for the case of the absorbing spacer. The result was a tap length of 50 µm, a TE transmission of 60.67% (-2.17 db) and a 0.20 db recovery loss. This represented a length extension of 50/35.5 or 40.8 % relative to the standard tap device of Fig WELL WIDTH EFFECT IN RIDGE GUIDE TAPS As mentioned previously, the well width of the ridge guide tap needed to be wider than the ridge width in order to minimize excess lateral mode recovery loss. The mechanism behind this loss is readily apparent in Fig for the case of well width 76

91 (W T ) = ridge width (W R ). Here, the lateral evanescent portions of the light field are clipped upon entry into the deep but narrow tap well. Upon exiting the tap well, the outer evanescent portions are out of phase with light that experienced MMI, resulting in high mode recovery loss. Increasing the tap well width W T to 2W R vastly improved the mode recovery, as shown in Fig The W T = 3W R case of Fig represented little improvement over the 2W R case at the cost of increased chip area. A plot of transmission and mode recovery loss is given in Fig Here, it can be seen that mode recovery and transmission and size are optimized at W T = 10µm ( 2W R ). High Mode Recovery Fig. 3.36: Poor 3-D mode recovery loss of an isolated ridge guide tap with tap well width W T = ridge width W R = 5 µm. 77

92 Low Mode Recovery Fig. 3.37: Case of W T = 2W R. Note improved mode recovery. No change in Mode Recovery Fig. 3.38: Case of W T = 3W R. Note only slight improvement in mode recovery. 78

93 Well Width Effect on Ridge Tap Transmission (%) Mode Power (%) Total Power (%) Recovery (db) Optimum Width = 2W R Recovery (db) Well Width ( x Ridge Width) Fig. 3.39: Plot of transmission and mode recovery loss over well width of an isolated ridge tap structure. For minimum tap size, optimal width is about 2W R (10 µm) 3.5 CONCLUSIONS AND FINAL DESIGNS From the 2-D and 3-D simulation results, designs could be completed for ridge and channel guide based test devices. Confidence in the dimensions of fabricated devices stemmed from the agreement of the Beam Prop results with the Fullwave FDTD results and with the low sensitivity of the results at the Pade orders used. Given the index values of 1.40 for upper and lower claddings and 1.46 for core layers at 850 nm wavelengths, the designs for various configurations are given in Table 3.1. Note that these results are taken from ridge tap simulations. Channel tap devices would exhibit similar values but at slightly higher (+0.05 db) excess losses. The waveguide lower cladding thickness would need to be at least 1.5 µm to limit maximum TE mode excess guide losses to 0.2 db/mm. TM modes would require lower cladding thickness of at least 1.9 µm to achieve the same 79

94 0.2 db/mm guide to substrate loss. Ridge taps would have ridge width W R = 5 µm, ridge height H R = 0.1 µm and well width W T = 2W R = 10 µm. Spacer layers of index 2.3 and variable thickness would be used to adjust coupling of the tap as shown in Fig. 3.26, as well as providing more isolation between the guide and substrate. Table 3.1: Summary of tap designs with estimated performance Standard Well Tap Extended Well Tap Parameter Isolated Device On Silicon Isolated Device On Silicon Tap Depth (µm) Tap Length (µm) TM NA 36.5 TE NA 38.0 Core Thickness (µm) 1.0 Cladding Thickness (µm) TE TM >1.5 µm for 0.2 db/mm guide loss >1.9 µm for 0.2 db/mm guide loss Estimated Ridge Device Coupling (db) Estimated Recovery (db) TE NA TM NA TE TM

95 CHAPTER 4 WAVEGUIDE TAP FABRICATION INTRODUCTION The simulation results of chapter 3 provided theoretical validation for the vertical multimode interference tap structure. The primary goal for subsequent experimental work was to prove the coupling behavior and low excess loss of the asymmetric vertical MMI tap structures on silicon substrates both with and without a thick isolating spacer layer. In this chapter, the various test structures and mask design are described. Then, the evolution of the fabrication process is reviewed. The final section details the final process used to achieve test devices, and tabulates the physical properties of the finished devices. 4.1 MASK DESIGN For the basic optical waveguide tap structure, only two layers were required; the tap well layer, and the waveguide layer. Both layers constituted etch steps and were designed for positive resist masked etching processes. The overall mask pattern used is shown in Fig. 4.1 below. As can be seen, one half of the 0.1 µm resolution chromium mask contained the well pattern, and the other half contained the waveguide pattern. This was a cost reduction decision that took advantage of the symmetry of the patterns. The 4 chromium on quartz mask was made by Photo Sciences, Inc, in Torrance, CA. The layout of the mask was done in RSoft s CAD Layout package that comes with their BeamProp software. The layout was then exported into DXF format for mask fabrication. 81

96 Test structures comprised cascaded in-line taps (Fig. 4.2), segmented coupler taps (Fig. 4.3), and continuous coupler taps (Fig. 4.4). Cascades varied from 1 device to 5 series devices for each type. This allowed a measure of the effects of cascading taps, as well as lending a more accurate measure of the average loss of single tap devices through loss slope averaging. This is described more in the test and analysis chapter 5. Between each of the test device/guides were reference waveguides, which would serve as the basis for absolute loss measurements of the tap devices. For the coupler devices, the coupling ratios for each tap in cascade were chosen as discussed in Chapter 2. For N taps in cascade, the first coupler was designed to collect 1/N portion, the second 1/(N-1), and so on. A sin 2 (γz) model was used to convert directional coupling ratios to actual coupling lengths. By reducing the guide spacing, the coupling lengths of the segmented couplers were one half the lengths for the continuous couplers. Specifically, the ridge waveguide gaps were 2.1 µm for segmented couplers and 3.3 µm for the continuous ones. This resulted in the coupler lengths shown in Table Ridge widths were 5 µm, while channel guides were 1 µm. Tap well lengths for in-line ridge tap devices were two groups of unit lengths 26 µm and 36.4 µm. For channel devices, they were 25 µm and 35 µm. Coupler taps required termination of light, so the well lengths for these devices were set to 4 x the group unit length. This was 104 µm and µm for ridge devices, and 100 µm and 140 µm for channel devices. For TE light with 70% transmission per tap unit length, this would yield = 24% transmission, or 76% termination. With appropriate spacer layer selection, TE transmission could be reduced to 50% per tap unit length, yielding or 94% (>12 db) termination. TM light would experience stronger termination, with 30% 82

97 transmission resulting in 0.8% transmission or 99.2% (> 20 db) of termination. Tap well lengths were chosen so as to allow testing of both isolated (longer well) and non-isolated (shorter well) tap devices. The longer well devices also doubled as test devices for the non-isolated 50% extended well tap, which would require a tap length about 1.5 x the standard 25 or 26 µm unit length. 4 Mask Zoom Section Mirror Copy Mirror Axis Ridge Wells Channel Wells Ridge Guides Channel Guides Fig. 4.1: Overall view of the mask Layout 83

98 5 Series Taps 4 Series Taps Reference Guides Detail of Tap Device 3 Series Taps Well Length 2 Series Taps Tap Device Guide Width Fig. 4.2: Composite pattern showing ridge guide test devices for cascaded in-line tap devices. Note aspect ratio is x:y = 1:10. Detail of Tap Device Guide Gap Fig: 4.3: Test structures for segmented ridge guide tap couplers. Aspect ratio is 1:10 84

99 Detail of Tap Device Guide Gap Fig. 4.4: Test structures for continuous coupler devices. Aspect ratio is 1:10 Table 4.1: Coupler lengths for ridge guide based tap couplers Coupler Type Segmented Continuous Num Taps Length 1 (µm) Length 2 (µm) Length 3 (µm) Length 4 (µm) Length 5 (µm)

100 4.2 PROCESS DESCRIPTION GENERAL PROCESS FLOW The general process flow for fabrication of tap structures on silicon substrates consisted of the following steps: 1. If applicable, deposit spacer layer. 2. Deposit the lower cladding layer. 3. Pattern and etch tap wells in the cladding layer 4. Fill tap wells with guide core material. Planarize. 5. Deposit guide core layer 6. Pattern and etch core layer for channel (deep etch) and ridge (shallow etch) guides 7. Deposit upper cladding if applicable 8. Cleave bars of device guides for testing PROCESS EVOLUTION Initially, it was planned that the waveguide materials be made entirely from spinon dielectrics. The initial process approach is shown in Fig Here, a re-flowable spinon material would be used to fill and planarize the tap wells. Re-flow would be achieved by heating to the appropriate flow temperature. 86

101 1. Spin deposit lower guide cladding 4. Spin-reflow-cure core material p + n + n - well p - substrate p + n + n - well p - substrate 2. Reflow and full cure p + n + n - well 5. Pattern & RIE etch ridges. Spin & cure upper cladding. p - substrate 3. Pattern & RIE etch tap windows p + n + n - well p + n + n - well p - substrate p - substrate Coupler guide Tap guide Fig. 4.5: Process envisioned for fabrication of tap structures on device populated silicon substrates Samples of Allied Signal and Honeywell were attained (Honeywell merged with Allied Signal Advanced Materials). These included AccuGlass 512, 412, 311, HOSP, AccuSpin 720, AccuFlo 13EL spin-on organic polymer, and Flare Contacts for these products were: AlliedSignal Inc. Honeywell Electronic Products Advanced Microelectronic Materials Honeywell Electronic Materials 3500 Garrett Drive 1349 Moffett Park Drive Santa Clara, CA Sunnyvale, CA Phone: (408) Phone: (408) Fax: (408) Fax: (408) alliedsignal@supersite.net info@electronicmaterials.com Web: The published and measured characteristics of the materials are listed in Table 4.2. In the table, cracking thickness thresholds t crack indicate the maximum thickness of baked 87

102 films before stress induced cracking on Silicon substrates would occur. This is primarily due to shrinkage of the film upon baking, and the ensuing tensile film stress that develops. This stress would also likely result in birefringence of the films in optical waveguide applications. As can be seen from Table 4.2, there is an approximate relation between film shrinkage, stress, and cracking thresholds. From an optics standpoint, the non-clear materials had more organic content, and thus would be expected to have higher optical loss at the near-ir wavelengths targeted for this work. However, baking could remove much of the organic elements, such as in the case of 720, which purportedly becomes more like bulk glass as the final bake temperature exceeds the specified 270 o C. This was evident during spin and bake cycles, whereby soft-baked films exhibited no visible light thin film interference effect, while post baked films did. Table 4.2: Material properties for spin-on products acquired for this work. Values in ( ) are values measured by the author for hot plate baked films Product Material n 630nm n 850nm ε r t film (µm) t crack (µm) T bake ( o C) Planar 311 siloxane Local HOSP 4000 HOSP 9000 Flare 913EL Methylsiloxane Methylsiloxane Methylphenylsilsesquioxane Hybrid Siloxane organic Hybrid Siloxane organic Organic Polymer Organic Polymer 1.39 (1.392) (1.389) Local Local (1.501) Local (1.380) 1.37 (1.400) Shrink (%) Stress 120 MPa Low 21MPa Low 21MPa Very Low Liquid Color Clear Clear Clear Light yellow (1.376) Local - 50MPa clear (1.381) Local - 50MPa clear (1.667) (1.657) Local MPa (1.626) (1.614) N/A 150 Regional N/A Low gold Light red 88

103 Early experiments to achieve the film refractive index and thickness values were carried out. Spinning of films was done in a class 1000 clean room under a laminar flow and exhaust station. To attain index values of 1.40 and 1.46, varying proportions of 720 were added to the HOSP and T-12 products. Initial measurements of visible (630nm) refractive index were carried out via a Gaertner L-126B ellipsometer at incidence angles of 70 degrees. More accurate spectroscopic results were attained using a JA Woolam Co. VASE variable angle spectroscopic ellipsometer. A Nanospec AFT 200 was also used in conjunction with a Tencor Alpha step 200 stylus profilometer to verify the results. Later, very accurate 630 nm index and thickness measurements were made using a Metricon Model 2010 prism coupler based instrument. This instrument offered an absolute accuracy (+/ ) better than the single wavelength ellipsometer, while being a considerably faster technique than the spectroscopic ellipsometer approach. Index and thickness results for various spin and baked solutions of the materials on 2 and 3 <100> oriented silicon wafers are given in Fig Here, it could be seen that the index values followed a somewhat linear relation to the mix ratios. Spin speeds were typically in the range of 3000 to 5000 RPM for 30 seconds. It was found that the Flare product had too high a refractive index and furthermore could not be mixed with the lower index materials to reduce the index. High loss of the Flare and 13EL products was indicated by the deep coloration of the liquid state, and by the published higher organic content of the materials. Together with the fact that these products were primarily used in sacrificial CMOS processes (planarization), not as permanent layers in the CMOS structure, Flare and 13EL were eliminated as waveguide material candidates. 89

104 SOG Film Index Tuning Refractive Index (at 850 nm) % 720 HOSP 9000 to 720 0% = um 33% = um 50% = um 100% = 0.861um HOSP 4000 to 720 0% = um 33% = um 100% = 0.607um 412/720 4K/720 9K/ to 720 0% = um 33% = um 50% = um 100% = um Concentration % (vs 720) Fig. 4.6: Index and thickness results of various mixes of spin-on polymer materials Since target total waveguide structure thicknesses were in the 3.0 to 3.5 µm range, it was evident early on that cracking would be an issue, especially with the HOSP and 311 based films. Hazy films for these samples were confirmed to be cracking under a microscope. Flaking near the 3 silicon wafer edges was also common for thick HOSP based films. This was not surprising, given the published 1 µm cracking threshold for this product line. Attempts to slow down the baking process did not improve the cracking. The T-12 product fared better, with crack free film thicknesses in the 2-3 µm range being confirmed. Since the films were known to be tensile stressed after baking, it was considered that a lower compressively stressed spacer layer could improve the cracking threshold. A thick compressively stressed layer of tantalum pentoxide was ion beam 90

105 assisted, e-beam deposited on the silicon wafer. However, cracking was not significantly improved. One paper by A.S. Holmes, et al [39], described the formation of very thick spin on glass channel waveguides through repeated spin and rapid thermal anneal steps to build up the thick films of SOG without cracking. The film indices of the cured films were reported as 1.43 for un-doped TEOS and TPOT sol-gel based spin-on films, suggesting a lower density relative to bulk glass. Titanium doping was used to achieve index values as high as Rapid thermal processing of spun on films were reportedly carried out via a 4 second ramp to a critical temperature of 1075 o C, held for 10 seconds, then cooled over 60 seconds. Varying the anneal temperature yielded a full range of stress in the film from positive (compressive) at temperatures 50 o C over critical to negative (tensile) at temperatures 50 o C below the critical temperature. This was evident in the curvature of the substrate after processing. At the critical RTA temperature, the sample was virtually flat. Based on the results reported in that work, various 412 and 720 coated 3 silicon samples were treated as described in the paper under an oxygen ambient. The RTA model was a Heatpulse 410 RTA. The result was severe pitting of films, perhaps the result of trapped micro-bubbles or impurities in the films. This made the films not viable for waveguide applications, and the RTA approach was abandoned. In addition to the cracking issue, early spin experiments indicated that the film qualities of mixed materials were sensitive to solution preparation, dispensing conditions, and spin parameters. Particularly troublesome were spots near the center of the spun wafer film, and streaks extending radially from the center of the sample. Spinning at high ramp (acceleration) and speed tended to produce center spots, while slower acceleration and speed caused radial streaking. A balance occurred by using a high acceleration (<

106 sec) at a lower final spin speed of about 3000 RPM. However, even this setting generated spots and very light streaking at times. Even pure material spins of 720 would yield light streaking at times. Initially, the materials were dispensed using syringes and a 0.2 µm PTFE based filter. After consulting Allied Signal, it was discovered that PTFE filters can remove the surface tension reducing surfactant which also acted as a flowing agent. Removal of the surfactant could potentially cause the observed streaking. However, spinon attempts of HOSP products with no filter tended to generate too many particle defects and streaks for waveguide quality films. Spin-on of pure 720 films with no filter consistently yielded the best results. In an attempt to utilize the index tuning of mixed materials, Polypropylene 0.2 µm filters were procured based on the vendor recommendation. Results with the new filters did not significantly improve the streaking of the mixed material films. Other attempts were made to stabilize the mixtures by baking them at 65 o C for 30 minutes under nitrogen purge. Film quality results were inconclusive. Vacuum chamber treatment to out gas the mixtures were carried out both overnight and for 30 minute periods with similarly inconclusive results. Combinations of the two treatments were also inconclusive. The only approach that seemed to work consistently was the spin-on of pure 720 materials without filters. The resulting films occasionally had particle contaminant defects, but were otherwise high quality films. It was concluded that although the materials could be mixed to tune the refractive index, it would not be possible to maintain spin coated optical guide quality mixed films for this work. The final process would now have to address both the cracking threshold issue and the lack of ability to tune the index of the film through material mixing. Absent a successful RTA or other stress reducing approach, the 3+ µm waveguide layer stack 92

107 simply could not be made entirely from spin-on glasses. It was decided that a high quality lower cladding of SiO 2 would be deposited by thermal oxide, CVD, or by physical deposition, such as sputtering or ion-beam assisted e-beam evaporation. The planarizing 720 material of index 1.49 to 1.50 would be used as the well filling, planarizing, and waveguide core material. Another layer of SiO 2 could always be applied if an upper cladding was desired. At this point, the mask was already fabricated, and was based on an index delta of 0.06 (1.40 and 1.46 for cladding and core respectively). Using 720 as the waveguide core and tap well material, the cladding index would thus need to be about Thermal oxide locked in the index too high at about 1.46, making it unsuitable as a cladding material. Sputtering attempts resulted in compressive high index SiO 2 films with index 1.48, which was also too high. PECVD processes could be used, but availability and straightforward repeatable film index control of the ion beam assisted e-beam system ultimately made it the method of choice. By reducing the plasma (ion beam) source energy, SiO 2 films of index 1.44 and thickness of 1.0 µm (standard well depth) and 1.5 µm (extended well depth) were readily achieved. In addition, the e-beam system had a Tantalum source available for deposition of higher index Ta 2 O 5. In the 850 nm near IR regime, deposited tantalum pentoxide films have an index of about 2.09, which was close enough to the 2.30 value of chapter 3 to make it a suitable spacer layer for the tap devices. The final process used for test devices in this work is shown in Fig Here, the 720 SOG films were not re-flowed to planarize the tap wells. Rather they were simply polished back mechanically via slurry of 0.1 µm alumina polish, and more SOG layers were added to form the waveguide layer. A brief chemical mechanical polish (CMP) of 0.05 µm colloidal silica yielded optically smooth surfaces on both the SOG and SiO 2 93

108 surfaces. Thicker overall films of spin-on material were achieved simply by repeated spin and bake steps. The lower harder SiO 2 layer acted as a polish stop layer to the softer 720 material. To enhance the layer stop effect, the 720 was not fully cured before polishing, making it even softer. An ultrasound clean was carried out after the polishing step, and the film was fully cured at high temperature before proceeding to the waveguide layer. In cases where higher planarization was desired, the well fill/polish/cure step was repeated before depositing the guide layer. 1. Ion beam assisted e-beam Lower guide spacer/cladding layers Cladding (SiO 2) Spacer (Ta 2O 5) if applicable Silicon substrate 2. Pattern and wet etch tap windows Tap Well 4. Planarize - Polish Back SOG Silicon substrate 5. Guide Core Layer - Spin & cure SOG Silicon substrate Silicon substrate 3. Well fill Spin-on/bake SOG 6. Pattern & RIE etch ridges SOG Layer Tap guide Ref guide Silicon substrate Silicon substrate Fig. 4.7: Pocess used for fabrication of tap device test structures on silicon substrates. An upper cladding was also applied to one sample. 94

109 Early tap well etch experiments using RIE and a gold mask resulted in damaged lower claddings due to presence of SiO 2 and gold layer pinholes. Before this problem could be solved, a more serious problem arose; that of the inability to achieve suitable selective etch of the SiO 2 over the silicon substrate. The RIE process consisted of a CF 4 :O 2 gas mix at 20:5 flow ratio, 175W power, and 100mT chamber pressure. The RIE machine used was a Plasmatherm 790. The RIE etch rate of SiO 2 films varied from 2 um per hour to 4 um per hour, depending on the plasma energy of the ion beam source during deposition. As a result, punch through of SiO 2 film into the lower silicon substrate occurred for some samples, causing a very defective lower cladding. In the case of the tantalum oxide spacer, it was even more unclear how to selective etch SiO 2 over the tantalum in a dry etch process. Given the lack of selectivity of the RIE etching and the pin-hole problem, it was considered that simple wet etching, such as with a buffered oxide etch (BOE), could be employed using a standard photo-resist etch mask. The lateral dimensions of the ridge tap devices were about 26 and 36 µm by 10 µm wide. After isotropic wet etching of the tap wells, the well lengths and widths could be expected to increase by 1 to 1.5 µm (the lower cladding thicknesses) in each direction. Based on the simulation results of Chapter 3, a wider tap of 12 to 13 µm would simply result in a lower excess loss device. A 2-3 µm longer tap represented about a 10% increase, which could be compensated simply by adjusting the well depth. Making the lower cladding slightly thicker by 10% of the original well depth would result in a 10% longer unit tap length. For the case of a 1 µm deep tap well, the lower cladding of 1.1 µm would result in about a 28.6 to 29 µm device. The same 0.1 µm depth extension would give a 2.4 µm increase to the unit tap length of a 95

110 36 µm long x 1.5 µm well depth tap. In any case, chapter 3 indicated that at near optimum unit tap length, the transmission performance would not be very sensitive to perturbations of the tap length. Ultimately, a highly dilute solution of buffered oxide etch was used to achieve fairly repeatable etch rates with extremely high selectivity between SiO 2 and both the silicon substrates and tantalum oxide spacer films. After the well etch, planarization, and waveguide layer, the waveguide core layer was patterned using standard positive photolithography and a dry RIE etch process to form the shallow ridge guides. The RIE etch of the ridge pattern was based in part on the results reported for dry etching of spin-on glasses in [39]. After etching, the Photo-resist was removed in acetone and DI rinsed. This also had the secondary function of removing any organic material at the RIE damaged SOG surface. Due to the limitations of the lithography equipment available and the issues related to RIE etching of tap wells, the 1 µm channel guide devices were not fabricated. After the formation of ridge devices, an upper cladding of SiO 2 was deposited on one of the samples. However, an increase in point defects occurred, drastically reducing the yield of low loss waveguides. This was apparently due to the energy of the ion beam assisted e-beam process. However, it was most likely due to the observed presence of flaring of small glowing particles being ejected from the plasma source. These would readily embed and damage the softer spin-on 720 film. Some presence of flaring always occurred to a more or lesser degree. A well maintained plasma source would reduce this effect. However, another more serious issue with the upper cladding was poor cleaving performance. The sample with the upper cladding tended to result in facet region flaking or otherwise damaged waveguide facets. Samples not treated with upper claddings 96

111 yielded excellent cleave performance. In an actual production level semiconductor process, such facets would be precision diced and polished, typically with the protection of a temporary upper block layer. Here, the samples were simply snap cleaved by using a combination of carbide scribe and knife tip. It was considered that an upper layer of SOG such as the 412 or HOSP products could be applied to form the upper cladding. However, simulations and test results indicated that good optical test results could be attained without the yield threatening upper cladding, as so it was omitted on the remaining samples. Further details of the fabrication process are given in the next section DETAILED PROCESS DESCRIPTION Here, the specifics of the fabrication process are described. 1. Silicon Wafer Preparation - 3 single side polished wafers of p or n doped <100> silicon were degreased using a sequence of: 30sec each running DI, Isopropyl, Methanol, Acetone, Methanol, Isopropyl, DI and N 2 blow dry. - Wafers were then cleaned using a standard RCA-1 clean procedure. 1:1:5 Hydrogen peroxide, Ammonium Hydroxide, and DI water were mixed and heated to 75 o C. A 20 minute dip in this solution was followed by a 1 minute dip in HF:DI 1:40 solution to remove native oxide. DI rinsed for 30 seconds and N 2 blow dry. 97

112 2. Spacer and Lower cladding deposition - Cleaned wafers were mounted on 300 mm diameter by 7 mm thick BK-7 glass wafers using high temperature vacuum tape. - The entire assembly was mounted into a Leybold Optics APS 1104 ion beam assisted e-beam evaporation system with the wafers pointed downward. The general deposition procedure involved pumping down and baking out the chamber to a pressure in the 5E-7 mt range, followed by elevating the samples to a temperature of about 130 o C via a resistive coil radiative heater. - The ion beam plasma gun source was set to clean mode for 5 minutes. For the spacer layer case, tantalum pentoxide was deposited next from e-beam evaporation of a pure tantalum source. The Plasma source gases contained sufficient oxygen to fully oxidize the tantalum at the wafer sample surfaces. The SiO 2 lower cladding layer was then deposited at reduced plasma gun settings so as to achieve the desired refractive index of 1.44 at 850 nm (slightly higher at about in visible). Coating thicknesses were controlled via crystal thickness monitor. Dummy runs were carried out to calibrate the refractive index and thickness of layers. A Metricon Model 2010 Prism Coupler instrument was used to measure thickness and refractive index in the 630 nm wavelength regime. Index accuracy for the instrument was specified as ±.0005 in a 20 second step. Run parameters are given in Table

113 Table 4.3: Deposition parameters for layers in this fabrication work Parameter Clean SiO 2 Ta 2 O 5 (spacer) O 2 Flow (sccm) Ar flow (sccm) Discharge Volts (V) Discharge Current (A) Bias Voltage (V) Coil Current (A) Chamber Pressure (mt) 3.0E-4 4.4E-4 5.0E-4 - For the case of isolated tap samples R1 and R2, a 1 µm layer of SiO 2 was deposited and tap wells were later etched. This was followed by another deposition of SiO 2 of about 1.6 µm, forming 1 µm deep tap wells isolated from the substrate by 1.55 µm of lower cladding material. Samples R3, R4, and R5 had 1.55 µm of SiO 2 directly on the silicon substrate. Sample R6 had 6 µm of Ta 2 O 5 spacer followed by 1.55 µm of SiO 2. 99

114 3. Tap Well Patterning and Etch - Samples were degreased and dehydrate baked as in the part 1 initial wafer preparation. - Shipley 1811 photoresist was dispensed by polypropylene syringe (no o-ring) through a 0.2 µm PP filter and spin coated at 4000 RPM for 30 seconds with a 6 second spread cycle at 200 RPM. By the manufacturer spin curve, this yielded a 1.1 µm film of resist. - Resist was soft baked on hot plate under a laminar flow hood at 90 o C for 1 minute. - Aligned mask to wafer flat of sample. One half of the sample was exposed to the chromium mask using a Karl Suss MJB3 4 mask aligner with a 350 W mercury arc lamp. Exposure time was 13 seconds. The waveguide half of the mask was masked using aluminum foil. - A brief 5 to 10 second dip in a dilute developer solution 5:1 of DI:351 to partially develop the pattern. DI rinse and N 2 blow dry. - Expose other half of the wafer for 13 seconds. - Develop sample for 20 seconds to fully develop both patterns. DI rinse and N 2 blow dry. - Hard bake on hot plate at 120 o C for 15 minutes. Resolution of the entire process was about 1 µm. - Brief RIE O 2 ash sample. RIE was a Technics Series 85-RIE with 30KHz source and operated in manual mode. Power = 100 W, O 2 flow = 10 sccm, pressure = 200mT, time = 30 seconds. This step ensured clean etch surface in the tap well windows. - Samples were dipped with agitation in a 10:1 DI:BOE solution for up to 80 seconds. The BOE portion consisted of a solution of 10:1:1 ratio DI water: Ammonium fluoride (NH 4 F): Hydrofluoric Acid (HF). This resulted in about a 200:1 dilute solution of DI: HF. 100

115 The buffering was to preserve the photoresist pattern for extended etch times. Fortunately, the less dense SiO 2 (from e-beam evaporation at reduced plasma gun energies) etched much faster than bulk or thermal SiO 2, minimizing the exposure of the photoresist to the etchant. No degradation of the photoresist pattern was observed. Etch rates were typically 1 µm per minute. To avoid over etching, the process was broken up into multiple etch steps (10 second dips and check after an initial 40 second dip). Total etch times were about 80 seconds. To check selective etch over the tantalum pentoxide spacer, one edge of the R6 sample was dipped in the BOE solution for 10 minutes, with no visible etching occurring. - After etching, samples were stripped of photoresist using acetone, and inspected under Nomarski microscope. Well dimensions were recorded, with typical ridge well widths of µm as expected for the 10 µm pattern well width. 4. Tap Well fill - After etching and photoresist removal, samples were dehydration baked for 15 minutes at 120 o C on a hot plate. - The samples were then cooled in air and placed on the wafer spinner under a laminar flow hood. Spinner settings were a 100 RPM spread cycle for 5 seconds, followed by a rapid ramp to a spin speed to 1700 RPM for 60 seconds. This low speed would result in spun films of thickness approaching 0.5 µm. This minimized the number of spin cycles required to achieve the greater than 1.5 mm films needed to planarize the tap wells. It also tended to reduce the number of defects. 101

116 - 720 spin on polymer was dispensed through a syringe and a 6 long, 1/8 ID polypropylene tube in the following manner: The 1/8 tube was thoroughly cleaned in Methanol, then acetone rinsed and N 2 blow dry. The tube was fitted to the syringe, and positioned vertically in the bottle of 720. The liquid was slowly drawn into the 1/8 tube by syringe, without letting the liquid enter the syringe. The liquid was then dispensed onto the static wafer on the spinner, starting outside the center, and working inward until the wafer central region was completely coated. The spinner was then engaged. While the spinner was running, the 1/8 tube was immediately taken off and completely cleaned and dried again for the next cycle. This minimized the chance of dry particulate formation in the tube, which would in turn result in particle defects in later film spins. - After spinning, the sample was hot plate baked at 100 o C and 190 o C for 1 minute each before application of the next layer. At least four layers of 720 were deposited to ensure complete well fill. This resulted in layer thicknesses of at least 2 µm. Cracking threshold was not an issue for layers thicker than 2 µm, since the films were not yet fully cured. - After all layers were deposited and baked, an acetone soaked lint free cloth was used to scrub/remove the 720 film starting just outside the central tap well features and all the way to the wafer edge. This minimized the required amount of polishing of the 720 SOG films in the next step. 5. Planarization In preparation for polishing, wafers were mounted to a 100 mm diameter x 5 mm WMS- 02 glass sub-mount via a thin layer of Gel-Pak temporary adhesive sheet as shown in Fig The Gel-Pak sheet on the optically flat glass sub-mount allowed quick, safe, and flat 102

117 attachment and reattachment of the samples. This was as opposed to hot wax, which would require even pressure and temperature across the sample to ensure a globally flat surface. Another advantage of the Gel-Pak was that thin shims of aluminum foil of arbitrary shapes could be inserted under the wafer to selectively raise the sample surface in areas where more polishing was desired. This allowed control of the uniformity of the polish, which was important to prevent dishing (over polish) or under polishing of tap wells. Initially, concentric round disks of foil of increasing diameter were applied under the center of the sample to achieve more polishing at the center of the sample. This compensated for the tendency of a sample to polish more at the edges, and yielded a more uniform result. 103

118 Sample SOG Film Gel-Pak Film Polished Flat Glass Sub-mount SIDE VIEW Steel Weight and Hand Hold Sample Aluminum foil shims under sample Tap Wells Area removed of SOG TOP VIEW SOG Film Fig. 4.8: Mounting of 3 wafer sample in preparation for polishing - The assembly of Fig. 4.8 was then manually polished on a 12 diameter MultiTex TM soft pad part number PMT12A-10 from South Bay Technology, Inc. ( which was adhesive mounted on a flat polishing glass plate. Other pads were attempted, but only the MultiTex TM pad resulted in smooth unscratched surfaces. Because of the lateral (rectangular) aspect ratio of the tap wells, the best result 104

119 for minimizing dishing of the wells was a more linear polish pattern, as opposed to the more conventional figure eight pattern. This is shown in Fig Polish Pattern used in this work Tap Well/Guide Orientation Standard Figure eight Polish Pattern Polish Pad Fig. 4.9: Approximately linear polish pattern used for this work. Tap well orientation was maintained over the stroke pattern to minimize dishing of the rectangular tap wells. The primary polish slurry was a purely mechanical polish using 0.1 µm deagglomerated alumina suspension part# ASD01-16 from South Bay Technology. Medium pressure of about 5 lbs was applied to ensure a level polishing surface. After each 300 to 600 strokes, the wafer was DI rinsed and inspected, and new aluminum shims were inserted as 105

120 necessary to maintain uniform polish. A razor blade was used to slowly and gently separate the wafer from the Gel-Pak film for insertion of shims. The outer area of the wafer was never shimmed so as to maintain a good adhesion of the sample to the submount. Since this outer area was removed of SOG earlier, no preferential polishing was required there. - After clearing the upper SOG film from all the tap well patterns, the polish pad was forced water cleaned and DI rinsed. Colloidal silica 0.05 µm suspension part # CS1-16 from SouthBay Technology was then applied, and the sample was chemical mechanical polished for 300 strokes to ensure an optically smooth surface. Forced water and final DI rinse and N 2 blow dry followed. - Before advancing to the next step, the samples were cleaned in a warm (65 o C) Ultrasound soap bath for 5 minutes, DI rinsed, then rinsed in warm Ultrasound DI bath for 5 minutes. This was followed by a final DI rinse, Methanol rinse for 30 seconds to ensure removal of any damaged organic SOG surface and/or soap, DI rinsed for 1 minute, then N 2 blow dried. - Samples were then full cure baked using 100 o C and 200 o C hot plate steps for 1 minute each, followed by a 5 minute hot plate bake at 290 o C. To avoid thermal shock, the sample was quickly moved from one plate to the next. After the final 5 minute bake, the sample was very slowly removed from the hot plate, and thus allowed to cool slowly over a 30 sec to 1 minute period. - For most samples, the entire planarization procedure was repeated so as to ensure maximum planarization of features. In the case of sample R4, the silica CMP polish was increased to achieve dishing of the entire SiO 2 cladding areas around the tap wells (

121 µm dishing over a µm radius from the well region). This yielded test devices with 1 µm tap well depths and guide to substrate cladding thicknesses of 1.5 µm. - After the samples were planarized, they were inspected under a microscope and also scanned using a Digital Instruments Dektak 3 profilometer. Results for the various samples were: R1, R2 - Good planarization. Less than 0.1 µm tap well dishing R3 R4 - Good planarization. Less than 0.1 µm tap well dishing - Dishing of cladding region around well. Waveguide cladding 1.5 µm far from well, and 1 µm at well edge. This 0.5 µm variation of the cladding thickness occurred over 50 to 60 µm, making vertical bending loss of the waveguide insignificant. R5 R6 - Same result as R4 - Good planarization. < 0.1 µm dishing of tap wells Since the bulk of the polishing was done using 0.1 µm alumina slurry, the 0.1 µm or less tap well dishing was expected. By using the 0.05 µm silica slurry as a finishing polish, it was expected that any well edge discontinuity step would be in the 0.05 µm to 0.1 µm range. This could be verified with a finer scan such as by atomic force microscopy. Fig shows the results for a long (terminating) ridge guide based tap well. Dishing from polishing can be seen at the center of the well in both the white light interference image on the left, as well as the Nomarski image on the right. Fig shows a single unit length tap well after polishing. Here the dishing is reduced due to the reduced lateral aspect ratio of the well. Fig shows the case of the channel guide based (narrow) tap well, which shows no dishing at all. 107

122 Waveguide Direction Fig. 4.10: Earlier ridge guide based tap well. 4 x unit length x 13 µm wide. Note color change in center of well, indicating presence of polish dishing. Nomarski image confirms dishing of both well and surrounding area. Waveguide Direction Fig. 4.11: Ridge guide based (wide) planarized tap well. 1 x unit length x 13 µm wide. Width is about 13 µm 108

123 Waveguide Direction Fig. 4.12: Channel guide based (narrow) tap well. No dishing observed. About 3 µm wide. 6. Waveguide Core Layer Deposition - The waveguide core layer was applied in the same way as the tap well fill, with only two spin coats at RPM for 60 seconds each being used to attain a 720 SOG thickness of 1 µm. The 720 SOG film thickness and refractive index on bare silicon test substrates for these spin conditions were previously checked by ellipsometer and later more accurately determined using the Metricon prism coupler. - The films were then hot plate baked at 290 o C for 5 minutes. 7. Waveguide Ridge Pattern and Etch - After the core layer was applied, samples were spin coated with 1.1 µm of Shipley 1811 photoresist and soft baked as described in step 3. - Samples were exposed 13 seconds to waveguide patterns and developed one half wafer at a time as in step 3. - Hard bake of resist 15 minutes at 120 o C hot plate under laminar flow hood. 109

124 - Samples were loaded and etched one at a time in the Technics Series 85-RIE etcher. Gas flows were: CHF 3 = 5 sccm, Ar = 5 sccm, O 2 = 2 sccm. These values were derived in part from the work reported in [39]. RF power was set at 40 W, and the operating pressure was typically 185 to 190 mt. Etch time was 70 seconds to etch 1000 Angstroms (0.1 µm) of cured 720 SOG, translating to an etch rate of 14.3 Angstroms/second. Dummy etch runs of SOG samples on bare silicon substrates were always run before etching the real samples. The ellipsometer was used to check the film thicknesses before and after etching steps. - Resist patterns were stripped in acetone, and the samples were then rinsed in methanol and DI water before final N 2 blow dry. A final bake at 200 o C ensured no trapped water in the SOG film. 8. Upper Cladding A test run of upper cladding on a dummy patterned sample was carried out with 1.5 µm upper cladding of SiO 2 being applied using the Leybold Optics 1104 e-beam deposition system. Attempts to cleave this sample indicated cleave edge flaking and damaged end facets. Subsequently, sample R5 was cleaved before upper clad coating. End facets were much improved, but an increase in the number of surface defects was observed during optical test of the waveguides. This drastically reduced the yield of useful devices, and so the other samples were not coated. Simulations and test results on air upper cladding devices indicated that no significant penalty would be incurred for this slight asymmetry in the waveguides. In the interest of maximizing yield, remaining samples were left without upper cladding. 110

125 9. Cleaving The samples were cleaved to form three device test bars R#-3, 4 and 5 as shown in Fig The R#-3 sample served as a measurement for the waveguide loss. By measuring the transmission of two different waveguide lengths, the distributed guide loss could be estimated. R# -2 R#- 5 Cleave 2 R#- 3 D C B A Cleave 3 R#- 4 A B C D R# -1 Cleave 5 Cleave 4 R#- 6 First Cleave Fig. 4.13: Sectioning of the samples after completion of ridge waveguide tap structures Cleaving was carried out by gently scribing a notch at the edge of the wafer where cleaving was to start. A shock wave was applied to this damage center in the cleave direction by the back side of a steel carpet knife blade. Under reflected light, it could be seen when cleaving had started. Then the wafer was placed over a straight edge steel ruler, with the cleave line aligned to the ruler edge. Gently pushing down on one part of the sample over the edge resulted in a clean cleave of the sample. End facets were inspected under microscope. All cleaves came out very sharp, with no end facet damage, as can be 111

126 seen in Fig Samples were then arranged in 3 plastic sample carriers, with Gel-Pak strips applied to the container bottoms to keep the samples from shifting and damaging each other. Microscope images of tap devices are shown in Figs Fig. 4.14: Sample cleaved ridge guide facets 112

127 Fig. 4.15: Completed ridge tap device alongside a reference waveguide Fig. 4.16: A segmented coupler tap device. Note slight extension of well under source waveguide. 113

128 Fig. 4.17: A continuous coupler tap. Although gap is larger than Fig. 4.17, well is aligned to center of well, causing some overlap of well with source waveguide. 114

129 CHAPTER 5 DEVICE TEST AND ANALYSIS INTRODUCTION After the fabrication phase, the primary goal of the test phase was to measure transmission characteristics of the tap structures and to compare them to theory. The first section of this chapter describes the test set-ups. Section 5.2 describes the models used for theory comparisons. These models had to include the real world effects of tap well dishing, edge discontinuities, and tap well lateral misalignment. The relative effects of each of these are given by way of examples. Section 5.3 tabulates the test results for the various tap structures and compares them to theory. 5.1 TEST SET-UP DESCRIPTION The most basic and important test was the insertion loss test. Using reference waveguides as background levels, the tap device losses could be accurately determined without concern for waveguide (launch) and collection losses. The set-up for insertion loss is shown in Fig Here, a single mode fiber coupled, temperature controlled, 10 mw, 840 nm Fabry Perot laser diode optical source (model QFLD S from Qphotoincs, L.L.C., was used in conjunction with the Agilent 81624A large area photodetector and prism polarizer to test insertion loss for TE or TM light. Detector averaging time was set to 500 ms. Using a Melles Griot model 06 DLD205 laser diode driver and an Ando 6317B optical spectrum analyzer (OSA), the 115

130 spectral width and wavelength of the laser was confirmed at about 2 nm and 840 nm respectively for a pump current of 70 ma, and a thermistor resistance of 10KΩ. A separate output fiber affixed to the 20x output objective lens was manually positioned in place of the 20x free space collection for measurement of the spectral response via the optical spectrum analyzer (OSA). A second photodetector module with fiber adaptor was use to optimize the output fiber collection before measurement by the OSA. Spectral response of the 6 µm spacer tap devices was seen to be essentially flat over 50 nm sweeps. For polarization dependant measurements of the isolated tap devices and waveguides, a Protodel Fiberlogix mechanical polarization controller (3-loop type) was used in conjunction with the Melles Griot 03-PTA-003 Taylor Glan wide band, near IR polarizing prism to maximize the polarization state to TE or TM light. Source light was directly measured from the input fiber by imaging the fiber tip onto the photodetector. For qualitative tap scatter measurements and visible images, a Duma Optics, L.L.C. SPOTCCD-IR-009 near IR sensitive CCD imaging head was used in conjunction with Duma s Spot-on CCD software ver. 2.0 and video capture PCI card ( For Visible images, the IR CCD device was replaced by a JAI CV- 950 camera attached to the s-video port of the Duma video capture card. The mechanical stages were Newport 460P series linear stages and nested Melles Griot 07 GON 001 and 07 GON 002 manual goniometers. High resolution micrometers were used for the sample stage x and y adjustment. The entire test set-up was mounted on a Thorlabs T3648A 4 x 3 x 2 hollow optical breadboard. Photos of the test set-up are given in Figs. 5.2 and

131 Fig. 5.1: Test set-up for insertion loss and spectral response tests of fabricated optical ridge waveguide tap devices 117

132 Meiji Microscope and CCD camera PC running Duma Spot-On video capture SW Ando 6317B OSA Agilent 8164A Chassis and detector electronics Optomechanical Set-up Fig. 5.2: Optical test set-up for fabricated ridge tap devices 118

133 20x Objective and output fiber Laser Polarizer And Detector Polarization Controller Sample Fig. 5.3: Close-up of optical test set-up. 119

134 5.2 FABRICATED DEVICE MODELING The optical measurements were carried out on the in-line single and cascaded ridge tap devices shown previously in Fig The layout is repeated in schematic form in Fig The 2-D model for the ridge tap devices included polish step and dishing effects as shown in Fig Guide dishing reduced the thickness or depth of the tap well, and effectively reduced the unit length of the device. The well step s well was the sharp discontinuity resulting from the selective polish of the well SOG fill material and the harder SiO 2 cladding. The effects of this step were to increase the vertical mode tap well insertion and recovery loss as well as to reduce the effective unit length from well depth reduction. The 2-D simulated effects of s well are given in Fig. 5.6, with a 0.07 µm step inducing a loss of 0.26 db relative to the no step (s well =0) case. As per Metricon prism measurements, core and cladding material indices were taken as 1.49 and 1.44 respectively at the 840 nm wavelength. OUTPUT FACET D C B A Guide #13 ZOOM VIEW Guide #1 INPUT FACET TOP VIEW OF CLEAVED CHIP Reference Guides Tap Wells First Tap Row Fig. 5.4: Schematic layout of tap and guide devices measured in this work. A-D group assignments are also shown. 120

135 t core L well t ridge Air Upper Cladding d wel s wel d guide Core t clad Lower Cladding Light Propagation t well t spacer Spacer Silicon Substrate Fig. 5.5: Tap model for fabricated devices. Note polishing related step (s well ) and dishing (d well, d guide ) parameters Transmission (db) Effect of Polish Step on Device TE Mode (db) TM Mode (db) Polish Step (mm) (µm) Fig. 5.6: Effect of the well polish step parameter s well on transmission loss for the isolated tap case. 121

136 Tap device well lateral dimensions and alignment for each group were checked under the microscope. Alignment of the guide to the well was found to have some impact on the excess loss of the ridge devices. Relative alignment comparisons are shown in Fig D BeamProp simulations indicated a ridge tap lateral mode recovery excess loss relative to the 2-D slab case. Specifically, a 3-D isolated ridge tap with well width 13 µm yielded 91.6% transmission (-0.38 db) for good and fair alignments, while the 2-D slab case simulation yielded 92.9% ( db) transmission. Poor alignment yielded 90.8% ( db). Thus, for isolated devices, a 0.1 db lateral mode recovery loss for poor aligned devices relative to the 2-D slab case could be assumed, and 0.06 db lateral recovery loss could be assumed for good to fair aligned devices relative to the 2-D slab case. 5 µm Ridge Guide 13 µm Well width Good (no offset) Fair (~1 µm offset) Poor (~3 µm offset) Fig. 5.7: Alignment criteria for ridge tap devices 122

137 5.3 FABRICATED DEVICE TEST RESULTS DATA FORMAT AND DEFINITIONS OF TERMS Measurements of device transmission (-loss) were taken for ridge device groups of Fig Raw data are given in spreadsheet format in Appendix A. Samples were labeled in the appendix according to the following scheme: Sample piece# - group guide# (example: R2 3 D 1) where groups A and D had the same tap length of µm, and groups B and C were longer taps at about µm. As such, in the appendix, super groups A,D and B,C were arranged together for statistical purposes. The appendix data are defined as follows: L Rel (Relative ) measured loss for each device-populated guide relative to the average of the two adjacent reference waveguide power measurements. L PT (Per Tap ) relative loss divided by the number of taps in the guide. L Inc - (Incremental Tap ) - relative to the previous (one less tap) loss value. For the case of the 2 cascaded taps (device #6), is relative to the average of the single tap cases (devices #2 and #4). L ST (single tap loss) - average of the two single tap (devices #2 and #4) measurements. L casc (average cascade loss) - average of the cascaded per tap losses (i.e. excludes single taps). LA Inc (average incremental loss) - Average of L Inc values (includes single taps) Slope (db/tap) Linear fit slope of relative loss data Offset (db) offset for loss data linear fit (y intercept) 123

138 5.3.2 DATA ANALYSIS PARAMETERS To accurately calculate tap loss values from the raw data, there were two issues to consider. One issue was the effect of a single tap on cladding mode transmission. For reference guides, more overfill from the fiber input could have been transmitted through lower cladding modes than the case of when a tap well was present. Thus, an artificially larger loss per tap could be measured for the single tap measurements. Recall that the input fiber was a single mode 6-10 µm fiber core, and these guides were 1 µm thick. For cascaded taps, the opposite problem to the single tap case could occur, whereby the output spot power into the detector would begin to be dominated by scattered cladding modes. This was present in the form of weak or very streaky spots visible on an IR sensitive card. An artificially larger transmission could be measured in these cases. To generate a weighted average of the single tap and cascaded tap losses, the following average slope parameter LSA was defined: LSA = Lcasc + LAInc + Slope 3 [5] where the LSA and L ST values then served to represent lumped cascade and single tap loss values respectively. Averaging these two values gave the net loss parameter LNet., which represented a more balanced and potentially more accurate typical tap loss. Polarization dependant loss effects were measured for the isolated R1 sample (t clad = 3 µm). The other samples (t clad = 1.5 µm) did not sufficiently support the transverse magnetic (TM) polarization mode to enable accurate polarization dependant loss measurements. It should be noted that for normal tap implementation, the lower loss 124

139 transverse electric (TE) mode would be used. In prior work, the TM mode was found to be useful only where total termination of the light into the tap device was desired. IF TM light is desired, a spacer layer in the tap well region would be used to isolate the upper guide from the substrate and to control the polarization dependant coupling of the tap device. Interpretations of experimental data and simulation model values were also based on a visual check for defects and well alignments and on Dektak measurements of guide dishing (d g ). In cases where defects were visible or where the data value varied much more than a standard deviation from the norm, the data point was excluded. In cases where well alignment was poor, a 0.2 db correction was applied. Although 0.1 db was indicated by simulations for misalignment, experimentally the value was seen to be considerably larger, perhaps due to roughness of the well sidewalls. Specific data points and group alignments are addressed in the appendix data, while Table 5.1 summarizes fabricated device properties in terms of measurable dishing, thickness, and material parameters. Table 5.1: Summary of physical and material properties of test samples SAMPLE t well (µm) d guide (µm) n spacer index t spacer (µm) Top cladding Comments R1,R2 1.0 < Air Isolated taps for excess loss tests R3 1.5 <0.1-0 Air Extended well depth case R Air Standard well depth case t well = t core R5 1.5 < Extended well with over cladding* R Air Extended well with thick coupling spacer layer *Poor yield from over cladding nullified test results - no spacer layer present 125

140 5.3.3 WAVEGUIDE LOSS ANALYSIS Reference waveguide loss measurements were taken for TE as well as TM modes where appropriate. Sample R3 indicated 2.1 db per 10.5 mm = 2 db/cm or 0.2 db/mm. This was exactly equal to the predicted guide to substrate loss 0f 0.2 db/mm for TE light in chapter 3. This indicated that minimal material absorption and scatter loss was present in the test guides. Of course some error could be present in the form of cladding mode transmission differences between short and long guides, but it is likely that this would be a very small contribution. For TM light on the same R3 sample, the difference between reference guide TE and TM transmission was 6.6 db per 6.5 mm or about 1 db/mm. This followed the Fig. 3.2 simulation results for TM light exactly, confirming the virtually zero material and scatter loss of the waveguides. R6 guides exhibited 4.95 db per 7 mm or about 0.7 db/mm TE mode guide loss, while simulation results predicted the same 0.7 db/mm for TE modes on 6 µm thick Ta 2 O 5 spacers. Total sample R3 TE mode loss of the guides was typically 12 db for an approximately 13 µm fiber to guide input facet gap and 17 mm long guides. This placed the net fiber insertion and collection loss at typically 12 db 17 x 0.2 or about 8.6 db. As a check of the guide loss, it was necessary to compare the net guide transmission to the net loss expected for this set-up. The sources of insertion and extraction loss from the guide were: 1. Gap (Input fiber to guide separation) 2. Mode Mismatch (input fiber to guide) 3. Numerical Aperture Mismatch es 4. Fresnel (reflection ) losses at input and output guide facets 126

141 For mode mismatch and gap loss, a 3-D BeamProp model was simulated assuming a fiber mode field diameter of about 3.5 µm. This was determined by the single mode normalized frequency condition: 2 π NA a V = [6] λ with a = step index core radius. Fiber NA for 1% mode field width was measured using a Photon beam scanning profiler to be 0.20 at 850 nm for a divergence angle of 11.5 degrees (half cone angle). NA for 1/e 2 was measured to be Taking the NA value of 0.20, this implied a core diameter of 2 a = 3.25 µm. At a 13 µm fiber to guide separation, the increase in mode size from the fiber would be related to the acceptance angle θ a which in turn was related to the numerical aperture NA, ambient medium index n o, and guide indices n core and n clad by: 2 core 2 clad NA = n sin( θ ) = n n [7] o a For the fiber NA of 0.20, the fiber acceptance and output beam spreading angle was 11.5 degrees (half cone angle). Using the tangent of the angle, the increase in the mode radius at the guide facet for a 13 µm gap would be calculated from tan(θ) = r/z, yielding a r of 2.64 µm. The net mode size increase would then be 5.28 µm for a total mode size of about 8.8 µm. A 3-D model in BeamProp was simulated, and yielded a mode size mismatch loss of 3.3 db. 127

142 For numerical aperture mismatch loss, the following model was used from [48]: 2 R NA L NA = 10log (db) [8] NA T where: NA R = receiving guide (ridge guide) NA NA T = input guide (fiber) NA Setting n core and n clad to and for the guide vertical structure yielded an NA y of This was larger than the input fiber NA of 0.17, so no NA mismatch loss would be incurred for the vertical (y) mode profile. For the shallow 0.1 µm etched ridge structure, the lateral confinement effective indices were calculated as in chapter 3 to be and for cladding and core regions respectively. This yielded a ridge guide lateral NA x of 0.107, and an NA mismatch loss L NA = 5.43 db for the fiber NA of NA mismatch between the input fiber and 20x objective and guide and objective (for total power measurement) were taken as zero, since the 20X objective NA of 0.4 matched or exceeded NA values of both fiber and guide. Thus the net lateral NA mismatch loss was equal to the lateral NA mismatch loss of 5.4 db. Fresnel loss was taken as reflection loss from index mismatches between fiber and ridge guide effective indices and air. Facets were typically slightly angled with respect to guides and input fibers so as to avoid etalon induced standing wave effects in the guide and in the fiber to guide gap. Taking the reflection as: 2 n1 n2 1 n1 + n2 T = [9] and using the effective index of the guide as about 1.46, reflection loss at each ridge guide facet would be only about 0.16 db each or 0.3 db. 128

143 Collecting loss terms, the total guide insertion and extraction loss would be 5.4 db db db = 9.0 db. This was reasonably close to the experimentally determined value of 8.6 db, especially considering the high sensitivity of the NA mismatch equation. NA measurements are often error prone, with 10% errors common. Assuming a slightly lower fiber NA of 0.19 would place the NA mismatch loss at 5.0 db for a total loss of 8.6 db. Thus, the analytical approximation confirmed the low measured waveguide loss DATA ANALYSIS RESULTS L ST and LSA values for the device groups of samples R1-R6 (excluding R5, due to damage from the upper cladding run) are given in the wafer sample maps of Figs. 5.8 to In cases where both values are given, the first value is L ST, and the second is the LSA value. In cases where devices were visibly damaged, or data was out of range, the group is shaded out to indicate exclusion from the L Net values. In these maps, the samples are oriented as they were cleaved from the original wafer. Dimensions and performance could be expected to be similar in devices coming from the same half of the wafer. This allowed trends to be seen, such as in Fig. 5.8, where R1-3-A and R1-4-D values were very similar. In other cases such as R3-3-A and R3-4-D, an obvious trend toward higher loss was seen for the left half of the wafer, and the points could be excluded. Note however, that the slope parameters were not too far from the L Net value of 2.26, indicating that perhaps the taps closest to the outer radius (which included the single taps) of the wafer may have been more defective. Such trends instilled more confidence in the results. 129

144 R1-3 A B C D R D C B A R2-3 A B C D [1] [1] Device Structure Isolated tap R D C B A [1] Not fully etched wells Silicon substrate A,D Group L Net = 0.64 db B,C Group L Net = 7.42 db Fig. 5.8: Maps of TE mode loss data for samples R1, R2 isolated ridge tap devices. First data value is average of single taps (L ST ), second is loss slope average parameter LSA. R1-3 R1-4 A B C D D C B A Device Structure: Isolated TM Mode Silicon substrate A,D Group L Net = 1.16 db B,C Group L Net = 7.38 db (R1-4 data incomplete) Fig. 5.9: TM loss data for sample R1 130

145 R3-3 A B C D R D C B A Device Structure Extended Well Silicon substrate Silicon substrate A,D Group L Net = 2.26 db B,C Group L Net = 9.26 db Fig. 5.10: Map of loss data for sample R3 extended well depth ridge tap devices. R4-3 A B C D R D C B A Device Structure Standard Well/Thick Cladding Silicon substrate Silicon substrate A,D Group L Net = 5.22 db B,C Group L Net = 2.82 db Fig. 5.11: Map of loss data for sample R4 standard well depth (thick cladding) ridge taps. 131

146 R6-3 A B C D R [1] D C B A [1] Microscope Damaged Devices Device Structure Thick Spacer/Extended well tap 6 um Spacer Ta2O5 Silicon substrate A,D Group L Net = 3.19 db B,C Group L Net = 7.68 db Fig. 5.12: Map of loss data for sample R6, thick spacer/extended well ridge tap devices. Net loss results are summarized in Table 5.2. Both first and second order (typically two unit tap lengths) tap length results are given. Theoretical values were determined via 2-D and 3-D simulations in Rsoft s BeamProp ver. 5.0 software with full transparent boundary conditions, and at Pade orders of (4,4) for 2-D, and (1,1) for 3-D. For cases of high index substrates and spacers, the 3-D model optical tap lengths had to be scaled accordingly. For non-isolated tap structures, 3-D simulations indicated an additional 0.13 db loss (relative to the 2-D case) from lateral cladding energy separation during exit mode recovery. For the isolated case, the difference was less at 0.08 db. Note that actual tap lengths ( Nom Length ) were typically 30 µm and 40 µm for short and long taps respectively. The Nom+ and Nom- values give the range of loss values possible from a +/- 2 µm effective tap length variation. Length variation effects could come from 132

147 physical length variation as well as from dishing, polish step, and other well depth variations, with +/-2 µm representing a +/- 5.0 and 6.7% net variation in the tap unit length for 40 and 30 µm devices respectively. Optimal lengths are given in 1 st order (smallest) and 2 nd order lengths. An average polish step s well = 0.07 µm was assumed for all simulations based on typical step measurements and on the use of 0.1 µm alumina polish and 0.05 silica suspension final polish. From the results of Table 5.2, we see good agreement between the theoretical range of values and measured values, except in cases where the actual tap length was far from the optimum (high scatter loss cases). The isolated tap (samples R1, R2) loss of 0.64 indicated actual tap device effective excess losses of near half this value, or about 0.3 db. This was due to the fact that roughly half the scattered light during mode recovery is absorbed into the substrate and could potentially be used as signal energy. The other half radiates away from the substrate and would be lost. In these low loss cases, the data would be more affected, in terms of error percentage, by small fabrication process and measurement variations. For example, polish stepping was previously calculated to contribute db losses for a µm polish step, 0.25 db for a 0.07 µm step, and 0.45 db for a 0.1 µm step. For measured raw data values that were better than the theoretical optimum length case, it was likely that there was overestimation of the average polish step. 133

148 Table 5.2: Summary of measurements, and comparison to simulated (theoretical) results. Polish step swell set to 0.07 µm. Structure Sample Optim Length (µm) Silicon substrate R1,R2 TE Mode Nom length (µm) Meas (db) Theoretical loss at length (db) Nom Nom+ Nom- Optimum * R1,R2 TM Mode * Silicon Silicon substrate substrate R * R * Silicon Silicon substrate R um Spacer Ta2O * Silicon substrate * tap length far from optimum 134

149 From the data of Table 5.2, the average polish step of 0.07 µm appeared to be a good estimate for R1 and R2, where the measured value exactly equaled (to two decimal precision) the calculated value for the nominal fabricated tap length. Polarization effects were also measured for sample R1. The experimental data agreed with the approximately 0.5 db polarization dependant loss calculated for this tap length (Nom+ case). Sample R6 data confirmed the near 3 db coupling of TE light when using the thick 6 µm spacer. From the previous work, this would indicate polarization independence of the device, with TM light likely undergoing the same 3 db loss. However, this could not be confirmed, as the TM mode was not sufficiently supported. As a check of MMI operation, it was clear from sample R4 that the tap loss did not merely increase with longer tap lengths. Here the loss was actually less for the longer R4 tap devices. In this case, the light actually went through two MMI oscillations before exiting the tap device. Although no R4 devices were near the optimum unit tap length of 19 µm, it could be seen from the simulated optimum value that the loss would indeed be slightly better than the extended well tap case of R3. As a qualitative measure of the MMI operation of the tap devices, visible and infrared images of tap operation for devices from sample R1 are shown in Figs and Here, two tap lengths are shown, one longer than the unit tap length (~39 µm), and one close to the unit tap length (~29 µm). As can be seen, both devices show some scatter at the input to the tap well. However, the longer tap device can be seen to exhibit much more output mode recovery scatter than the near-unit length device. Slightly more scatter at the input face of the longer tap could also be due to more light being reflected from the output mode mismatch. More striking is that the sidewall scatter occurs at the 135

150 same distance from the input to the tap well. This sidewall scatter occurs when the light shifts down into the well toward the substrate. For the long device, this scatter occurs before the longitudinal center of the well, confirming the tap length as being too long. For the shorter device, this well scatter occurs in the middle of the device, as expected for a unit length tap device under vertical MMI. 5.4 CONCLUSIONS From the data and subsequent analysis, it was clear that the asymmetric vertical multimode interference tap structure worked in practice as predicted in theory. Although no upper clad device data was presented, it was clear that no significant penalty for this small increase in asymmetry was incurred. At most, a slight offset in excess loss of 0.13 db was indicated for isolated devices by Fig (15 µm wide ridge) and Fig. 5.6 (no polish step). Sample data confirmed all the trends indicated in the simulation chapter 3 for thick spacers, standard well, extended well, and isolated tap designs. Of special note was the result for sample R4, which served to confirm the MMI behavior of these devices. An effective excess loss of about 0.3 db was demonstrated for isolated taps. Improvements to the devices would primarily be in terms of planarization quality, and the addition of a matching upper cladding. In this case, excess loss could be expected to approach 0.19 db / 2 or about 0.1 db. Based on experimental results for air-upper cladding devices, excess losses of 0.32 / 2 db or about 0.15 db could be expected with improved planarization of the existing devices. 136

151 Input Poor Mode Recovery (scatter) Light shift down into well Fig. 5.13: Visible (top) and infrared (bottom) CCD images of an isolated tap device (R1) under injection of 840 nm light. Here, the tap is longer than the unit length for this structure, as can be seen by the increased output mode recovery scatter. 137

152 Input Improved Mode Recovery Light shift down into well Fig. 5.14: Visible (top) and IR (bottom) images for a tap that is close to the unit (optimum) length. Note reduced mode recovery scatter, indicating low excess loss. 138