DS1482S. 1-Wire Level Shifter and Line Driver with Load Sensor PIN ASSIGNMENT

Transcription

1 FEATURES Works with All ibuttons and 1-Wire Devices Communicates at Regular and Overdrive 1- Wire Speed (ost-dependent) Separate Interface Power Supply to evel Shift to Non-5V Systems External Strong-Pullup Control Pin can be Used to Provide ow-on-resistance-igh Current Power Source oad Sensor to Detect when Strong-Pullup Power Delivery is no onger Needed Power Delivery Signal can be Connected to ost Interrupt ow-cost 16-Pin SO Surface-Mount Package Operating Temperature Range: -40 C to +85 C 1-Wire evel Shifter and ine Driver with oad Sensor PIN ASSIGNMENT Q GND PCTZ ORDERING INFORMATION S SO-16 S/T&R SO-16, Tape-and-Reel Contact the factory for versions with different signal polarities. DESCRIPTION The is a simple 1-Wire line driver with load sensor and level shifter, designed to function as an interface between a 3V host system and a 1-Wire system that runs on 5V. Two supplies are provided, a 5V supply for the 1-Wire operations ( ) and an interface supply (Q ). The can connect directly to a synchronous serial port if it supports the appropriate bit rates to generate 1-Wire timing. Figure 1 shows the block diagram. is buffered and controls an N-channel transistor, which drives the 1-Wire pin low, e.g., to initiate a time slot. The logic level of the pin is returned through a level-shifting buffer to the pin for the host processor to read. Figure 3 shows the relationship of these signals in case of a 1-Wire read time slot. The input generates a control signal (PCTZ) for an external low-impedance PMOS transistor (Figure 2) that bypasses the 1-Wire pullup resistor (R PUP ) to provide power for 1-Wire devices with a high-load current. PCTZ is gated by the inverted signal. This prevents a high through-current in case and are high at the same time. The contains a high-precision comparator because it is important for the host micro to know when the high load on the 1-Wire side is no longer active. As shown in Figure 4, the high current load causes a small drop of the voltage on the pin. The comparator detects when the high current phase ends, and enables after the deglitching time t CF is over. The signal allows the host micro to selectively enable. ibutton and 1-Wire are registered trademarks of Dallas Semiconductor. 1 of

2 PIN NAME FUNCTION 1 Q Operating voltage for all circuitry that connects to the controlling microprocessor (,,,, pins). This line is used to control the external strong pullup function. When is 3 low, the strong pullup (PCTZ) is high. When is high and is low, PCTZ is low. This line acts as an enable control for the pin. If is high, then 4 reflects the filtered digital output of the current-sense comparator. If is low, then is low. When is low, the pin is pulled resistively to. When is 5 high, the 1-Wire bus is pulled to GND (for write-0, write-1, read, and reset low times). 7 GND Ground Reference for Q,, 1-Wire 10 1-Wire Data 12 This line returns the digital state of the 1-Wire bus, level-shifted to swing between Q and GND. This line is high only when the buffered, filtered digital output from the 13 current-sense comparator indicates that the downstream 1-Wire slave device is no longer sinking high current. This signal is enabled if is high. Active-low control pin for an external low-on-resistance, high-current 14 PCTZ supply. This signal typically controls the gate of a P-channel MOSFET. This signal is low when is high and is low. 16 Operating voltage for all circuitry that connects to the 1-Wire environment ( and PCTZ pins). 2, 6, 8, 9, 11, 15 Not Connected Figure 1. Block Diagram EVE-SIFT BOUNDARY Q R PUP GND + - Vref PCTZ 2 of 7

3 Figure 2. Typical Operating Circuit = 5V Q = 3.3V IRMS6702 RS Selecting RS Assuming that the series resistance of the FET in on-condition can be neglected, the value of RS is limited as follows: RSmax = x VCCmin/I(standby,max) RSmin = 0.01 x VCCmax/I(active,min) (21) Q S7622 µc (164) TxD0 (171) RxD0 (32) PTA0 (31) PTA1 (178) IRQ7 Q GND PCTZ 1-Wire NETWORK Example: VCCmin = 4.5V, VCCmax = 5.5V I(standby,max) = 0.15mA I(active,min) = 12mA RSmax = 45Ω, RSmin = 4.58Ω To maximize available power on the 1-Wire line, RS should be close to the lowest permissible value, in this example 5.1Ω ±5%. The effect of the on-chip pullup resistor is negligible. Figure 3. Application Signals, Normal Communication,, A OW Figure 4. Application Signals, Strong Pullup Case PCTZ CURRENT t CF 4 3 of 7

4 Point 1: Point 2: Point 3: Point 4: The 1-Wire slave device starts drawing current (internal micro or numeric processor is running). The strong pullup () must be activated before the high current phase begins. The 1-Wire slave device no longer draws current. After the deglitching time (t CF ) is over, the signal turns high. The signal must be activated no later than t SD before t CF is over. Typically is activated shortly after, but not before the 1-Wire slave device has started drawing high current. As soon as the signal is high, the host micro ends the strong pullup by changing to low. While the signal is high, the host micro changes to low; this may occur simultaneously with the state change of or later. When changes to low, becomes low. Figure 5. Timing References to 0.7 x Q 0.2 x Q t TI t TI 0.9 x 0.1 x t FIO Figure 6. Timing References to 0.7 x 0.2 x t IR t IR 0.9 x Q 0.1 x Q t F t R 4 of 7

5 Figure 7. Timing References to PCTZ 0.7 x Q 0.2 x Q t SP t SP PCTZ 0.9 x 0.1 x t F t R Figure 8. Timing References to 0.2 x Q t SD 0.9 x Q 0.1 x Q t R t F 5 of 7

6 ABSOUTE MAXIMUM RATINGS* Voltage to GND (All Pins) Combined Source/Sink Current (All Pins) Operating Temperature Range Junction Temperature Storage Temperature Range ead Temperature (Soldering) -0.5V, +6.0V 20mA -40 C to +85 C +150 C -55 C to +125 C See IPC/JEDEC 020A * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. EECTRICA CARACTERISTICS ( = 4.5V to 5.5V, Q = 3.0V to 3.6V; T A = -40 C to +85 C.) PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS Supply Current I CC 150 µa Supply Current I CCQ 100 µa Supply Ramp-up Time (System Requirement) t RCC, Q rising from 0 to MIN and QMIN, respectively 0.1 µs 1-Wire Pullup R Resistor PUP Ω INPUT PINS,, Input igh Voltage V I 0.7 x Q V Input ow Voltage V I 0.2 x Q V Input eakage Delay to I P t TI Measured with either 0V or Q on the pin (Note 1) No DC load on ; see Figure 5 (Note 2) 3 µa 100 ns PIN (1-WIRE) Output ow Voltage V O 100μA load 0.4 V Output igh Voltage V O No DC load V Pin eakage Current I P (Note 3) µa Input igh Voltage V I 0.7 x V Input ow Voltage V I 0.2 x V Comparator Reference Voltage V REF 0.99 x x x t FIO 0.9 x to 0.1 x ns V 6 of 7

7 PARAMETER SYMBO CONDITIONS MIN TYP MAX UNITS OUTPUT PIN Output-ow Voltage V O 100µA load 0.4 V Output-igh Voltage V O -100µA load Q - 0.5V V Output Rise Time t R 0.1 x Q to 0.9 x Q 50 ns t F 0.9 x Q to 0.1 x Q 50 ns Delay to t IR See Figure 6 (Note 2) 100 ns OUTPUT PIN PCTZ Output-ow Voltage V O 100µA load 0.4 V Output-igh Voltage V O -100µA load - 0.5V V Output Rise Time t R 0.1 x to 0.9 x 50 ns t F 0.9 x to 0.1 x 50 ns Delay to PCTZ t SP See Figure 7 (Note 4) 100 ns OUTPUT PIN Output-ow Voltage V O 100µA load 0.4 V Output-igh Voltage V O -100µA load Q - 0.5V V Output Rise Time t R 0.1 x Q to 0.9 x Q 50 ns t F 0.9 x Q to 0.1 x Q 50 ns Delay to t CF at Q (Note 5) µs Delay to t SD See Figure ns Note 1: Note 2: Note 3: Note 4: Note 5: The input pins have a weak pulldown. For OD read- or write-1 time slots, should be pulsed high for 1.28µs. The window for sampling begins 1.8µs after has turned high and ends 2.05µs after has turned high. must be sampled inside this window. Correct sampling can be achieved with the particular recommended microcontroller itachi S7622 if the peripheral module operating frequency PΦ is higher or equal to 22Mz. Measured either with on the pin and low or with 0V on the pin and high. This parameter is guaranteed by design, and is not production tested. The PCTZ signal is gated by. The PCTZ output is only low if is low. Characteristic of the glitch-eating filter on the output of the load-sensing comparator, i.e., an event where the downstream 1-Wire slave device is sinking high current, ceases sinking the current for less than this amount of time, and resumes sinking the current does not generate high level on ; goes high this amount of time after the downstream 1-Wire slave device has ceased sinking high current. 7 of 7