Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon

Transcription

1 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd and Vikram Iyengar Department of ECE, Carnegie Mellon University, Pittsburgh PA IBM Systems & Technology Group, Essex Junction, VT Abstract Physically-aware N-detect attempts to improve the detection characteristics of traditional N-detect by exploiting the localized characteristics of defects. Specifically, in addition to detecting each fault N times, we also require that the physical neighborhood surrounding the target change state as well. In this work, the effectiveness of the physically-aware metric is examined using two approaches. First, tester responses from an in-production IBM chip are analyzed to compare the physically-aware N- detect test with other traditional tests that include stuck-at, IDDQ, logic BIST, and delay tests. Second, diagnostic results from LSI chip failures are utilized to directly compare the traditional and physically-aware N-detect metrics. Results from both experiments demonstrate the effectiveness of physically-aware N-detect test in detecting defects in modern industrial designs. 1. Introduction The stuck-at fault model [1] has been widely used as the basis of test generation and evaluation because of its low cost and low complexity. It is well-known however that the stuck-at fault model alone is not sufficient to detect defects encountered in advanced manufacturing processes. N-detect test, which requires every stuck-at fault be detected by at least N different patterns, has been used to improve defect coverage without significantly increasing test development cost [2 16]. Physically-aware N-detect test hopes to further improve the quality achieved by N-detect by considering layout information [12, 17, 18]. In [18], a physically-aware test selection (PATS) approach This work is supported by the National Science Foundation under award no. CCF and the Semiconductor Research Corporation under contract no was described for generating a compact, physically-aware N-detect test set. There it was shown that PATS can be used to create a test set that is more effective than a traditional N-detect test set in exercising physical neighborhoods that surround targeted lines without increasing test-execution costs. The work here is focused on evaluating the effectiveness of the physically-aware N-detect metric for defect detection with respect to other test approaches using tester responses from real silicon. Specifically, we conduct two experiments. In the first experiment, PATS is applied to an in-production ASIC from IBM to create a test set that maximizes the physically-aware metric under a test-set size constraint of 5,000 patterns. This test set, along with other traditional tests that include stuck-at, IDDQ, and delay test, are applied to nearly 100,000 (99,718) chips in a stop-on-first-fail test environment. Chips that fail any of the PATS tests are then re-tested. Results from this coarse-grain experiment are analyzed and conclusions are drawn. In a second, fine-grained experiment, real chip failures from LSI are diagnosed in order to directly compare the test of sites believed to be the location(s) of failure. Through this analysis, we directly compare the traditional and physically-aware N-detect coverage of individual, failing sites. The details of test-set creation for the IBM chip and the two experiments are provided in the remaining sections of this paper. Specifically, Section 2 provides a brief overview of PATS and describes the challenges of applying it to a modern-day chip. Section 3 describes the test flow applied to the IBM and LSI chips, while Section 4 gives the details of the two experiments involving these chips. Finally, in Section 5, we draw conclusions and cite directions for follow-on research. Paper 21.3 INTERNATIONAL TEST CONFERENCE /08/$20.00 c 2008 IEEE

2 necessarily have the same neighborhoods. Hence, it is necessary to consider the neighborhood for each uncollapsed fault separately. For an industrial design, the size of the fault list can therefore be quite significant. To reduce fault simulation and test selection time, the faults listed below are not explicitly considered. Figure 1. PATS procedure. 2. Physically-Aware Test Methodology To further improve the quality of N-detect test, a physically-aware metric has been proposed to guide the test generation process [17]. The metric defines the neighborhood of the targeted line as all the physical nets that are within some specified, physical distance from the net that corresponds to the target. The set of logic values established on the neighborhood lines by a test pattern that sensitizes the target is defined as the neighborhood state. For traditional N-detect, the objective is to ensure every stuck-at fault is detected N d times. For physically-aware N-detect, the objective is to detect every stuck-at fault N s times, where each detection is associated with a unique neighborhood state 1. PATS utilizes the physically-aware metric to generate a compact test set by greedily selecting the most effective tests from a (preferably large) test pool. (See Figure 1.) PATS requires four inputs, namely, (1) a logic-level circuit description, (2) a list of all the uncollapsed stuck-at faults, (3) the neighborhood information for each signal line, and (4) a large M-detect test set T M (M N s ). T M is simulated to extract the list of neighborhood states established by T M for each stuck-at fault f i. With the neighborhood state information, tests in T M are weighted based on their ability to detect faults with various neighborhood states. PATS greedily selects heavily-weighted tests from T M until the test-set size reaches a user-provided limit. To handle large industrial designs with millions of gates, several techniques are developed. The following subsections describe these techniques in detail Fault List Management Initially, the fault list includes all uncollapsed stuck-at faults. An uncollapsed fault list is used since the physical nets corresponding to a set of equivalent faults do not 1 N d and N s will be used in place of N when it is necessary to distinguish between the number of detections (N d ) and the number of detections with unique neighborhood states (N s). 1. Faults involving clock signals: Faults affecting clocks are likely to result in failures that are easy to detect, and thus do not require explicit attention. 2. Faults detected by tests for the scan chain: These faults affect the scan paths and will alter the logic values on the fault sites in every scan-in/scan-out operation. Therefore, faults detected by tests aimed at the scan chain are relatively easy to detect and can also be ignored. 3. Faults involving global lines: Here global lines are defined to be signal lines that have a large fanout. In this work, lines with fanout greater than eight are deemed global. A line with a large fanout is likely to have a strong drive capability, and therefore is less likely to be controlled by its neighborhood. For example, if a bridge defect affects a global line and its neighbor, the defect is likely detected when the fault involving the neighbor is sensitized. For a global line affected by an open, it is likely that one of the many floating fanout lines will be detected. Consequently, global lines are excluded from consideration Test Pool Pruning For a design with scan, the neighborhood state of a targeted line should be extracted after the scan-in operation and before the capture-clock pulse. Determining fault detection when multiple capture clocks [15, 19, 20] are used is difficult and makes neighborhood state extraction more complex. Sequential fault simulation over multiple clock cycles would be required to extract states of the detected faults, a process that would increase analysis time tremendously. We instead choose to ignore test patterns with these characteristics since the percentage of faults uniquely detected by these complex patterns are very small (< 0.01%) Neighborhood Management The neighborhood of a targeted line includes physical neighbors (i.e., signal lines that are within radius r of the targeted line). However, it is often true that inputs of the gate that drives the targeted line (driver-gate inputs) and side inputs of the gates that receive the targeted line (receiver-side inputs) are naturally included in the neighborhood as well due to their close proximity. For an Paper 21.3 INTERNATIONAL TEST CONFERENCE 2

3 N-detect test set, the N detections of a stuck-at fault may have different justification and propagation paths for the fault (depending on the N-detect ATPG algorithm). Including both driver-gate and receiver-side inputs enables PATS to explore a richer set of defect activation and propagation conditions. Consequently, driver-gate and receiver-side inputs are explicitly included in a neighborhood as was done in [21]. For some neighborhoods, including all the physical neighbors, driver-gate inputs, and receiver-side inputs may significantly increase the overall number of neighbors. To keep the neighborhood size tractable for test selection, we construct neighborhoods based on the following rules: 1. Include up to 16 physical neighbors with maximum adjacency values. Some neighbors are more likely to be problematic than others. Specifically, one neighbor may have long parallel runs next to the targeted line while another only enters the neighborhood with a small footprint. The layout information utilized in this work contains a measure (called the adjacency value) of the physical proximity of two wires. We order physical neighbors according to their adjacency values, and consider up to 16 neighbors with the greatest adjacency values. 2. Include all the driver-gate inputs. Since a single cell (gate) drives a targeted line, the number of drivergate inputs to be included in a neighborhood is usually small. Therefore driver-gate inputs are always included in the neighborhoods. 3. Include receiver-side inputs only if the target is not a global line. Excluding global lines also has the effect of constraining the number of receiver-side inputs. Therefore all receiver-side inputs are included in the neighborhoods Top-off Test Selection In order to maximize defect detection during slow, structural scan-test, we decided to use PATS to top-off (augment) the existing stuck-at test patterns. This is in contrast to the approach applied to the LSI test chip considered in [18]. Top-off test selection is easily accomplished by (i) grading the existing stuck-at test patterns using the physically-aware N-detect metric, and (ii) using those results as the starting point for PATS. In other words, only tests that established neighborhood states that have not yet been established by the existing stuck-at tests are selected by PATS. 3. Industrial Chips and Test Flows The physically-aware N-detect test metric is applied to industrial chips from IBM and LSI. Details of the two chips and their corresponding test flows are described next IBM In-Production Chips The chip from IBM is an in-production ASIC, fabricated using 130nm technology. The chip design has nearly a million gates, and the physical neighborhood information includes all the signal lines within 0.6µm of the targeted line. After applying the rules described in Section 2.1, approximately four million uncollapsed stuck-at faults are considered. PATS is used to select a physically-aware N s =10-detect test set of 5,000 test patterns from a N d =20- detect test set of 16,358 patterns. Cadence Encounter Test [22] was used to generate the 20-detect test set. It was also used to fault simulate and extract neighborhood states for both the IBM stuck-at tests and the 20-detect test set. The production test for the IBM chip, applied in the following sequence, includes scan-based stuck-at test, IDDQ, PATS, and delay test. These tests are applied in a stopon-first-fail environment, that is, failure of any chip means that subsequent tests are not applied. Features of the various test sets are shown in Table 1. The stuck-at and PATS test sets are applied with a latch launch-capture speed between 33MHz and 50MHz. Delay test is applied at different speeds, mostly ranging from 77MHz to 143MHz, but is performed at low VDD. For IDDQ, four measurements are taken. Fault coverage, where known, is based on the appropriate test metric. For stuck-at tests, coverage is simply the percentage of stuck-at faults detected. For delay test, it is the percentage of transition faults detected. Finally, for PATS, coverage is the percentage of stuck-at faults that have N s 10 or N s = 2 n < 10, where n is the number of neighbors in a given stuck-at fault neighborhood. Test speed Fault coverage Test type No. patterns (MHz) (%) Stuck-at 3, IDDQ PATS 5, Delay * 19, * Applied at low VDD. Table 1. Production test details for the IBM ASIC LSI Test Chips The LSI test chip consists of bit ALUs (arithmetic-logic units) that are interconnected through Paper 21.3 INTERNATIONAL TEST CONFERENCE 3

4 multiplexers and scan chains, and is fabricated using a 130nm process. Each ALU has approximately 3,000 gates, 10,220 stuck-at faults, and is subjected to scan-chain integrity test, scan-based stuck-at test, and IDDQ test. The stuck-at test consists of 260 scan-test patterns, achieving >99% stuck-at fault coverage. In the next section, we describe how the tester responses from stuck-at failures are used for comparing the traditional and physically-aware N-detect metrics. Number of faults Silicon Experiments We examine the effectiveness of the physically-aware metric using two approaches. The first approach centers on a coarse-grained test experiment involving the aforementioned chip from IBM. The second approach is fine-grained in nature and uses diagnosis of failing test chips from LSI Coarse-Grained Experiment In this experiment, the ability of tests derived using the physically-aware metric to detect actual defects is examined and compared to other types of tests that include stuck-at, IDDQ, logic BIST, and delay patterns. The test statistics and the production test analysis for the IBM chip is presented in the following subsections Test Statistics The physically-aware test methodology described in Section 2 is applied to the IBM chip. Figure 2 shows the distribution of neighborhood sizes, i.e., the number of faults (y-axis) that have the specified number of neighbors (x-axis). Since driver-gate and receiver-side inputs are included along with the actual physical neighbors, each fault has at least one neighbor. From Figure 2, it is evident that a majority of faults have less than 20 neighbors. The plot would have a much longer tail however if all faults and neighbors were included. (Recall that some faults and neighbors are excluded based on the criteria outlined in Sections 2.1 and 2.3, respectively.) A comparison of the 1-detect, physically-aware 10- detect, and the 20-detect test sets is shown in Table 2. The last two columns of Table 2 give the percentage of change for various test-set attributes for PATS and the 20-detect test sets with respect to the original (1-detect) stuck-at test applied by IBM. The size of each test set is given in the second row, where the number in parentheses gives the number of test patterns whose neighborhood states are easily extractable. The third row is the total number of neighborhood states established by each test set. Table Number of neighbors Figure 2. Distribution of neighborhood sizes. reveals that PATS achieves 56% more states with only a 39% increase in test-set size over the 1-detect test set. The traditional 20-detect test set establishes 2.2X more neighborhood states than the 1-detect test set but at the cost of a 3.5X increase in the number of tests. This means there are patterns within the 20-detect test set that do not establish new neighborhood states, implying inefficient use of test resources in the generation and application of traditional N-detect tests. The fourth and fifth row show the number of faults that have N d = 10 and N s = 10, respectively. Although the 20-detect test set has more faults reported for both metrics, its advantage over PATS is not significant and comes at the cost of a much larger pattern count. Figure 3(a) plots the number of faults (y-axis) that have N s detections with unique states for various values of N s (x-axis). The fault counts from the 1-detect test set form the lower bound, and the upper bound stems from the 20-detect test set. For clarity, the tails of the curves are not shown in Figure 3(a). It can be observed that PATS and the 20-detect test set are very close for N s 10, thus demonstrating the ability of PATS to boost neighborhood state counts for faults with fewer established states. For N s > 10, PATS gradually departs from the 20-detect test set as expected since we do not target faults that have N s 10. Test resources are therefore not wasted on well-tested faults that are not targeted. Figure 3(b) shows the number of faults versus, where is defined as the difference between N d and N s. Ideally, should be zero indicating that every time the corresponding fault is detected, it is done so with a unique neighborhood state. A fault with a large means it is detected many times but with repeating neighborhood states. In this experiment, the 1-detect test set has the most faults with = 0, while the 20-detect test set has the least. Even though many Paper 21.3 INTERNATIONAL TEST CONFERENCE 4

5 Percentage change Percentage change Test set properties 1-detect PATS 20-detect PATS vs. 1-detect 20-detect vs. 1-detect 3,594 5,000 16, % % Test-set size (3,431) (5,000) (15,328) (45.73%) (346.75%) No. of established states M M M 56.28% % No. of faults with N d M 3.70M 3.89M 23.33% 29.67% No. of faults with N s M 1.70M 1.81M 25.93% 34.07% Table 2. Comparison of test-set sizes and the number of neighborhood states established detect PATS 1-detect detect PATS 1-detect Number of faults (million) N s Number of faults (million) = N d - N s (a) (b) Figure 3. Analysis of N-detect and PATS test sets based on the distribution of (a) the number of faults versus N s, and (b) the number of faults versus = N d N s. faults have = 0 for the 1-detect, this is not a desirable situation since this test set only guarantees that each fault is sensitized a single time. The 20-detect curve has a long tail, which is absent from Figure 3(b) for clarity purposes. Compared to the 20-detect test set, PATS has more faults with low values for, indicating that the neighborhood state count reasonably increases as the number of detections grows. These results are quite consistent with our previous work [18], where we showed that N s can be significantly increased with respect to N d without increasing the number of test patterns Production Test Evaluation The outcome of the production test for nearly 100,000 IBM chips is described in Figure 4. Of the 99,718 parts that passed the stuck-at test, 57 parts failed the IDDQ test, 16 failed the PATS tests, and 330 failed delay test. The 16 chips that failed the PATS tests were subjected to re-test using the transition-fault delay tests and logic BIST. Logic BIST runs at-speed at about 300MHz under nominal VDD without any signal weighting, and applies 42,000 test patterns. Eight of 16 chips that failed the PATS tests were Figure 4. IBM production test results. Paper 21.3 INTERNATIONAL TEST CONFERENCE 5

6 detected by the delay test which means its application in production reduced DPPM (defect parts per million) by about 80. Of the remaining eight chips, five were detected by logic BIST. Thus, the addition of logic BIST to the production flow implies that DPPM reduction solely due to PATS would be approximately 30. Together, logic BIST and delay test apply over 60,000 patterns which is 12X more than the number of PATS tests. Even with this large difference, PATS is able to uniquely fail three chips. With respect to the delay test patterns alone, eight chips are uniquely failed even though nearly 4X more patterns are applied. It is likely the effectiveness of the 5,000 PATS test patterns can be further improved if, along with the stuck-at tests, the delay test and BIST patterns are graded and used as the starting point for PATS. This is possible but somewhat time consuming however since grading the 3,594 stuck-at patterns required 12 hours of compute time Fine-Grained Experiment In the fine-grained experiment, diagnosis is used to identify the defective site that established the first evidence of failure. The test patterns that sensitize this site are then examined to compare the traditional and physically-aware N-detect metrics, that is, N d and N s. It should be noted that this approach to measuring the effectiveness of a test methodology is quite general and can be used to examine the utility of a test method without necessitating the need for additional test patterns. This characteristic is demonstrated using fail logs from LSI test chips. The applied test set achieves >99% stuck-at fault coverage and more than 98% of the 10,220 faults are detected with N d > 1 (see Figure 5) 2. The value of N d will be used as one of the screening criteria for selecting failing chips for analysis. Next, we describe the screening flow for selecting failing chips of interest, the analytical procedure, and the results showing the effectiveness of the physically-aware metric Chip Selection To select failing chips best suitable for comparing the traditional and physically-aware N-detect metrics, we use the procedure described in Figure 6. The objective is to identify failing chips that are (i) hard to detect and (ii) have evidence that allows us to identify a single faulty signal line that causes the first failing pattern (FFP). The reason 2 It should be noted here that there are different stuck-at test sets applied to the identical ALUs within the LSI test chip, an artifact of the automated test-generation process. The data plotted in Figure 5 is from one of these test sets and is quite representative of the others. The analyses presented in Section however use all of the test sets, that is, the appropriate test set for a given failing ALU are coupled before the analysis is performed. Number of faults N d Figure 5. Distribution of the number of faults versus the number of detections N d for a 1-detect stuck-at test set applied to the LSI test-chip ALU. for this objective is that this class of chips are the ones that are directly targeted by N-detect. From the 2,533 chips in the stuck-at failure logs, nine chips whose failing patterns are all non-slat [23] (single location at a time) are excluded. These chips do not exhibit any stuck-at failure behavior, meaning they have one or more defects that create simultaneously faulty lines. These chips are difficult to diagnose and more importantly, are not directly targeted by N-detect test methods like the ones considered here. Using the methodology described in [21] with a neighborhood radius of 0.25µm, the stuck-at failure logs of 719 out of the remaining 2,524 failing chips are successfully diagnosed. For each failing chip the following is collected: 1. The index of FFP for the chip. 2. Whether or not the failing chip exactly exhibits stuckat behavior. (These chips are of no interest due to their simple detection characteristics.) 3. Each faulty site 3 believed to be involved in the failure and the following fault characteristics: (a) The number of test patterns, N d, that detected the fault before and including the chip s FFP. (b) The number of test patterns, N s, that detected the fault with a unique neighborhood state before and including the chip s FFP. (c) The index of the first pattern that detected the fault (which may or may not be the same as the chip s FFP). 3 A faulty site behaves as a stuck-at zero or one fault for one or more failing patterns but is not necessarily a stuck-at fault. Paper 21.3 INTERNATIONAL TEST CONFERENCE 6

7 by computing the ratio R = N s /N d. Table 3 shows the distribution of N d, N s and R for the 12 single-suspect chips. It can be seen that all 12 chips have R = 1, which means that each test that sensitized the faulty site established a unique neighborhood state. For each chip, multiple states were encountered before the chip failed. More interesting is that none of these hard-to-detect failures would be necessarily detected by a traditional N-detect test set. N d N s R No. of chips Table 3. The number of detections N d, the number of states N s, and their ratio R = N s /N d for LSI chip failures that have one sensitized faulty site for the chip s FFP. Figure 6. Diagnostic process used to identify the defective sites for hard-to-detect failures. In the third step of Figure 6, we disregarded chips whose FFP is a non-slat pattern. Although diagnosis has been successfully performed for these seven chips, a single site cannot be indicted as the cause of the chip s FFP. After this step there are 712 chips remaining. Next, any chip that has a faulty site that is detected by the chip s FFP and has N d = 1 is also disregarded. There are 631 chips falling into this category. These chips are easily detected with a 1-detect test set, and are therefore of no interest when considering N-detect. The remaining 81 chips are partitioned into two categories: 12 chips have only one suspect site, and 69 have two or more suspects, each of which could alone cause the chip s FFP. The smaller set of chips are of particular interest since we have significant confidence in the failure location identified by diagnosis. The larger set is of interest as well however since best, worst and average case analyses can be performed. In the next section, we examine the test of these faulty sites with respect to N d and N s for these hard-todetect defects N s /N d Ratio Analysis Using N d and N s collected for each chip during diagnosis, we compare traditional and physically-aware N-detect For chips with multiple suspect sites, the ratio is computed for the best, worst and average case. Specifically, for each failing chip c i with q i FFP sites, the best, worst and average ratios are calculated as follows: R i,best = max j=1 q i R i,j R i,worst = R i,avg = min j=1 q i R i,j j=1 q i R i,j /q i The histograms for the best, worst, and average ratios for the 69 multiple-suspect chips are shown in Figure 7. The histogram of the best ratios shows that the suspect sites of all but four failing chips have an R = 1, indicating that these sites are all detected N d times with N s = N d unique neighborhood states. Two of the four chips have a ratio of 0.6 and the other two have 0.8, which are still high. The histogram for the worst ratios shows that only four of 69 chips have a ratio of less than 0.5. For contrast, Figure 8 shows the histograms for two sets of data: first, from Figure 7, the average ratio of the multiple-suspect chips diagnosed, and second, the ratio for all of the faults in the LSI ALU (i.e., we compute R = N s /N d for every fault using all of the stuck-at patterns) 4. Comparing the two histograms reveals that 100% of the multiple-suspect failing chips have R 0.5 while only 34% of all stuck-at faults have R 0.5. Moreover, 74% (= 50/69) have a perfect R=1.0 4 Of the 10,220 stuck-at faults in the ALU, 2,299 of them are detected with N d N s = 2 n, where n is the number of neighbors. If N d > N s = 2 n, then the ratio R = N s/n d is misleading. Faults that have N s = 2 n are therefore not included in Figure 8. Paper 21.3 INTERNATIONAL TEST CONFERENCE 7

8 Number of chips best worst avg Percentage of fault sites (%) ~ detect avg Figure 7. Histograms of best, worst and average ratios for failing ALU chips that have multiple suspect sites that can cause the chip s FFP. Figure 8. Ratio comparison between faulty sites in diagnosed ALU chips and all ALU chip faults. while only 26% (= 2, 087/(10, 220 2, 299)) of all the stuck-at faults have R=1.0. These numbers only slightly change when the worst-case plot of Figure 7 is used instead. We draw the following conclusions from analyzing Figure Defective chips that are hard to detect require a relatively high ratio since it appears there is some particular neighborhood state required for defect activation. 2. For any of the failing chips, it is possible that some state before the chip s FFP activated the defect and sensitized the defect site to some observable point but did not cause failure due to timing issues. However, these cases are beyond the scope of this work since N-detect inherently focuses only on static defects, that is, those defects that do not depend on the timing or sequence of the applied test patterns. 3. Similar observations are made for the chips from Figure 6 not successfully diagnosed. All of these chips, for at least one failing pattern, suffered from at least two, simultaneously faulty lines. Because of this characteristic, they too are not directly targeted by N- detect. 5. Conclusions The effectiveness of the physically-aware metric was evaluated using tester responses from real silicon. In the experiment involving an in-production IBM chip, PATS uniquely failed 3 chips passing stuck-at, IDDQ, logic BIST and delay tests, even thought the latter tests applied 12X more patterns (i.e., 5,000 compared to over 60,000). As mentioned in Section 4.1.2, it is likely that the effectiveness of the PATS patterns can be further improved if the top-off test selection used, as a starting point, all the patterns (stuck-at, delay, and logic BIST) instead of just the stuck-at tests. The second experiment involving the LSI test chip provides evidence that hard-to-detect defects are activated only after various neighborhood states are established for the faulty sites. Utilizing the physically-aware metric in the test generation process can therefore improve defect detection by establishing more neighborhood states for targeted lines. PATS can be easily integrated into existing test flows, and as demonstrated here, can be applied to modern-day designs. In addition, the simple test-selection procedure implemented in PATS can be used in several ways. In [18], PATS was used to produce a neighborhood-based test set for the LSI test chip. The size of the resulting test was constrained to be equal to a traditional N-detect but the effectiveness, as measured by the number of neighborhood states, was significantly improved. In this work, PATS is used to create top-off patterns, that is, a limited number of patterns that are meant to maximize coverage of the overall scan test. PATS can also be used to improve diagnosis accuracy by creating additional test patterns for suspect sites. Specifically, knowledge of which neighborhood states lead to defect activation and which ones do not, enables the extraction of various defect characteristics [21]. There are a number of open research questions that may Paper 21.3 INTERNATIONAL TEST CONFERENCE 8

9 be worthy of exploration. For example, the results of the coarse-grained experiment reveal that many defects are caught by at-speed BIST and transition fault test. Given this result, it may be worthwhile to explore neighborhood-based delay test. Another more immediate question related to this work presented here has to do with the number of neighborhood states N s needed to achieve a desired level of quality. This question, which is the focus of our current work, is one that has been addressed by other researchers for traditional N-detect [4]. It is therefore likely those and similar works can be extended to physically-aware N-detect. 6. Acknowledgment The authors are very grateful to Brion Keller of Cadence for his valuable feedback on Encounter Test. The authors would also like to thank LSI for providing design and tester data for the ALU test chips. From IBM, we would like to thank Maroun Kassab for his work in extracting the neighborhood information for the IBM ASIC, and Christian Fontaine for performing all of the re-test and characterization experiments of the failing IBM chips. References [1] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits. Boston MA: Kluwer Academic Publishers, [2] S. C. Ma, P. Franco, and E. J. McCluskey, An Experimental Chip to Evaluate Test Techniques Experiment Results, Proc. International Test Conference, pp , Oct [3] E. J. McCluskey and C.-W. Tseng, Stuck-fault tests vs. actual defects, Proc. International Test Conference, pp , Oct [4] M. R. Grimaila, S. Lee, J. Dworak, K. Butler, B. Stewart, H. Balachandran, B. Houchins, V. Mathur, J. Park, L.-C. Wang, and M. R. Mercer, REDO - Random Excitation and Deterministic Observation - First Commercial Experiment, Proc. of VLSI Test Symposium, pp , Apr [5] S. Lee, B. Cobb, J. Dworak, M. R. Grimaila, and M. R. Mercer, A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of all Faults, Proc. Design, Automation and Test in Europe, pp , Mar [6] B. Benware, C. Schuermyer, N. Tamarapalli, K.-H. Tsai, S. Ranganathan, R. Madge, J. Rajski, and P. Krishnamurthy, Impact of Multiple-Detect Test Patterns on Product Quality, International Test Conference, pp , Sep.- Oct [7] I. Pomeranz and S. M. Reddy, A Measure of Quality for N-Detection Test Sets, IEEE Transactions on Computers, vol. 53, pp , Nov [8] S. Venkataraman, S. Sivaraj, E. Amyeen, S. Lee, A. Ojha, and R. Guo, An Experimental Study of N-Detect Scan ATPG Patterns on a Processor, Proc. VLSI Test Symposium, pp , Apr [9] M. E. Amyeen, S. Venkataraman, A. Ojha, and S. Lee, Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor, Proc. International Test Conference, pp , Oct [10] Y. Tian, M. Grimaila, W. Shi, and M. Mercer, An Optimal Test Pattern Selection Method to Improve the Defect Coverage, Proc. International Test Conference, Nov [11] H. Tang, G. Chen, S. M. Reddy, C. Wang, J. Rajski, and I. Pomeranz, Defect Aware Test Pattern, Proc. Design, Automation and Test in Europe, pp , Mar [12] J. E. Nelson, J. G. Brown, R. Desineni, and R. D. Blanton, Multiple-Detect ATPG Based on Physical Neighborhoods, Proc. Design Automation Conference, pp , July [13] K. R. Kantipudi and V. D. Agrawal, On The Size and Generation of Minimal N-Detection Tests, Proc. International Conference on VLSI Design, pp , Jan [14] J. Geuzebroek, E. J. Marinissen, A. Majhi, A. Glowatz, and F. Hapke, Embedded Multi-Detect ATPG and Its Effect on the Detection of Unmodeled Defects, Proc. International Test Conference, Oct [15] G. Bhargava, D. Meehl, and J. Sage, Achieving Serendipitous N-detect Mark-Offs in Multi-Capture-Clock Scan Patterns, Proc. International Test Conference, Oct [16] I. Pomeranz and S. M. Reddy, On the Saturation of N- Detection Test Sets with Increased N, Proc. International Test Conference, Oct [17] R. D. Blanton, K. N. Dwarakanath, and A. B. Shah, Analyzing the Effectiveness of Multiple-Detect Test Sets, Proc. International Test Conference, pp , Sep.-Oct [18] Y.-T. Lin, O. Poku, N. K. Bhatti, and R. D. Blanton, Physically-Aware N-Detect Test Pattern Selection, Proc. Design, Automation and Test in Europe, pp , Mar [19] X. Lin and R. Thompson, Test Generation for Designs with Multiple Clocks, Proc. Design Automation Conference, pp , June [20] V. Jain and J. Waicukauski, Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique, Proc. International Test Conference, pp , Oct [21] R. Desineni, O. Poku, and R. D. Blanton, A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior, Proc. International Test Conference, Oct [22] The Encounter Test Reference Manual, Cadence Design Systems, Inc., San Jose, CA., [23] L. M. Huisman, Diagnosing Arbitrary Defects in Logic Designs Using Single Location at a Time (SLAT), IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp , Jan Paper 21.3 INTERNATIONAL TEST CONFERENCE 9