Classification of the Destruction Effects in CMOS- Devices after Impact of Fast Transient Electromagnetic Pulses

Transcription

1 1 of 8 Classification of the Destruction Effects in CMOS- Devices after Impact of Fast Transient Electromagnetic Pulses Short title: EMP Destructions in Integrated Circuits Michael Camp 1,4, Sven Korte 1, Heyno Garbe 1 1 Institut für Grundlagen der Elektrotechnik und Messtechnik, Universität Hannover, Hannover, Germany 4 To whom correspondence should be addressed: Michael Camp, Institut für Grundlagen der Elektrotechnik und Messtechnik, Universität Hannover, Appelstraße 9A, Hannover, Germany; camp@ieee.org Abstract In this investigation the destruction effects in CMOS-devices after impact of fast transient electromagnetic pulses have been classified. In comparison with TTL-devices, identical CMOS-devices are much more complex concerning the layout. Anyway, the destruction effects are similar to the destruction effects observed at TTL-devices in previous investigations [1]. In this paper a classification concerning the location areas have been performed. It will be shown that first, at lower field amplitudes, the input protection circuits of the tested CMOS-devices are damaged. If the amplitude increases additional destructions of the output circuits appear. Further increase leads to destructions directly inside the electronic circuit (between input and output circuits). Keywords: Susceptibility, CMOS, Electromagnetic Pulse, EMP, UWB, Destruction Effects 1. Introduction Risks as a result of upset effects of electronic circuits are ranging from artless breakdown effects of household appliances to perilous failure effects of medical equipment, culminating in a total collapse of traffic-, communication- and defense-systems of modern developed nations, with fatal consequences for the affected areas. New developed pulse generating devices can be built in a very small volume due to the low energy content of the pulse. In combination with broadband antennas it is possible to damage arbitrary electronic equipment in a great distance. Therefore the investigation of the susceptibility of electronic devices is of great interest.

2 2 of 8 2. Measurement Setup The applied pulse shape is generally double exponential as shown in Figure 1. Five different pulse generating devices are available. Table 1 shows the rise time (t r ) and the full width half max value (t fwhm ) of the different pulses. Pulse Rise time t r Pulse length t fwhm UWB 100 ps 2.5 ns EMP (fast) 1.5 ns 80 ns EMP (med.) 5 ns 300 ns UWB - slow EMP 500 ps - 10 ns 2.5 ns ns EMP (slow) >10 ns 500 ns 100 % 90 % 50 % 10 % t r r E 1 (t) t fwhm r E ( t) 1 = 0 E ( e β t α t e ) t / s Figure 1 Pulseshape and Parameters The measurements were carried out with two different waveguides shown in Figure 2 and 3. Waveguide 1 is an open area test simulator with a maximum heigth of about 23 m described in [2]. Waveguide 2 [3] is an open waveguide inside a shielded room enclosed by absorber walls. The absorbers at the end of the waveguide were placed on interchangeable wooden walls. The position of the septum can be adjusted via nylonthreads. The measurements of the electromagnetic properties were done by a Time Domain Reflectometer (TDR) and electric and magnetic groundplane and free field probes as described in [4]. Septum Terminating Resistors 5,8 m Terminating Resistors Generator 23 m Connector Nylon 2 m 110 m Aluminium Absorber Figure 2 Waveguide 1 Figure 3 Waveguide 2 3. Test Setup To apply the different pulses to the EUT a modular setup has been realized (Figure 4). Ten separate channels were built with a combination of differently printed circuit boards. The circuit boards were combined with ribbon cables to realize different coupling lengths at the

3 3 of 8 input and output pins of the devices under test. In Fig.5 a NAND test setup with 20 cm ribbon cable length at the input pins and 0 cm ribbon cable length at the output pins of the test devices is shown. The power supply is realized with ten different accumulators. DIP switches were implemented to the power supply unit to adjust arbitrary bit patterns at the input pins. LEDs and resistors were used as loads to observe the operating states of the devices. Standard TTL Logic FAST TTL Accu Accu Logic... Power supply... Logic circuits... Logic Buffer Buffer Buffer circuits Buffer separate Channels ribbon cables S v E v v H HCT CMOS S v E v H v ribbon cables power supply DIP switches logic devices Load Loads (LEDs + Resistors) Load Load loads Figure 4 Test Setup - Principle Figure 5 NAND Test Setup - Realization 4. Measurement Results After impact of an electromagnetic pulse to the measurement setup equipped with CMOS- Devices as described in section two, two different forms of chip destructions occur. First there can be observed breakthroughs as shown in Figure 6. Figure 6 Breakthrough Figure 7 Melting Process

4 4 of 8 Here the chip damage takes place between vicinal IC-lines and destroyed the structure located between. The second type of destruction effect is shown in Figure 7. In this case, a melting process caused by thermal heating of the structure cut the connection. In contrast to former investigations of TTL-Technology [1] the described destruction effects in CMOS-Devices do not show a dependency of the field strength of the applied pulses. On the other hand the destruction areas are strongly influenced by the field strength as discussed in the following sections Classification of the Destruction Effects After microscopic analysis of damaged CMOS-Devices three different destruction areas can be stated. At lower amplitudes of the applied pulses only the input protection circuits of the gates, originally designed for ESD protection, are victims of destructions. Figure 8a shows an undamaged input circuit of an AC-/ACT-Inverter consisting of two integrated diodes and one resistor. With increasing field strength breakthroughs and melting processes can be observed (Figure 8b) which are leading finally to a total destruction of the input circuit and the surrounding structure (Figure 8c). a.) Diode Diode b.) c.) Breakthrough Resistor Melting Process undamaged damaged damaged Figure 8 Input Protection Circuit of AC-/ACT-Inverters With increasing field strength additional destructions can be observed at the output circuits of the logic devices. On most chip layouts the outputs are also protected against ESD. Figure 9a shows the undamaged output circuit of an AC-/ACT-Inverter with a protection diode. The damaged device in Figure 9b shows again both a breakthrough in the diode structure and melting effects on the IC-line very similar to Figure 8. On components without ESD protection circuits the thermal destruction of IC-lines can be noticed. In this case breakthroughs cannot be detected.

5 5 of 8 a.) Diode b.) Melting Process undamaged damaged Breakthrough Figure 9 Output Circuit of AC-/ACT-Inverters With further increase of the field strength, the destruction effects at the output circuits scatter back in the rear transistor stages of the damaged devices (Figure 10). a.) b.) N-Channel-MOSFET Breakthroughs P-Channel-MOSFET Diode Melting Processes undamaged damaged Figure 10 Last Transistor Stage and Output Circuit of AC-/ACT-Inverters

6 6 of 8 Figure 10a shows the undamaged rear section of an AC-/ACT-Inverter consisting of a ESD protection diode and a transistor stage with each one N-Channel- and one P-Channel- MOSFET. As expected the diode is destroyed with increasing amplitude similar to Figure 9 (Figure 10b). At very high amplitudes the destructions additionally scatter back in the last transistor stage of the logic gate. The results are breaktroughs in the transistors structures and additional melting processes Field Strength Dependence of the Destruction Effects The influence of the field strength on the chip damage suggests a closer examination of the destruction effects with increasing field amplitude. Figure 11 shows the Destruction Failure Rate (DFR) of the examined four CMOS families of NAND Devices separated into the three destruction classes according to Section 4.1. The DFR diagram relates the percentage of damaged chips to the applied field strength E of the EMP. The Destruction Thresholds (DT) in Figure 12 are extracted from Figure 11 at 5 % of the maximal DFR [5]. At lower field strength, just above 700 kv/m, destructions only occur in the input circuits of the damaged gates. By increasing the amplitude above 800 KV/m the gates are damaged additionally near their outputs. Only at field strengths of 900 kv/m and above, structures in the inner stages of the gates are destroyed. The destructions in this cases always scatter back from the output circuits into the last stages of the gates. An analogue field strength dependence can be observed for CMOS Inverter Devices. DFR DT in kv/m 1 0,8 0,6 0,4 0,2 0 HC HCT AC ACT Output Circuit HC HCT AC ACT Destruction Scattering HC HCT AC ACT E in kv/m Output Circuit Destruction Scattering HC HCT AC ACT Figure 11 Destruction Failure Rate of NANDs Figure 12 Destruction Threshold of NANDs 4.3. System State Dependence of the Destruction Effects Additional to the field strength dependence, the observed effects are also dependent of the system state. Figure 13 shows an Inverter Harris CD74AC04E after impact of an EMP with a maximum field amplitude of 1143 kv/m (Figure 13a), respectively 1290 kv/m (Figure 13b). The white lines divide the devices into the six integrated inverter gates. The missing of bond wires in Figure 13b is a result of the opening process and no destruction based on the applied pulses. At lower amplitudes only the input stages of the Inverters A,C and E are damaged. Higher field strength cause additional destructions in output circuits and rear transistor stages

7 7 of 8 as mentioned in Section 4.2. Exemplary details and their localisation on the layout are shown in Figures 14 and 15. a.) b.) D1 E1 E2 D2 Inverter F Inverter E Inverter D Inverter A Inverter B Inverter C Inverter F Inverter E Inverter D Inverter A Inverter B Inverter C Output Circuit Destruction Scattering Figure 13 Inverter Harris CD74AC04E after EMP impact with field strength: a.) 1143 kv/m; b.) 1290 kv/m E1 E2 D1 D2 Figure 14 Exemplary Details of Figure 13 Observing Figure 13a und 13b, the distribution of the destructed areas draws attention. In Figure 13a only the Inverter Gates A,C and E are damaged, the destructions caused by higher field strength only occur on the Gates B,D and F (Figure 13b). E +U CC D Output Circuit +U CC Inverter F IN: L OUT: H Inverter E IN: H OUT: L Inverter D IN: L OUT: H A Inverter A Inverter B Inverter C E1 E2 D2 D1 IN: H OUT: L IN: L OUT: H IN: H OUT: L Figure 15 Located destructions of Figure 14 Figure 16 System State

8 8 of 8 Considering the system state of the inverter device during the application of the EMP (Figure 16), analogies can be observed. At the inputs of the Inverters A,C and E high-level was applied, while the Inverters B, D and F were leading low level at the input and high level at the output. Structures close to bondpads which are leading supply voltage are apparently most frequently victims of damage by EMP impact. This effect can be observed on all tested devices. 5. Summary The investigation of the susceptibility of logic devices (NANDs and Inverter), built in different CMOS semiconductor technologies, to EMP and UWB pulses has shown, that the destruction areas are strongly influenced by the field strength. At lower amplitudes of the applied pulses only the input protection circuits of the gates, originally designed for ESD protection, are victims of destructions. Breakthroughs and melting processes can be observed. With increasing field strength additional destructions can be observed at the output circuits of the logic devices. With further increase of the field strength, the destruction effects at the output circuits scatter back in the rear transistor stages of the damaged devices. Additional to the field strength dependence, the observed effects are also affected by the system state. High level adjusted input or output circuits are much more susceptible than low level adjusted circuits. This investigation is part of the study Susceptibility of Electronics to EMP and UWB, Phase II, commissioned by the Armed Forces Scientific Institute for Protection Technologies - ABC-Protection (Munster, Germany). [1] M.Camp, H.Garbe, D.Nitsch, Influence of the Technology on the Destruction Effects of Semiconductors by Impact of EMP and UWB Pulses, 2002 IEEE International Symposium on Electromagnetic Compatibility, USA, Minneapolis 2002, August 19-23, ISBN: , pp [2] D.Nitsch, J.Schlüter, H.J.Kitschke, Generierung und Vorteile von Ultrawideband- Impulsen, EMV99, Mannheim, Germany [3] C.Braun, Aufbau eines breitbandigen Wellenleiters für NEMP Modell Simulationen, INT Bericht Okt. 84 [4] D.Nitsch, M.Camp, "UWB and EMP Susceptibility of Modern Microprocessorboards", EMC Europe, Brugge, Sept [5] M.Camp, H.Gerth, H.Garbe, H.Haase, Predicting the Breakdown Behavior of Microcontrollers under EMP/UWB Impact Using a Statistical Analysis, IEEE- Transactions on Electromagnetic Compatibility, Special Issue on IEMI 2004