Title Power electronic interfaces in Micro grids. Dejene

Transcription

1 Ttle Power electronc nterfaces n Mcro grds By Frew Zerhun Dejene Master of Scence Thess Supervsors: Dr. Staffan Norrga, ABB Professor Hans-Peter Nee, KTH XR-EE-EME 7:6 Royal nsttute of Technology (KTH) Department of Electrcal Engneerng Electrcal Machnes and Power Electroncs Stockholm, 7

2 Abstract Ths dploma work report deals wth manly DC to AC type Power electronc nverters used n DGs such as PV type or photocell types, wth the man focus beng on how these nverters handle unbalanced loads, especally whle the DG s workng n slanded mode. The professonal s Tool for Power Systems Smulaton usng EMTDC (PSCAD) software whch s a general-purpose tme doman smulaton program for mult-phase power systems and control networks s used for smulatons. Analytcal calculatons were also done n Matlab. Keywords Mcro Grds, Voltage Source nverters, DC capactor szng.

3 Acknowledgement would lke to pass my heartly thanks to Dr Staffan Norrga for helpng me work on ths thess as well as hs help durng my job. would also lke to thank Professor Hans Peter Nee for gvng me very excellent deas and scholarly explanatons whle was workng. Mom and Dad, thank you so much! You have been sources of my strength all my lfe tme. Last but not least would lke to thank all those who have helped me wth ths thess work Dejene A sunny day n Stockholm, June 6, 7

4 Contents Chapter ntroducton...8. BACKGROUND...8. PROBLEM DESCRPTON Mcro Source Grd nterfaces Topologes for comparson Assumptons n the comparson Standard Norms to be adopted....3 MOTVATONS AND OBJECTVES....4 SCOPE OF THE PROJECT... Chapter Lterature Revew.... Mcro grds and state of the art Trends..... MCROGRDS Defnton..... Why mcro grds? Types of Dstrbuted Generaton Mcro Grd Archtecture Mcro Source Controller (MC) Modellng and smulaton of Mcro Grds..... Challenges Related to Mcro grds....3 Power Electronc nterface Features and Capabltes Self commutated converter systems Power flow control - real and reactve components Basc Control of Real and Reactve Power Voltage regulaton through droop Mcro-Grd Power Qualty and Three-Phase Four-Wre Grd- nterfacng Compensator Emergng Generaton Technologes... 7 Chapter 3 Common features of the converter Topologes Prncple of Snusodal PWM generaton Snusodal Pulse wdth modulaton SPWM Spectra Three Phase Snusodal Pulse Wdth Modulaton Non Snusodal reference njecton Fourth wre and neutral handlng Neutral handlng Common applcatons of four legged nverters The Swtchng functon Analyss Swtch Functon v

5 3.4. Calculaton of DC-Ral currents usng the Swtchng Functons Calculaton of DC-lnk capactor Voltages usng the Swtchng Functons Pole mode and Common mode currents DC-Lnk voltage rpples Frequency doman Consderatons Load Modellng DC- Lnk Capactors Szng Capactor szng for Three Legged Converter wth Unbalanced Load/Source Capactor szng for Four Legged Converter wth Unbalanced Load/Source and Three legged converter wth Delta Wye transformer DC-Lnk Capactor Szng for a converter under balanced Load condtons DC-Lnk Capactors szng for a converter under unbalanced load Condtons Sze of Low Pass LC Flter Components Needed PSCAD MATLAB Agreement Verfcatons of THD v requrements on the Output LC Flter Chapter 4. Capactor Md-Pont Topology DC-Lnk Capactor Md-Pont Topology Tme Doman Analyss of the topology Common Mode equvalent Crcut Dfferental Mode equvalent Crcut PSCAD models for verfcaton of the analytcal Models Tme Doman Consderatons... 5 VS under balanced three phase loads... 5 VS wth sngle phase load only (3% mbalance) Frequency Spectrum consderatons Matlab Calculatons for verfcaton of the analytcal models The Common mode Equvalent Schematc The Dfferental mode Equvalent Schematc Total DC lnk Voltage rpples DC Lnk capactors szng Tuned LC lnk and Component sze reducton consderatons...64 Chapter 5. Topology wth Delta-Wye Transformer Three-phase Transformers and ther effects on sequence components Topology wth Delta-Wye Transformer...69 v

6 5.3 Tme Doman Analyss Common Mode/Zero sequence equvalent Crcut Dfferental mode/negatve and postve sequence equvalent crcuts PSCAD models for verfcaton of the analytcal Models Matlab Calculatons of the PSCAD Smulatons DC- Lnk Capactors Szng Non snusodal reference njecton consderatons Tuned LC lnk and Component sze reducton consderatons...8 Chapter 6: Four Legged nverter Topology Four Legged nverter Topology Tme Doman Analyss for Four leg VS Common mode/zero sequence equvalent crcut Dfferental mode/negatve and postve sequence equvalent crcuts PSCAD models for verfcaton of the analytcal Models DC- Lnk Capactors Szng Tuned LC lnk and Component sze reducton consderatons...9 Chapter 7: General Comparsons and Specfc Component calculatons of the topologes General Comparsons of the Topologes Comparson based on the level of DC lnk voltage harmoncs present Comparson based on the DC-Lnk Capactor Sze Comparson based on the Flter components requred Comparson based on Thrd Harmonc njecton consderatons Specfc Component calculatons and fnal comparsons Specfc Norms/standards used Connecton to Grd and harmonc lmts Specfc Converter Values used Requred DC-Lnk Voltage Requred DC-Capactor sze Capactor Md pont VS Topology Four Legged VS and Delta Wye Transformer topologes AC Flter sze and component dmensonng Transformer Sze...98 Chapter 8: Conclusons and Future Work Conclusons...99 v

7 8. Recommendatons Future Work...99 References... Lst of Symbols and Abbrevatons... Lst of Abbrevatons... Lst of Symbols... App. Proof of some mportant equatons...6 App. DC-Lnk Capactor related Dervatons... v

8 Chapter. ntroducton Chapter ntroducton. BACKGROUND The nterconnecton of small, modular generaton sources to low voltage dstrbuton systems can form a new type of power system, the Mcro Grd. Mcro Grds comprse LV dstrbuton systems wth dstrbuted energy sources (mcro turbnes, fuel cells, PV, etc.) together wth storage devces (flywheels, energy capactors and batteres). Such systems can be operated n a non-autonomous way, f nterconnected to the grd, or n an autonomous way, f dsconnected from the man grd. The operaton of mcrosources n the network can provde dstnct benefts to the overall system performance, f managed and coordnated effcently. The output from the power sources are typcally not suted for drect connecton to the mcro grd, whch wll operate at standard frequency and voltage. For ths reason a power electronc nterface s requred. Recent research nto the feld has shown that a control system for each of the mcro sources that emulates the propertes of a synchronous generator has several advantages. Ths way the system wll be less dependent on rapd superor level control. MV ac network N/O loads generaton storage LV mcrogrd Fgure -. A Mcro grd. PROBLEM DESCRPTON.. Mcro Source Grd nterfaces The objectve of the work wll be to evaluate possble concepts for mcro source power electronc grd nterfaces. The possblty of adaptng standard ndustral converters for ths purpose wll be studed n partcular. Fgure- shows varous possble pathways for nterfacng low voltage mcro sources such as PV panels to an LV dstrbuton network wth three phases and a neutral. The system manly has to accomplsh three tasks:. Voltage adaptaton and regulaton. n many cases the output voltage of the mcro source s consderably lower than that of the AC grd.. Galvanc solaton. n several markets t s mandatory that the grd s galvancally solated and should be separated from the source e. g. by a transformer. 3. AC-DC converson. Ths s necessary snce a fltered sne voltage should be produced. 8

9 Chapter. ntroducton The basc topology that should be the focus of ths work can be seen n Fgure -3. t conssts of two stages. The frst steps up and regulates the voltage. The output s a regulated DC voltage. The second stage converts ths DC voltage nto a fourwre three-phase AC voltage that can be connected to the grd. The work should manly be concerned wth ths latter stage. One specfc ssue that should be addressed s how to handle unbalanced condtons resultng from sngle-phase loads connected n the AC grd. Ths could e.g. be electrcal applances n households. n Fgure -4 dfferent ways of achevng the DC/AC converson are dsplayed. n the frst a delta-wye coupled transformer s used to from the neutral requred n the four-wre system. Ths way the zero-sequence resultng from unbalanced loadng s decoupled from the converter. Wth such a system a part of the voltage adaptaton could be made by the transformer whereby a lower DC lnk voltage could be used. n the second alternatve the neutral s formed by the mdpont of the DC lnk. Ths s a smple soluton. One drawback s however those mbalances on the AC sde wll result n a voltage rpple on the DC sde whch may mply that a larger DC capactor s requred. The thrd alternatve uses an addtonal phase leg n the converter to handle the neutral. Ths soluton has the advantage of ndependent control of the neutral voltage, but s lkely to be more expensve and complex than the other solutons. f other promsng solutons are encountered durng the course of the work they should also be nvestgated. LF transformer Natural commutaton Forced commutaton VSC MF/HF transformer Cycloconverter DC mcrosource/ -storage Z-source Converter Lne flter AC mcrogrd Unsol DC/DC converter Boost stage VSC L LCL CM/DM sol DC/DC converter (HF transformer) Full brdge Half brdge Push.pull solated Cuk Seres resonant Flyback Other topology ssues: -Cascadng - Multlevel structures - Soft swtchng Fgure -. DG nterfaces wth LV DC nput. Varous possble path ways. 9

10 Chapter. ntroducton Common DC bus DC storage Bdrectonal DC/DC DC mcrosource Undrectonal DC/DC (P), U(Q) control VSC Lne flter AC mcrogrd AC mcrosource e.g. mcroturbne AC mcrosource e.g. small wnd turbne (Actve) Rectfer (MPPT, voltage adaptaton and regulaton,galvanc solaton) Generc converter For nstance: ABB Multdrve TM Semens SMODRVE 6 TM Fgure -3. Proposed generc nterface for DG sources... Topologes for comparson Fgure -4: Dfferent topologes for nterfacng a DC source to a four-wre LV dstrbuton grd

11 Chapter. ntroducton..3 Assumptons n the comparson As a bass for the comparson of the dfferent concepts the followng assumptons are made wth regard to the AC system. Data of model AC system Rated AC voltage 4 V, 3-phase, 4-wre Rated power of converter kva Current mbalance / rat -3 % Harmonc compatblty Acc. to EC 6-3- or dependng on current level Addtonal assumptons The DC lnk voltage s assumed to be constant at a sutable level. For the transformer-based alternatve the DC voltage does not have to be adapted to the AC sde voltage. The GBT devces wll by necessty have blockng voltages of ether V or 7 V. The GBT swtchng frequency s assumed to be 45 Hz...4 Standard Norms to be adopted Harmonc compatblty Acc. to EC 6-3- or dependng on current level and EEE 547 a standard for nterconnectng Dstrbuted Resources wth Electrc Power Systems are to be adopted..3 MOTVATONS AND OBJECTVES The man am of ths report s to evaluate the dfferent converter topologes wth regard to the followng crtera:. Requred DC lnk voltage.. Requred DC capactor sze. 3. AC flter sze requred to comply wth relevant norms and regulatons regardng harmoncs. Dmensonng of the components. 4. Transformer sze, f applcable..4 SCOPE OF THE PROJECT Ths dploma work ntended to asses the steady state behavour of dfferent three phase Voltage Source nverters for PV type mcro grds shown n Fgure -4, that work ether off grd or grd ted, wth the man focus beng on how these converters handle unbalanced loads wth a current mbalance level beng 3 %. rated

12 Chapter. Lterature revew Chapter Lterature Revew. Mcro grds and state of the art Trends.. MCROGRDS Defnton nterconnecton of small, modular generaton to low voltage dstrbuton systems forms a new type of power system, the Mcro Grd. Mcro Grds can be connected to the man power network or be operated autonomously, smlar to power systems of physcal slands. Fgure -: A general structure of a Mcro grd The Mcro Grd concept assumes a cluster of loads and mcro sources operatng as a sngle controllable system that provdes both power and heat to ts local area. Ths concept provdes a new paradgm for defnng the operaton of dstrbuted generaton. To the utlty the Mcro Grd can be thought of as a controlled cell of the power system, for example ths cell could be controlled as a sngle dspatch able load, whch can

13 Chapter. Lterature revew respond n seconds to meet the needs of the transmsson system. To the customer the Mcro Grd can be desgned to meet ther specal needs; such as, enhance local relablty, reduce feeder losses, support local voltages, provde ncreased effcency through use waste heat, voltage sag correcton or provde unnterruptble power supply functons to name a few. Dstrbuted generaton offers many advantages such as: a) Peak shavng to reduce the overall cost of power by generatng durng peak load hours when the cost of electrcty s hgh and b) Standby generaton to provde power durng system outages untl servce can be restored. Both of the above advantages can be effectvely utlzed f the dstrbuted generaton system s utlty-nteractve. Fgure -: The key concept that dfferentates the mcro grd approach from a conventonal power utlty s that the power generators are small (often referred to as mcro generators, of a smlar sze to the loads wthn the mcro grd). They are also located n close proxmty to the energy users. The generators, and possbly also loads, are then managed to acheve a local energy and power balance. Ths development n dstrbuted generaton has been compared by the Economst wth the changes currently takng place n the telephone ndustry and t has been estmated that, wthn a decade, the market for such equpment wll exceed $6 bllon a year. The US Electrc Power Research nsttute and ABB can foresee the emergence of vrtual utltes whch, by analogy wth the nternet, wll allow ntellgent meterng and swtchng []. The antcpated results nclude reduced envronmental mpact, greater system relablty and lower operatng cost. Mcro grds promse substantal envronmental benefts through hgher energy effcency and by facltatng the ntegraton of renewable sources such as photovoltac arrays or 3

14 Chapter. Lterature revew wnd turbnes. By vrtue of a good match between generaton and load, mcro grds have a low mpact on the electrcty network, despte ther potentally sgnfcant level of generaton. However, to acheve ths, a number of techncal, regulatory and economc ssues have to be resolved before mcro grds can become commonplace... Why mcro grds? The motvaton behnd ths trend les n the potental of the mcro grd concept to delver a sgnfcant reducton of CO emssons, for the followng reasons: The use of both electrcty and heat permtted by the close proxmty of the generator to the user, thereby ncreasng the overall energy effcency; Sgnfcant envronmental benefts made possble by the use of low or zero emsson generators ncludng PV arrays and fuel cells; Low mpact on the electrcty network, by vrtue of good match between generaton and load, despte a potentally sgnfcant level of generaton by ntermttent energy sources Role of Dstrbuted Generaton n addton to meetng future energy needs, t s expected that dstrbuted generaton (DG) wll have ncreasng mportance n a deregulated envronment for a number of reasons: (a) t can provde ndependence and flexblty to the consumer n plannng, and developng the nstallaton. Ths s partcularly mportant for senstve and crtcal loads n envronments subjected to nterruptons and curtalments. (b)the cost of energy produced by DG s decreasng to the pont where t becomes compettve wth grd suppled electrc energy. Power companes can therefore add generaton at crtcal ponts n the power grd, n partcular near loads. Ths can result n sgnfcant savngs n the electrc dstrbuton nfrastructure, partcularly expansons. (c) t allows ndependent producton of electrc energy by a consumer, possbly at a cheaper rate, thus savng on the utlty bll. Excess energy can be posted on the spot market and made to generate a proft. (d) Wth decreasng costs, ndependent power producers (PP) can nstall generaton and connect to the power grd, to sell energy at a proft. Techncal, economc and envronmental benefts Energy effcency Mnmsaton of the overall energy consumpton mproved envronmental mpact 4

15 Chapter. Lterature revew mprovement of energy system relablty and reslence Network benefts Cost effcent electrcty nfrastructure replacement strateges Cost beneft assessment Energy Effcency - Combned Heat and Power Up to now: Central power statons Decentral heat producton n the Future: Decentralzed combned heat and power..3 Types of Dstrbuted Generaton (a) Wnd energy systems: the resource s abundant and these systems are ganng popularty. Power ratngs are steadly ncreasng. (b) Photovoltac cells: although less powerful than wnd energy system, they offer more flexblty and are passve (c) Mcro turbnes: a number of these systems derve from systems developed for the mltary. (d) Fuel cells: although the prncple has been known for many years, these systems have recently receved a large amount of attenton as a less pollutng replacement for crude ol derved generatng systems. (e) Solar dshes: snce these generate heat, they may be combned wth non solar fuels, such as natural gas, resultng n hybrd systems that can be cost effectve and supply contnuous power. (f) Other types nclude gas turbnes, desel engnes and gas fred nternal combuston engnes. A. Mcro turbnes Fgure -3: Mcro turbne electrcal system A typcal scheme s shown n Fg -3. Because the turbnes run at hgh speeds, up to 8, rpm, the ac generator s a hgh frequency generator that cannot be coupled drectly 5

16 Chapter. Lterature revew to the ac grd. An ntermedate dc lnk s used, a dc capactor fed from the dode rectfer. A dc/ac nverter produces voltages at the power system frequency. t s of the voltage source type, and s currently usng GBTs up to the MW range. B. Wnd turbnes The wnd turbne can be operated at ether constant or varable speed and coupled to ether a synchronous or nducton generator producng power system frequences. The latter has been wdely used due to smplcty and lower cost. Fgure -4: (a) Wnd turbne electrcal system of a Varable speed nducton generator. Fgure -4: (b) Wnd turbne electrcal system of a doubly fed varable speed nducton generator. The varable speed turbne has a smpler mechancal system and s the preferred soluton n newer nstallatons. Fgure -4 (a) shows an nducton generator system.. The lne commutated converters are beng replaced wth self commutated, typcally GBT based, converters, Fgure -4 (b). The rotor s fed at a frequency such that the sum of the mechancal and the rotor slp frequences s equal to the ac grd frequency. C. Photovoltac systems A common scheme nvolves the use of a dc/ac nverter, convertng dc energy produced by the cell nto ac voltage synchronzed wth the grd, Fgure -5 []. The control system s desgned to track peak power ponts. The three phase nverter s typcally of the GBT type. 6

17 Chapter. Lterature revew Fgure -5 Photovoltac electrcal converson system. D. Fuel cells The dc voltage produced by the cell s converted nto ac usng a dc/ac nverter, smlar to that of a photovoltac system. Fgure -6: Fuel cell electrcal converson system. Not all renewable generators are synchronous machnes: wnd turbnes are often nducton generators and photovoltac arrays connect to the system through nverters. These two requre very dfferent frequency and load control n order to satsfactorly operate n a system. nverters can be used to control frequency snce the nverter frequency can be controlled ndependently of load. However, nverters do not behave as rotatonal synchronous generators and requre dfferent phlosophes. An asynchronous connecton usng a drect current (DC) coupled electronc power converter mght be b-drectonal, enablng mport and export of power or smply a devce to mport power when local resources were nadequate. An advantage of ths approach s that t solates the mcro grd from the utlty as regards reactve power, load balance etc. Only power s exchanged wth the utlty, the mcro grd s entrely responsble for mantanng the power qualty (frequency, voltage and supplyng reactve power and harmoncs) wthn ts area. Wth an asynchronous lnk the mcro grd mght be unusual n that all ts power wll be suppled through electronc nverters. Some generators, such as photovoltac cells are ntrnscally sources of DC and hence need nverson to connect them to an AC network. Others, for example mcro turbnes may generate AC but are not well suted to operatng a synchronous generator because the frequency s unsutable or varable. Voltage source nverters wth sutable control schemes wll be requred to permt stable operaton of the network wth many small generators attached. Fortunately advances n power electroncs and dgtal controllers mean that sophstcated control strateges are possble and the cost need not be excessve. 7

18 Chapter. Lterature revew..4 Mcro Grd Archtecture Fgure -7: Mcro grd Archtecture Fgure -7 llustrates the basc Mcro Grd archtecture. n ths example the electrcal system s assumed to be radal wth three feeders A, B and C and a collecton of loads. The radal system s connected to the dstrbuton system through a separaton devce, usually a statc swtch. The feeder voltages at the loads are usually 48 volts or less. Feeder A ndcates the presence of several mcro sources wth one provdng both power and heat. Each feeder has crcut breakers and power flow controllers. Consder the power flow controller near the heat load n feeder A. Ths controller regulates feeder power flow at a level prescrbed by the Energy Manger. As loads down stream change the local mcro sources ncrease or decreases ther power output to hold the power flow constant. n ths fgure feeders A and C are assumed to have crtcal loads and nclude mcro sources, whle feeder B s assumed to have non-crtcal loads whch can be shed when necessary. For example when there are power qualty problems on the dstrbuton system the Mcro Grd can sland by usng the separaton devce shown n the fgure. The noncrtcal feeder can also be dropped usng the breaker at B...5 Mcro Source Controller (MC) Mcro source controller s an mportant component of the Mcro Grd nfrastructure. Ths controller responds n mllseconds and uses local nformaton to control the mcro source durng all events. A key element s that communcatons among mcro sources are unnecessary for basc operaton. Each nverter s able to respond to load changes n a predetermned manner wthout communcaton of data from other sources or locatons, whch enables plug and play capabltes. Plug and play mples that a mcro source can 8

19 Chapter. Lterature revew be added to the Mcro Grd wthout changes to the control and protecton of unts that are already part of the system. The basc nputs to ths controller are steady state set ponts for output power, and local bus voltage. Conceptual Desgn of Mcro Grds energy management wthn and outsde of the dstrbuted power system control phlosophes (herarchcal or dstrbuted) slandng and nterconnected operaton phlosophy type of networks (ac or dc, fxed or varable frequency) management of power flow constrants, voltage and frequency devce and nterface response and ntellgence requrements protecton optons for networks of varable confguratons next-generaton communcatons nfrastructure (slow, fast) standardsaton of techncal and commercal protocols and hardware Mcro Grds Herarchcal Control Mcro Grds Control Levels n order to acheve the full benefts from the operaton of Mcro grds, as outlned n the ntroducton, t s mportant that the ntegraton of the dstrbuted resources nto the LV grds, and ther relaton wth the MV network upstream, wll contrbute to optmze the general operaton of the system. To acheve ths goal, a herarchcal system control archtecture comprsng three control levels, as shown n Fgure, can be envsaged [3,4]. Fgure -8: Mcro grd Control Archtecture Local Mcro generator Controllers (MC) and Load Controllers (LC) Mcro Grd System Central Controller (MGCC) Dstrbuton Management System (DMS). 9

20 Chapter. Lterature revew The Mcro generator Controller (MC) takes advantage of the power electronc nterface of the mcro source and can be enhanced wth varous degrees of ntellgence. t uses local nformaton to control the voltage and the frequency of the mcro grd n transent condtons. MCs have to be adapted to each type of mcro source (PV, fuel cell, mcro turbne, etc.) Local Load Controllers (LC) are also nstalled at the controllable loads to provde load control capabltes. The Mcro grd Central Controller (MGCC) functons can range from montorng the actual actve and reactve power of the dstrbuted resources to assumng full responsblty of optmzng the Mcro grd operaton by sendng control sgnal settngs to the dstrbuted resources and controllable loads. The Dstrbuton Management Systems (DMS) to whom multple MGCCS are nterfaced need to be enhanced wth new features related to the operaton of Mcro grds. Mcro grds connected on ther feeders should deally look lke concentrated loads. The ssues of autonomous-non-autonomous operaton of the Mcro grds and the related exchange of nformaton are new mportant ssues. Dsconnecton and re-synchronzaton of Mcro grds durng and post-fault perods need to be evaluated. t s clear that n order to operate a Mcro grd n a coordnated manner t s mportant to provde a more or less decentralzed decson makng process n order to balance demand and supply comng both from the dstrbuted resources and the MV dstrbuton feeder. There are several levels of decentralzaton that can be possbly appled rangng from a fully decentralzed approach to a bascally centralzed control dependng on the share of responsbltes assumed by the MGCC and the MCs and LCs. nterconnected Operaton Mcro Grds can operate: Normal nterconnected Mode sland Mode : Normal nterconnected Mode Connecton wth the man MV grd; Supply, at least partally, the loads or njectng n the MV grd; n ths case, the MGCC: nterfaces wth MC, LC and DMS; Perform studes (forecastng, economc schedulng, DSM functons, etc) slandng Operaton n case of falure of the MV grd (mproved relablty and reslence) Possble operaton n an solated mode as n physcal slands;

21 Chapter. Lterature revew n ths case, the MGCC: Changes the output control of generators from a dspatch power mode to a frequency mode Prmary control MC and LC; Secondary control MGCC (storage devces, load sheddng) Eventually, trggers a black start functon. ntegraton requrements and devce-network nterfaces operaton as the good and model ctzen seamless transton between connecton/slandng reslence under changng condtons operaton fault level management and protecton recovery from dsturbances and contrbuton to network restoraton nterfacng ac and dc networks Safety, modularty, robustness, low losses, calbraton and self-tunng. Modellng and smulaton of Mcro Grds modellng of generator technologes (mcro generators, bomass fuelled generaton, fuel cells, PV, wnd turbnes), storage, and nterfaces load modellng and demand sde management unbalanced determnstc and probablstc load flow and fault calculators unbalanced transent stablty models stablty and electrcal protecton smulaton of steady state and dynamc operaton smulaton of nteractons between Mcro grds Market and Regulatory frameworks for Mcro Grds coordnated but decentralsed energy tradng and management market mechansms to ensure effcent, far and secure supply and demand balancng development of open and closed loop prce-based energy and ancllary servces arrangements for congeston management secure and open access to the network and effcent allocaton of network costs alternatve ownershp structures, energy servce provders new roles and responsbltes of supply company, dstrbuton company, and consumer/customer

22 Chapter. Lterature revew.. Challenges Related to Mcro grds Specfc techncal challenges: Relatvely large mbalances between load and generaton to be managed (sgnfcant load partcpaton requred, need for new technologes, revew of the boundares of mcro grds) Specfc network characterstcs (strong nteracton between actve and reactve power, control and market mplcatons) Small sze (challengng management) Use of dfferent generaton technologes (prme movers) Presence of power electronc nterfaces Protecton Unbalanced operaton.3 Power Electronc nterface Features and Capabltes A crtcal feature of the Mcro grd s the power electroncs. The majorty of the mcro sources must be power electronc based to provde the requred flexblty and to ensure controlled operaton as a sngle aggregated system. Such a system must be capable of operatng despte changes n the output of ndvdual generators and loads. t should have plug-and play functonalty: t should be possble to connect extra loads wthout reprogrammng a central controller (up to a predefned lmt). Some of these loads mght be conventonal. Lkewse t must be possble to add generaton capacty wth mnmal addtonal complexty. These schemes have one element n common: the nterface to the ac dstrbuton grd, a self commutated Pulse Wdth Modulaton (PWM) dc/ac nverter. Ths nterface allows the generaton scheme to be confgured for a number of functons..3. Self commutated converter systems Converters are bascally of two types: (a) Lne commutated, based on thyrstors. (b) Self commutated, usng fully controllable swtches such as the GBT (typcally for low voltage, low and medum power applcatons) or the GTO or GCT (for medum voltage grd medum and hgh power applcatons). The converter usually swtches up to a few l khz or more, dependng upon the applcaton. Ths results n a number of mproved features over lne commutated converters: (a) The nverter voltage harmonc components are large but at a hgh frequency. The ac lne current harmonc components are therefore small. (b) The dynamc response of the nverter s fast snce the delay n changng nverter operaton s on average of the order of half a swtchng perod.

23 Chapter. Lterature revew The same nverter can be used as a rectfer, that s, convert ac nto dc. The combnaton of rectfer and nverter allows the mplementaton of frequency changers, wth ndependent control of voltage and frequency on the both ac sdes. The dc bus allows ths complete decouplng. n addton, energy storage (batteres) can be connected to the dc bus. The dc bus provdes flexblty to the structure and t can be used n a number of ways: (a) A number of rectfers can be connected to a common dc bus. The dc voltage s converted nto ac by a sngle dc to ac nverter, connected to the ac grd. Ths allows transmsson of power n dc rather than ac form, whch has a number of advantages. n partcular, no reactve power s requred to transmt power. Ths means that no reactve power compensaton s requred even for long dstance lnes. A common dc bus also allows a mx of generaton to be combned, for example desel drven generators, wnd energy systems and photovoltac systems. Energy from all of these sources s converted nto ac by one or more dc/ac nverters, connected to one or more ac grds (mult termnal hgh voltage dc HVDC transmsson) or to ndependent loads. (b) f the dc bus s controlled from the ac grd sde, the nverter can provde reactve power, even n the absence of real power on the dc bus. Wnd energy systems can operate as Var compensators n the absence of wnd..3. Power flow control - real and reactve components The converter can be consdered as a statc synchronous ac source, coupled to the ac grd through a reactor, n many cases provded by the couplng transformer. Snce the converter s self commutated, t can produce an ac voltage of an arbtrary ampltude and phase, Fgure -9 (b). n a manner smlar to synchronous generators, Fg. Fgure -9 (c), there are two control varables: (a) The poston of the fundamental component of the nverter output voltage V cl relatve to the ac grd voltage VL defned by the load angleδ, Fgure -9 (d). The power transferred form the nverter to the ac grd, on a per phase bass, s gven by: VLVcl P snδ VL L cosφ X Equaton - 3

24 Chapter. Lterature revew (b) The ampltude of the nverter output voltage, controlled by the modulaton ndex of the PWM pattern generator. Ths ampltude drectly controls the amount of reactve power drawn or njected nto the ac grd: ( V + V cosδ ) VL L cl Q VL L snφ Equaton - X Where, X s the couplng reactance between the nverter and the ac grd. The reactve V cl power depends upon the angle between the lne current fundamental component L and the grd voltage V L. The nverter can therefore be operated at any desred power factor, ncludng unty power factor. Ths s n contrast to lne commutated converters that always operate at a laggng power factor. Fgure -8: P W M nverter power control (reactor may be the transformer leakage reactance). (a) Smplfed representaton. (b) Voltage-current relaton. (c) Per phase equvalent crcut at fundamental frequency ( VL VL, jωl X fundamental frequency (nverter supples vas). ) (d) Phasor dagram at the.3.3 Basc Control of Real and Reactve Power There are two basc classes of mcro sources; one s a D.C. source, such as fuel cells, photovoltac cells, and battery storage, the other s a hgh frequency ac source such as the mcro turbne, whch needs to be rectfed. n both cases the resultng D.C. voltage s converted to an acceptable ac source usng a voltage source nverter. The general model for a mcro source s shown n Fgure -. t contans three basc elements; prme mover, dc nterface and a voltage sourced nverter. Couplng to the power system s through an nductor. The voltage source nverter provdes control of both the magntude and phase of 4

25 Chapter. Lterature revew ts output voltage, V. The vector relatonshp between the nverter voltage, V, and the system voltage, E, along wth the nductors reactance, X, determnes the flow of real and reactve power (P &Q) from the mcro source to the system. Fgure -: nterface nverter System The P & Q magntudes are coupled as shown n the equatons below. For small changes P s predomnantly dependent on the power angle, δ, whle Q s dependent on the magntude of the converter s voltage, V. These provde for a basc feedback loops for the control of output power and bus voltage, E through regulaton of reactve power flow. 3 VE P snδ Equaton -3 p X ( V E cosδ ) 3 VE Q Equaton -4 p X δ δ δ Equaton -5 p V E p.3.4 Voltage regulaton through droop ntegraton of large numbers of mcro sources, mpled n the Mcro Grd concept, s not possble wth basc P-Q controls. Voltage regulaton s necessary for local relablty and stablty. Wthout local voltage control, systems wth hgh penetraton of mcro sources can experence voltage and/or reactve power oscllatons. Voltage control requres care to nsure that there are not large crculatng reactve currents between sources. The ssues are dentcal to those encountered n the control of large synchronous generators. n the power grd the mpedance between generators s usually large enough to greatly reduce the possblty of crculatng currents. n a Mcro Grd, whch s typcally radal, the problem of large crculatng reactve currents s mmense. Wth small errors n voltage set ponts the crculatng current can exceed the ratngs of the mcro sources. Ths stuaton requres a voltage vs. reactve current droop controller. Bascally, as the reactve current generated by the mcro source becomes more capactve the local voltage set pont s 5

26 Chapter. Lterature revew reduced. Conversely as the current becomes more nductve the voltage set pont s ncreased. The functon of the basc controller s shown n Fgure -. The Q lmt shown n the fgure s a functon of the volts-ampere (VA) ratng of the nverter and the power beng provded by the prme mover. Fgure -: Voltage Set Pont wth droop n solated operaton, load-trackng problems arse snce mcro turbnes and fuel cells have slow response and are nerta-less. The prme movers output power tme constants range from to seconds, whch s too slow for most loads. t must be remembered that the current power systems have storage provded though the generators nerta. When a new load comes on lne the ntal energy balance s satsfed by the system s nerta. Ths results n a slght reducton n system frequency. A system wth clusters of mcro sources desgned to operate n an sland mode must provde some form of storage to nsure ntal energy balance. The necessary Mcro Grd storage can come s several forms; batteres or super capactors on the dc bus for each mcro source; drect connecton of ac storage devces (batteres, flywheels etc.); or use of tradtonal generaton wth nerta wth the mcro sources. f the Mcro Grd s not requred to operate n sland mode the energy unbalance can be met by the ac system wthout provdng storage on the Mcro Grd..4 Mcro-Grd Power Qualty and Three-Phase Four- Wre Grd-nterfacng Compensator Mcro-grds can generally be vewed as a cluster of mcro generators connected to the mans utlty grd, usually through some voltage source nverter (VS) based nterfaces. Concernng the nterfacng of a mcro-grd to the utlty system, an mportant area of study s to nvestgate the mpact of unbalanced utlty grd voltages (usually caused by unbalanced system faults or connected loads) on the overall system performance. As a common practce, f the utlty grd voltages are serously unbalanced, a separaton devce, connected between the mcro-grd and mans-grd to provde solaton n the event of mans faults, wll open and solate the mcro-grd. But when the utlty voltages are not so serously unbalanced, the separaton devce wll reman closed, subjectng the mcro-grd to sustaned unbalanced voltages at the pont of 6

27 Chapter. Lterature revew common couplng (PCC), f no compensatng acton s taken. Such an unbalance n voltages can cause ncreased losses n motor loads and abnormal operaton of senstve equpment. An obvous soluton s to balance the voltages wthn the mcro-grd usng some voltage regulaton technques. However large unbalanced currents can flow between the unbalanced utlty grd and mcro-grd due to the very low lne mpedance nterfacng both grds, f only the mcro-grd voltages are regulated [5]. Ths flow of large unbalanced currents can overstress semconductor devces wthn the nterfacng nverters and system components such as overhead lnes and feeder cables. For low voltage dstrbuton where mcro-grds are usually constructed wth a four-wre confguraton to supply both sngle-phase and three-phase loads, ths problem s further complcated by the flow of zero-sequence currents through the lne and neutral conductors. To mtgate the above-mentoned complcatons, a grd-nterfacng power qualty compensator for three-phase four-wre mcro-grd applcatons s proposed n recent papers [6]. The proposed compensator s to be used wth each ndvdual dstrbuted generator (DG) and t conssts of two optmally controlled four-phase-leg nverters (a shunt and a seres) Operatng together, the two four-leg nverters can compensate for all the unwanted postve-, negatve-, and zero-sequence voltages/currents wthn the system, enhancng both the qualty of power wthn the mcro-grd and the qualty of current flowng between the mcro-grd and the utlty. Specfcally, the shunt four-leg nverter s controlled to ensure balanced voltages wthn the mcro-grd and to regulate power sharng among the parallel-connected DG systems. To complement, the seres nverter s controlled to nject negatve- and zero-sequence voltages n seres to balance the lne currents, whlst generatng zero real and reactve power..4. Emergng Generaton Technologes n terms of the currently avalable technologes, the mcro sources can nclude fuel cells, renewable generaton, as wnd turbnes or PV systems, mcro turbnes and nverter based nternal combuston generators. One of the most promsng applcatons of ths new concept corresponds to the combned heat and power CHP applcatons leadng to an ncrease of the overall energy effectveness of the whole system. Most emergng technologes such as mcro-turbnes, photovoltac, fuel cells and natural gas fred nternal combuston engnes wth permanent magnet generator requre an nverter to nterface wth the electrcal dstrbuton system. Photovoltac and wnd-power are mportant renewable technologes that requre an nverter to nterface wth the electrcal dstrbuton system. 7

28 Chapter3: Common features of the Converter Topologes Chapter 3 Common features of the converter Topologes 3. Prncple of Snusodal PWM generaton Natural samplng Ampltudes of the trangular wave (carrer) and sne wave (modulatng) are compared to obtan PWM waveform The Ampltude modulaton rato m a s defned as Ampltude of the modulatng waveform Vˆ control Am m a Ampltude of the carrer waveform Vˆ A And the frequency modulaton rato m f ( p) s gven by frequency of the carrer waveform m f p frequency of the modulatng waveform Where, f m s the desred fundamental frequency of the nverter output voltage. f 3.. Snusodal Pulse wdth modulaton The swtches n the voltage source nverter (Fg.3-) can be turned on and off as requred. n the smplest approach, f the top swtch s turned on and off only once n each cycle, a square wave waveform results. However, f turned on several tmes n a cycle an mproved harmonc profle may be acheved. tr f f c m c U dc p + C U dc C n V Fgure 3-: Smple Voltage Source nverter n the most straghtforward mplementaton, generaton of the desred output voltage s acheved by comparng the desred reference waveform (modulatng sgnal) wth a hghfrequency trangular carrer wave as depcted schematcally n Fg.3-. Dependng on whether the sgnal voltage s larger or smaller than the carrer waveform, ether the postve or negatve dc bus voltage s appled at the output. Note that over the perod of one trangle wave, the average voltage appled to the load s proportonal to the ampltude of the sgnal (assumed constant) durng ths perod. 8

29 Chapter3: Common features of the Converter Topologes Fgure 3-: Prncple of Pulse Wdth Modulaton The resultng chopped square waveform contans a replca of the desred waveform n ts low frequency components, wth the hgher frequency components beng at frequences of and close to the carrer frequency. Notce that the root mean square value of the ac voltage waveform s stll equal to the dc bus voltage, and hence the total harmonc dstorton s not affected by the PWM process. The harmonc components are merely shfted nto the hgher frequency range and are automatcally fltered due to nductances n the ac system. Controllng the modulaton ndex controls the ampltude of the appled output voltage. Wth a suffcently hgh carrer frequency, the hgh frequency components do not propagate sgnfcantly n the ac network (or load) due the presence of the nductve elements. However, a hgher carrer frequency does result n a larger number of swtchngs per cycle and hence n an ncreased power loss. Typcally swtchng frequences n the -5 khz range are consdered adequate for power systems applcatons. Also n three-phase systems t s f c advsable to use a pulse number p 3 k, ( k N ) so that all three waveforms are f m symmetrc. Note that the process works well for ma. For m a >, there are perods of the trangle wave n whch there s no ntersecton of the carrer and the sgnal as n Fg.3-3. However, a certan amount of ths over modulaton s often allowed n the nterest of obtanng a larger ac voltage magntude even though the spectral content of the voltage s rendered somewhat poorer. Note that wth an odd pulse number, or the rato fc/fm, the waveform s ant-symmetrc over a 36 degree cycle. Wth an even number, there are harmoncs of even order, but n partcular also a small dc component. Hence an even number s not recommended for sngle phase nverters, partcularly for small ratos of fc/fm. 9

30 Chapter3: Common features of the Converter Topologes Fgure 3-3: Over modulaton: m a SPWM Spectra Although the SPWM waveform has harmoncs of several orders n the phase voltage waveform, the domnant ones other than the fundamental are the ones of order p and p±, f c where, p. Ths s evdent for the spectrum for p5 and m a.8 shown n Fg.3-4. f m Note that f the other two phases are dentcally generated but apart n phase, the lnelne voltage wll not have any trplen harmoncs. Hence t s advsable to chose p 3k f f c m,( k N ) as then the domnant harmonc wll be elmnated. t s evdent from Fg 3-4 (b), that the domnant 5th harmonc n Fg. 3-4 (a) s effectvely elmnated n the lne voltage. Choosng a multple of 3 s also convenent as then the same trangular waveform can be used as the carrer n all three phases, leadng to some smplfcaton n hardware. t s readly seen from ( PWM ( θ )) E, where E s the dc bus voltage, that the rms value of the output voltage sgnal s unaffected by the PWM process. Ths s strctly true for the phase voltage as trplen harmonc orders are cancelled n the lne voltage. However, the problematc harmoncs are shfted to hgher orders, thereby makng flterng much easer. 3

31 Chapter3: Common features of the Converter Topologes Fgure 3-4: SPWM harmonc spectra: p5, ma.8 3. Three Phase Snusodal Pulse Wdth Modulaton Three-phase reference voltages of varable ampltude and frequency are compared n three separate comparators wth a common trangular carrer wave of fxed ampltude and frequency (Fg.3-5). Each comparator output forms the swtchng-state of the correspondng nverter leg. n fgure 3-5, a saw-tooth- or trangular-shaped carrer wave, determnng the fxed PWM frequency, s smultaneously used for all three phases. Fgure 3-5: Prncple of three phase Snusodal PWM and generaton of swtchng sequences Ths modulaton technque, also known as PWM wth natural samplng, s called snusodal PWM because the pulse wdth s a snusodal functon of the angular poston n the reference sgnal. As mentoned before, choosng an odd pulse number for three phase nverters results n an odd symmetry, and hence all the even harmoncs wll dsappear from the out put phase 3

32 Chapter3: Common features of the Converter Topologes voltages. And also f the pulse number s a multple of 3 n a three phase SPWM, the domnant harmoncs at odd multples of p n the lne to lne voltages would be suppressed [9]. f the frequency modulaton rato s not an nteger, t wll result n sub harmoncs of the fundamental frequency that are not desred n most applcatons. 3.. Non Snusodal reference njecton t has been recognzed that the maxmum modulaton ndex of a three phase nverter PWM system can be ncreased by ncludng a common mode thrd harmonc term nto the target reference waveform of each phase leg. [8] Ths thrd harmonc component does not affect the lne to lne fundamental output voltage, snce the common mode cancels between the phase legs, but t does reduce the peak sze of the envelope of each phase leg voltage The same thrd harmonc s added to each of the three reference voltages. Addng thrd harmoncs agrees wth a smultaneous varaton of the potental n all phases, thus not recognzed at the termnals of an ac motor wth solated neutral pont: u ab ua ub ( ua + ut ) ( ub + uthrd ) hrd Therefore, the ntroducton of a thrd harmonc does not dstort the lne voltages snce thrd harmonc components n the phase voltages are cancelled. Hence the modulaton ndex m a can be ncreased beyond. wthout movng nto over modulaton.over modulaton s known to produce low-frequency baseband dstorton and s to be avoded f possble. Fgure 3-6: njecton of a thrd harmonc and modulaton A geometrcal calculaton yelds the maxmum possble ncrease of the lnear area wth the harmonc ampltude beng /6 of the reference voltage ampltude. Such an njecton of a thrd harmonc results n a 5.5% hgher maxmum output voltage wthout over modulaton. But some researchers [8] have proposed that the optmum thrd-harmonc njecton component should have a magntude of 5% of the target fundamental (.e. wth mnmal at njecton of a thrd harmonc wth the ampltude beng /4 of the reference voltage ampltude), argung that ths leads to a reduced harmonc dstorton. 3

33 Chapter3: Common features of the Converter Topologes 3.3 Fourth wre and neutral handlng 3.3. Neutral handlng Power electroncs converson systems, employed as controlled AC power sources, often feeds a star connected three-phase load wth accessble neutral termnal. The currents flowng on each phase are generally not balanced so, f a transformer s not requred, a connecton to the neutral termnal should be provded by addng an extra wre to the nverter. The load neutral termnal can be connected to the nverter usng two dfferent topologes: o three-phase four-wre, n whch the neutral pont s connected drectly to the mdpont of the supply voltage by means of a capactor dvder (splt dc lnk capactors topology) o Three-phase four-leg, employng an addtonal nverter leg that permts to modfy the neutral pont voltage. Wth the splt dc lnk capactors the three-phase nverters becomes three ndependent snglephase half brdge nverters, and the dc lnk capactor wll handle the neutral current drectly. Therefore, hgh capactance s requred. Four-leg converter whch s able to provde zero sequence voltage, so as to handle the neutral current caused by the unbalanced load or source uses the fourth leg to control AC neutral pont, then there are three ndependent voltages and keep the balance of the three-phase output voltages n unbalanced three-phase loads. The three-phase four-leg topology, llustrated n Fg.3-7, requres two addtonal power swtches ( S np and S nn ) and a more complex control strategy, but t offers dfferent advantages, such as a reducton of neutral currents and the possblty of neutral pont voltage control. S ap Sbp S cp S np S an S bn S cn S nn Fgure 3-7: Three-phase four-leg nverter Common applcatons of four legged nverters There s a growng nterest n four-leg converters for three phase four-wre applcatons. Some of the typcal applcatons are as follows. ) Dstrbuted power generators [] [6], such as mcro-turbne generators and fuel cell based generators, whch may run n ether stand-alone or grd parallel mode. These dstrbuted power generators adopt four-leg nverters to provde a three-phase output wth a neutral connecton. Stmulated by utlty deregulaton, ths type of equpment s growng rapdly and wll have a larger market share [7], [8]; 33

34 Chapter3: Common features of the Converter Topologes ) Actve power flters [9] [4], where four-leg converters are proposed for compensatng the harmonc current through the neutral pont; 3) Three-phase PWM rectfers [5], [6], where the addtonal fourth leg provdes flexblty to deal wth the lne dstorton and mbalance, as well as fault tolerant capablty. 4) Common mode nose reducton [7]. 3.4 The Swtchng functon Analyss 3.4. Swtch Functon The Swtch Functon concept s based on Logcal Swtchng constrants on The DC lnk capactors whch should not be short crcuted and the nductor should not be open crcuted, whch result n complementary Swtchngs of the top s and bottom, x a, b, c, swtches of an nverter leg swtches as: s s, where s and s can take values of ether + or. xp + xn xp xn xp s { } xn Udc p + C s xp L U dc C n s xn V Fgure 3-8: nverter Leg Swtches The analyss s based on representng the complementary actons of the upper and lower th GBT swtches of the x converter leg (x representng the, b or c phase) by the Swtch Functon sx. The symbol sx takes on the values of + and. Let s, x { a, b, c}, be the swtch functons of n-phase as defned as: x ), when the upper swtch s ON and the lower swtch s OFF; s x ) s x, when the upper swtch s OFF and the lower swtch s ON. Thus s and s xp xn can be related to s x as xp ( s x + s ) and s ( ) xn s x The currents of the dc upper bus and lower bus can be wrtten n terms of the swtch functons and the ac currents,, : a b c p {( s a + ) a + ( s b + ) b + ( s c + ) c } upper dc ral current Equaton 3- n a a b b {( s ) + ( s ) + ( s ) } c c lower dc ral current Equaton 3- The formula obtaned from conservaton of ac-sde power wth dc-sde power [9] s: 34

35 Chapter3: Common features of the Converter Topologes d { ma a + mb b mc c th + }, modulatng functon the of x phase Equaton 3-3 m x But ( p n ) saa + sbb scc d + Equaton 4- The two formulas n Equaton 3-3 and Equaton 4- are dentcal. Ths s because, as shown by the algebrac sums of the shaded areas n Fg. 3-9, the local averages of s x (t) and (t) are equal n every samplng perod ΔT [4], that s: ( n+ ) ΔT nδt m x ( n+ ) ΔT S ( t) dt m ( t) dt Equaton 3-4 x nδt x Fgure 3-9: Equal Local Averages 3.4. Calculaton of DC-Ral currents usng the Swtchng Functons n a smlar fashon as was explaned n Equatons 3- and 3-, the dc ral currents for an n legged converter (n3 or 4) can be calculated n a generalzed form as: n p ( s + ), n,,3, 4 upper dc ral current Equaton 3-5 n n ( s ), n,,3, 4 lower dc ral current Equaton Calculaton of DC-lnk capactor Voltages usng the Swtchng Functons For an n legged VS, wth the DC lnk capactor s thought of as beng splt n to two equal capactors and the voltages across them beng u,across the upper capactor and u,the p 35 n

36 Chapter3: Common features of the Converter Topologes voltage on the lower DC capactor, the out put phase voltages ( u a, b, c) legs can now be expressed n a general form as: {( s + ) u p + ( s ) un,... of each nverter u ( t) } nverter phase leg output voltage Equaton Pole mode and Common mode currents The Current that flows across the neutral of a three phase system s termed as the common mode current, whch n frequency doman corresponds to zero sequence terms. The dfferental mode or the pole mode currents are the currents that crculate among the nverter legs and not across the neutral wre. For a three phase system wth no neutral wre connected, there wll be only dfferental mode currents crculatng among the crcut components. n a three phase VS, the dfferental mode currents are those currents that crculate across the upper and lower dc rals DC-Lnk voltage rpples n a balanced operaton of the three phase VS, deally there wll be no rpple currents flowng across the DC-lnk capactor, hence the DC lnk voltage would not have larger rpples and would almost be constant. But when there are larger unbalanced loads connected to the three phase VS, there would be rpple currents flowng through the DC lnk capactors, hence these capactors would have larger rpples up on them dependng on the level unbalances. n general, when there are no rpple currents flowng through the Dc lnk capactor, the only voltage across the capactor s the pure DC voltage, and no current flows through the capactor. But when there s a rpple current flowng across the capactor, the rpple voltage Δu dc, can be calculated as Δu Where, dc C dc dt. s the rpple current across the DC capactor c c Cdc 3.5 Frequency doman Consderatons f the output voltages of the nverter legs are perodc,.e. f u t) u ( t + T / 3) u ( t + ( 3 T / 3), t can be shown that the set of phasors correspondng to these voltages of a certan harmonc order,, and,wll form ether symmetrcal or zero-sequence systems. Dependng U,k U, k U 3, k on the harmonc order, these systems can be charactersed as follows: k + 3r Pure postve sequence k + 3r Pure negatve sequence k 3 + 3r Pure zero sequence Where, r,, etc. 36

37 Chapter3: Common features of the Converter Topologes As the waveforms generally fulfl half-wave symmetry, n practce there wll be no even harmoncs. But when the nverter feeds unbalanced loads, the zero sequence as well as the negatve and postve sequence currents flowng across the DC lnk capactors would result n Voltage unbalances between the DC lnk capactors and addtonal rpple voltage on the out put voltage of the nverter legs. For an unbalanced loads at the fundamental order connected to the nverter legs, the zero sequence current at the fundamental order would result n a voltage mbalance at the DC lnk capactors at the same frequency order, and an addtonal voltage dstorton at same frequency order at the output voltages. A negatve sequence current at the fundamental frequency due to unbalanced load connected, would result n voltage dstorton at the DC lnk capactors of twce the fundamental frequency order. 3.6 Load Modellng Z sh Z L L Fgure 3- (a) Load Modelled as mpedance n Parallel wth a current source Fgure 3- (b) Load model Equvalent approxmaton Zsh << ZL For the purpose of studyng manly the effect of unbalanced loads on the DC capactors, the loads are modelled as current sources n parallel wth ther mpedances for convenence. For the purposes of analysng the nverter behavour whle operatng grd connected, the loads can be modelled as voltage sources n seres wth ther mpedances. Normally the load mpedance of a current-type load ZL s much larger than the source mpedance ZS, therefore, the equvalent crcut can be smplfed as shown n Fg 3- (b) The loads are modelled as current sources at the fundamental frequency (no rpples) n parallel wth mpedances, but snce the parallel mpedances of loads are generally very hgh, they can be neglected and can be thought of as beng ncluded on the shunt mpedance of the flters. Note: n all the smulatons and calculatons n the comng chapters the pulse number s assumed to be 8. 37

38 Chapter3: Common features of the Converter Topologes 3.7 DC- Lnk Capactors Szng 3.7. Capactor szng for Three Legged Converter wth Unbalanced Load/Source Fgure 3-: A Three Legged nverter wth Capactor-Mdpont topology Ths secton deals wth the desgn procedures to select capactor values n such a way as to ensure proper operaton of the nverter for varous load condtons, and to mantan an acceptable voltage rpple across the DC-lnk capactors. n the nverter topology shown n Fgure 3-, the DC bus capactors are used as reservors of energy, n order to mantan a constant DC voltage and to reduce the voltage dstortons under dfferent load condtons. Under szed capactors would ncur very large voltage dstortons, whle over szng would ncur hgher costs and problems of hgh startng currents. n desgnng the DC lnk capactors the followng assumptons are made: ) n Steady state the rpple voltage magntude s very small compared to the average voltage ) The Converter and flters are lossless.e. All the energy n the DC-lnk capactors s fully utlzed Capactor szng for Four Legged Converter wth Unbalanced Load/Source and Three legged converter wth Delta Wye transformer All the assumptons made above regardng the rpple voltage magntude and the flter components beng lossless holds n for these converters DC lnk capactor szng calculatons also. The Only dfference between the three legged converter and the four legged converter n terms of DC lnk capactor szng s the fact that n the later the zero sequence current would not flow across the DC lnk capactors, and hence no sgnfcant common mode voltage 38

39 Chapter3: Common features of the Converter Topologes rpples problems as was n the case of Splt md-pont capactors case. The same holds for the Topology wth Delta Wye Transformers to decouple the zero sequence currents resultng from the unbalances DC-Lnk Capactor Szng for a converter under balanced Load condtons When the three phase loads are balanced, the rpples across the DC lnk capactors would only be of hgh frequency orders, and hence for such a hgh swtchng frequency, deally there wll be no sgnfcant rpple across the DC lnk capactors. For such a condton, the requred DC lnk capactor sze would be determned manly by the hold up tme requrement, t h.e. the tme t takes the current across the DC capactor to reach the Rated DC current when all the rated power of the converter s fed to the DC lnk capactors. Ths means that the capactor value s chosen n such a way that over a desred tme nterval, t delvers the requred power to the load wth an acceptable drop n the DC voltage C dc t d h, Capactor szng for balanced loads Δudc Equaton 3-8 n general, when the three phase loads are balanced, there would be no low order frequency rpple power drawn from the DC-lnk capactors, nor the neutral current would flow nto the splt capactors, hence deally we can say there s almost no rpple voltage across the DC-lnk capactors DC-Lnk Capactors szng for a converter under unbalanced load Condtons When the three phase loads are unbalanced, the voltage across the DC-lnk capactors wll have a rpple at twce the fundamental frequency, due to the negatve sequence load current, as well as a zero sequence rpple at the fundamental frequency (when there s a common mode current flowng across the capactors, (only for the splt Capactor Md-pont topology) The worst case for these capactors loadng would be when a sngle phase load alone s connected, whch would result n the hghest rpple n the DC lnk voltage. The Mnmum Capactor sze requred to handle Negatve sequence load currents: When the three phase loads are unbalanced, there would be power oscllatons, whch would result n hgher dfferental mode voltage rpples across the DC lnk capactors. 39

40 Chapter3: Common features of the Converter Topologes C dc Fgure 3-: DC-lnk capactors seres equvalent for negatve sequence For a certan specfed value of maxmum allowed DC-lnk capactor voltage rpple, mnmum DC-lnk capactance needed to handle the negatve sequence load current C can be calculated from the power and energy relatonshps at the DC lnk dc _ Mn NS capactors,as s gven by Equaton 3-3 of [App.],whch s : Δu dc the C 3 _ peak ma dc _ Mn: NS Equaton 3-3 8ω Δudc Hence, Equaton 3-3 shows that the mnmum DC-lnk capactance sze for negatve sequence rpples s dependent upon the modulaton ndex level, as well as the maxmum allowed rpple voltage, the peak value of the negatve sequence current, and the frequency of the system. The Mnmum Capactor sze requred to handle zero sequence load current: For the three phase four wre topologes where there s a common mode current flowng back to the md pont of the DC lnk capactors, these currents would result n chargng and dschargng there capactors oppostely, hence there would be voltage mbalances across these DC lnk capactors. n a smlar fashon as was for the negatve sequence, for a certan specfed value of maxmum allowed DC-lnk capactor voltage rpple, Δudc the mnmum DC-lnk capactance needed to handle the zero sequence load current (The neutral current),c dc _ Mn ZS can be calculated as follows: For the topology shown n fgure () above, we can see that the zero sequence current due to unbalanced load flows through the md pont of the DC-Lnk capactors and t splts nto two. Hence the capactors can be treated as beng n parallel, and ther equvalent becomes C dc. C dc Fgure 3-3: Zero sequence current flows across the splt capactors treated as beng connected n parallel Hence ths C dc capactor should handle the neutral current ncludng the worst case of only a sngle phase load, n whch all the phase current flows through the neutral and across the capactors. n mn cos( ωt + ϕ Zero ) 3 cos( ω t + ϕ Zero ) Where, mn s the peak value of the neutral current and s the peak value of zero-sequence current, andϕ Zero s the phase angle between the converter phase voltage and zero sequence current. 4

41 Chapter3: Common features of the Converter Topologes The peak to peak common mode voltage rpple across each capactor due to the neutral current s twce the peak voltage rpple value across each of the DC-lnk capactors u dv 3 Δu C ω dc dc C 3 3 dc _ Mn ZS Equaton 3-3 ωδu dc ωudv Where, udv s the peak to peak common mode rpple across each capactor and Δudc s the peak value of the rpple voltage or half the peak to peak rpple value. Hence, Equaton 3-3 shows that the DC-Capactor sze requred to handle the mnmum allowed zero sequence rpple voltage across the DC-Lnk capactors s dependent up on the zero sequence current flowng across the neutral wre as well as the system frequency,the maxmum allowed peak voltage rpple, and not on the modulaton ndex. 3.8 Sze of Low Pass LC Flter Components Needed The Low pass LC flter s used to flter out undesred swtchng frequency components from the converter out put voltage, n order to meet the requrements set up by Standards for grd connecton as well as loads. Snce the pulse number used s 8, whch s a hgh number, the sze of flter components needed shall be assumed to be same for all the topologes, as the flters have no contrbuton to the energy storage. The Flter components are szed amng at gettng an deally snusodal out put voltage. As the pulse number s hgh for the VS converters consdered here, the effect of low order harmoncs on the Flter szng would be mnmal, and hence care should be taken n handlng the domnant harmoncs of order f s and ts multples. The Low pass flter components szng here s for the purpose of handlng harmoncs from the SPWM swtchng of the VS, and amed at gettng an deally rpple free voltage before connectng to the grd or to loads as specfed by standards mentoned below. Accordng to EEE 547 standard [A], whch s a standard for nterconnectng Dstrbuted Resources wth Electrc Power Systems, and EEE 59[B], Recommended practces for Utltes, for voltages below 69 kv, the Total Voltage Dstorton,THD[%] must be less than 5[%]. For any harmonc order n, the per phase equvalent crcut of the LC Flter can be drawn as shown n Fgure 3-4 below. jnx L V n jx C n V o Fgure 3-4: Equvalent Crcut of LC Output Flter for a harmonc order n 4

42 Chapter3: Common features of the Converter Topologes The Flter nductor, L can be assumed to have a value of 5[%] of the base mpedance of the system.e..5 p.u.,whch s a reasonable value because we wll get very small voltage drops of the fundamental across the nductor n p.u. for ths value and hgh losses for hgh order harmoncs. Hence knowng p u ω πf ω and ( X L ).5p. u., to fnd L ω pu., b ( ) pu pu Snce, Z. 6Ω X ( L) Z.6Ωx.5 p. u. 4Ω b L ω pu b And X L L ω b.4ω μH xπx5x The value of the flter capactor would also be calculated as follows: From the equvalent crcut we can wrte the voltage transfer functon for a certan harmonc order n as: jx C Vo H n n Equaton V jx n C X L jnx L + n n X C We can assume a certan attenuaton of a certan harmonc order n order to fulfll the requrements of the standards for THD to be 5[%]. For example, we can assume the rato of the nput voltages to out put voltages of the flter for a certan harmonc order to be 3[%], Hence, H n V V o n n X X L C.3 n X X L C 3 n X X L C + 3 X X L C n X n C X L For the pulse number of 8 n ths task, we have to get an attenuaton of 3[%] of the harmonc at the swtchng frequency, accordng to the above assumptons. Hence, 4

43 Chapter3: Common features of the Converter Topologes ω C (8) ( X ).5p. u p.u C pu ( X ).6Ωx8.664 p.u Ω X Z x C b C pu C ϖ X b C ( xπx5)( 45.86) 69.4μF Thus the Cut off frequency of the Low Pass LC flter would be, f C.9 p.u (.9x5) Hz 9. 5Hz π LC The Total Harmonc Voltage dstorton THD v s gven by Vn THD v n V Usng Matlab modules for calculaton of THD v for a pulse number of 8, the requrements of the standard shall be checked and f not fulflled the above assumed 3[%] rato of the output voltages to the nput voltages of the flter for a certan harmonc order can be reduced further to a smaller value teratvely untl the requrement of THD v to be less than 5[%] s fulflled PSCAD MATLAB Agreement Verfcatons of requrements on the Output LC Flter THD v Output Voltage THD Calculatons and Comparsons for the Out put voltage of PSCAD smulatons and deal Matlab analytcal calculatons were done for a case where the DC-Lnk Capactors are not connected and only the DC-Lnk Voltage s connected for the purpose of THD agreement verfcatons only. Analytcal Matlab Values The THD calculated analytcally before the flter s THD v 5.3 [%] The THD just after the output of the flters for the deal case THD [%] The Rato of the 8st harmonc to the fundamental n order to check f the condton of (3%) attenuaton by the flter at the swtchng frequency was met or not s found to be.99 [%] whch shows that t was met. PSCAD-Smulaton Values After proper smulaton tme as well as soluton tme adjustments n PSCAD the smulatons were done and these fles were exported to Matlab as excel fles and the THD Calculaton was carred out by Matlab on the PSCAD fles mported. Thus the result found for the out put voltage was THD v [%].Ths s THD just after the output of the flters for the Transported PSCAD fles. (Note: only one cycle was taken n steady state for ths case and as well the Matlab analytcal calculatons of THD as well are based on one cycle) 43 vo

44 Chapter3: Common features of the Converter Topologes The values are very close but reasons for the slght dfference mght be due to dfferences n solvng schemes.e. PSCAD soluton tme steps and number of samples taken n Matlab. Here we can have a look of how the FFT plots of the two cases would look lke: n Fgure 3-5 below, the fgure on the left s the FFT of the actual PSCAD smulaton values ther FFT done n Matlab and the fgure on the Rght s from the fles from Matlab (Analytcal Calculaton). Fgure 3-5: Output Voltage FFT spectrum after the flter n PSCAD and MATLAB 44

45 Chapter 4: Capactor Md Pont Topology Chapter 4. Capactor Md-Pont Topology 4. DC-Lnk Capactor Md-Pont Topology z dc p d + d u p C dc L V A v u dc o v 3 V B VC u n C dc v 3 C L L L3 z dc n d - d n Fgure 4--: Three-phase VS wth Capactor-Md Pont topology connected to loads Modelled as current sources n ths topology the md pont of the DC-Lnk capactors serves as a neutral wre connecton pont. n the followng sectons of ths chapter the tme doman as well the frequency doman analyss of ths partcular topology s presented. n the analyses the mpedance of the DC sde s neglected and s assumed to be very hgh, and that the DC Voltage s assumed to be properly rectfed DC wth no rpples. 4. Tme Doman Analyss of the topology n order to facltate the analyss the followng defntons are made frst: u ( u + u + u3 ) Common-mode AC sde voltage Equaton 4-3 u ' u u Dfferental-mode AC sde voltage, phase Equaton 4- ( ) Common-mode AC sde current Equaton ' d d Dfferental-mode AC sde current, phase Equaton 4-4 ( p n ) Pole mode DC sde current Equaton 4-5 ( p n + ) Ground mode DC sde current Equaton 4-6 Defnng average and mbalance components of the DC lnk voltage as follows: u p + un ud Average half DC-Lnk Voltage Equaton 4-7 u p un udv DC-Lnk mbalance voltage Equaton

46 Chapter 4: Capactor Md Pont Topology The swtchng functon S (t), tells whether the converter connects the phase outlet to the upper DC ral ( S ) or the lower DC ral ( S ). t changes sgn whenever a phase leg s commutated. Followng smple arthmetcal manpulatons, expressons for lnkng AC and DC can be derved as follows: (for proofs see Appendx []) u ( t) s ( t) u + u Dfferental-mode AC sde voltage, phase [] Equaton 4-9 d dv And thus: u ( t) [ s( t) + s ( t) + s3 ( t) ] u d + udv For the common-mode voltage [] Equaton 4-3 For the currents, the followng always apples: d ( s + s + s33 ) Pole/dfferental mode DC ral current [3] Equaton Ground/common mode DC ral current [4] Equaton 4-3 d L ( L + L + L3 ) Common mode Load current Equaton ' L Dfferental mode Load current,phase Equaton 4-4 L L The Equvalent crcuts for common mode as well as dfferental mode can be derved from above equatons (Equaton 4- to Equaton 4-9) 4.. Common Mode equvalent Crcut When the Md pont of the DC lnk capactors are connected to the neutral wre, due to the SPWM swtched common mode components or due to unbalanced loads, low order common mode current flows through the md pont of these capactors, and t splts between the two DC rals. Equaton 4-5 and Equaton 4- show how the common mode current, d dvdes equally between the upper and lower DC rals. These common mode currents flow n opposte drectons across the two DC lnk Capactors, hence they result n chargng and dschargng these two capactors oppostely. Ths condton gves rse to a voltage mbalance across these two equal capactors. Equaton 4- shows that the voltage mbalance u dv s seen at the output of a phase leg as a common mode voltage (projected to the AC sde), and that ths dstorton s not modulated. Puttng the above mentoned ponts n mnd, the equvalent crcuts are sketched as follows: 46

47 Chapter 4: Capactor Md Pont Topology (a) DC sde (both poles shown) u dv u dv Fgure 4- (a): Common-mode DC sde Equvalent Crcut (b) AC sde (one phase) ( s + s + s ) u / 3 3 d u dv Fgure 4- (b): Common-mode AC sde Equvalent Crcut Z dc Neglectng the DC sde mpedance,, and notng that the upper and lower DC half equvalent crcuts n Fgure 4- (a) are symmetrcal,the two halves can be vewed as parallel halves, hence they can be ntegrated n to one crcut as shown n Fgure 4- (c) below. Fndng the approprate scale for matchng the DC sde and AC sde common mode currents, the AC sde per phase equvalent crcut s also drawn n Fgure 4- (c) below. (c) Combned crcut u dv A ' A d ( s + s + s 3) ud / 3 B d ' B u dv 3 ( d ) Fgure 4- (c): Both the DC sde halves combned and per phase AC sde Equvalent crcut shown 47

48 Chapter 4: Capactor Md Pont Topology ' ' n Fgure 4- (c) above, the termnals A - A and B - B, have same voltage across them and current d through them. Hence these two termnals can be vewed as dentcal. Therefore the AC and DC sdes can be combned as shown n Fgure 4- (d) below. u dv ( s + s + s ) u / 3 3 d u dv Fgure 4- (d): Combned Common Equvalent crcut Omttng DC sde mpedance 4.. Dfferental Mode equvalent Crcut The dfferental mode currents (postve and negatve sequence harmoncs), whch are swtched, are less sgnfcant compared to the Common mode currents, whch are not swtched, from the pont of vew of the rpple voltage they mpose upon the DC-Lnk Capactors. Even though the dfferental mode currents are of smaller magntudes, wthout loss of generalty ther behavour must be explaned reflectng the fact that dfferental mode rpples are agan modulated. From Equaton 4-7 above, the average half DC-Lnk Voltage, u d,whch s gven by u p + un ud,contans dfferental mode rpple voltages due to the dfferental mode rpple current that flows across each capactor. Hence, s a combnaton of the pure half DC lnk voltage ( u dc u d ) and the dfferental mode rpple voltage across each DC Lnk Capactor. The dfferental mode rpple voltage Δ Hence, u u u d, s gven by Δu d C dc dt. dc d + Δud Average half DC-Lnk Voltage Equaton 4-5 d From Equaton 4-9, t can be noted that ths dfferental mode rpple s modulated, and ths shows that there s a lnk between AC and DC sdes. But due to the non lnearty of the AC and DC sde dfferental mode rpple currents because of the swtchng of the dfferental mode rpple voltages, an equvalent crcut jonng both the AC and DC sdes s not feasble, snce due to the swtchng, AC sde harmoncs of dfferent orders from that of the DC sde voltage rpple would arse, and s not a lnear relatonshp. Hence ther behavour must be explaned wth the AC and DC sdes treated separately, there s no lnear lnk as was n the case of common mode rpples, n whch DC sde common mode rpples would gve rse to ac sde currents and voltages of same frequency. 48

49 Chapter 4: Capactor Md Pont Topology (a) DC sde (One Pole shown) ud C dc d Fgure 4-3 (a): DC sde dfferental mode equvalent crcut (One pole) (b) AC sde (one phase) u ' ' ' L Fgure 4-3 (b): AC sde one phase dfferental mode Equvalent Crcut 4.3 PSCAD models for verfcaton of the analytcal Models A PSCAD model for capactor Md pont VS ncludng all the SPWM swtchng mechansms as well as the loads modeled as current sources n parallel wth ther mpedances s made. Fgure 4-4 PSCAD model of a capactor md pont VS wth loads 49

50 Chapter 4: Capactor Md Pont Topology n the PSCAD smulatons, the Converter components were szed to match the specfcatons of ths task, specfcally, the converter power ratng was kva, and the DC lnk voltage ( U dc ) was set to.86 kv, the modulaton ndex ma was.8.the system frequency was 5Hz. And the behavour of the system was analysed for a typcal case of a sngle phase load connected on the load sde, typcally 5 (A) rms or 8% of the rated converter out put current.e. 44 (A) on one phase wth the others set to zero Tme Doman Consderatons VS under balanced three phase loads n order to see the effect of unbalanced loads on the DC lnk capactor voltage, frst the PSCAD model was run for 5 seconds wth three balanced loads.e. current sources of 5 A each wth fundamental frequency order. The smulaton result was as shown n Fg 4-5 below..45 Up Un Vdc Tme Un (kv) Up & Un (kv) Vdc_half (kv) Fgure 4-5: PSCAD Tme doman smulaton of the VS wth balanced three phase loads of 5 (A) each. Fgure 4-5: shows the tme doman smulaton result just takng one cycle n steady state. The capactor value used for ths smulaton was mf. 5

51 Chapter 4: Capactor Md Pont Topology As can be seen from Fg.4-5, the upper capactor voltage and the lower capactor voltage u n reman dentcal, they are manly of the pure half DC lnk voltage, wth hgh frequency order rpples supermposed upon them, but ther magntude s nsgnfcant. Hence t can be seen that balanced three phase loads have no bg mpact on the DC lnk voltages rpples. Even though there are both common mode as well as dfferental mode currents flowng through the DC lnk capactors, they wll not result n large amounts of voltage dstortons due to ther hgh frequency order and small magntudes. VS wth sngle phase load only (3% mbalance) The above PSCAD model s once agan run for 5 seconds wth a sngle phase load ( 3% mbalance) of 5 (A) rms only on one phase and the rest two phases set to zero. The Capactor value used s stll mf.the result s as presented n Fgure 4-6 below. u p Up (kv) Un (kv) Up & Un (kv) Un Up Up Vdc Un Vdc_half (kv). Tme Fgure 4-6 (a): PSCAD Tme doman smulaton of the VS wth sngle phase load only of 5 (A). The DC lnk voltage rpple across each half capactor and the Total DC lnk voltage n steady state Udv (kv) Dc_voltage :half DC lnk Voltage common and dfferental mode Rpples Udv Udc.5 Ud (kv) Fgure 4-6 (b): Common mode and dfferental mode voltage rpples across each DC lnk capactor of the smulaton n Fg 4-6 (a) takng the last cycles n steady state 5

52 Chapter 4: Capactor Md Pont Topology n Fgure 4-6 (a), the DC lnk voltages across the upper capactor and the lower capactoru n have nstantaneous mbalances,.e. when one ncreases the other decreases and vce versa. But lookng at the fourth plot from top to down n the same fgure, the total DC lnk voltage does not have these mbalances, hence the two voltages are complementary and they cancel each other across the total DC lnk. u p un n Fgure 4-6 (b), the common mode DC lnk voltage rpple, u dv where, udv and u p + un udc the dfferental mode voltage rpple across each capactor, Δu d where Δ u d are plotted usng PSCAD blocks that can calculate these voltages accordng to the above expressons. Readng from the PSCAD tme scale, t can be noted that u dv s manly of fundamental frequency order whch s same as that of the load, wth hgh frequency order common mode voltage rpples supermposed upon t. But the domnant harmonc nu d s the second order harmonc, whch reveals the fact that un unbalanced load would result n low order dfferental mode voltage harmoncs across the DC lnk voltage. Furthermore a closer scrutny on Fgure 4-6 (b) shows that the common mode voltage rpple s much more pronounced than that of the dfferental mode rpple for ths converter topology. Typcally for the smulaton values used for Fgure 4-6,the peak value of the common mode rpple across each capactor s found to be.37 (kv) whle the dfferental mode rpple across each capactor has a peak value of.3 (kv),roughly wth a rato of :8,the common mode beng eght tmes bgger. The PSCAD smulatons were also tested for dfferent current mbalance levels (-3%) and the results turned out to be smlar to the result n Fgure 4-6, wth only magntude dfferences Frequency Spectrum consderatons n order to verfy the valdty of the tme doman equvalent crcuts mentoned prevously, the PSAD smulatons were studed usng Onlne Frequency Scanners (FFT) blocks n PSCAD as well as exportng the PSCAD output fles to TOP The Output Processor dong the frequency doman analyss takng the last cycle n steady state. The general targets here are the frequency spectrum of the DC lnk voltages, the nverter phase leg out put as well the lne to lne voltages, and the fndngs are as presented below. u p 5

53 Chapter 4: Capactor Md Pont Topology VS under balanced Three Phase Loads As was mentoned prevously, n all the smulatons the modulaton ndex m.8, u dc. 86 kv, Cdc mf, and load current s.5ka. a Fgure 4-7 (a): Lower DC lnk capactor Voltage rpple for balanced three phase load operaton n PSCAD Fgure 4-7 (b): Upper DC lnk capactor Voltage rpple for balanced three phase load operaton n PSCAD 53

54 Chapter 4: Capactor Md Pont Topology Fgure 4-7 (c): DC lnk dfferental mode Voltage rpple for balanced three phase load operaton n PSCAD Fgure 4-7 (d): DC lnk common mode Voltage rpple for balanced three phase load operaton n PSCAD Fgure 4-7(a) to (d) shows that generally there s hardly any DC lnk voltage rpples (very nsgnfcant magntudes) for balanced three phase loads operaton of capactor md pont VS topology. Fgures 4-7(a) and (b) show that the only sgnfcant voltage s the DC voltage alone on both capactors and the other harmoncs are very small. VS under sngle phase load connected on one phase only Here also same parameters are used for smulatons.e. the modulaton ndex ma.8, u dc. 86 kv, Cdc mf, and load current s.5ka. n PSCAD a sngle phase load of 5 A s connected only to one phase, and the results found are presented below. 54

55 Chapter 4: Capactor Md Pont Topology Fgure 4-8 (a): Lower DC lnk Voltage spectrum for a sngle phase load operaton n PSCAD Fgure 4-8 (b): Upper DC lnk Voltage spectrum for a sngle phase load operaton n PSCAD Fgure 4-8 (c): Full DC lnk Voltage spectrum for a sngle phase load operaton n PSCAD 55

56 Chapter 4: Capactor Md Pont Topology n Fgures 4-8(a) and (b), t s evdent that there s a harmonc component on the DC lnk voltage rpple at fundamental frequency as well as another smaller magntude second order voltage harmonc, due to the mbalance n the loads. The magntude of the common mode harmonc voltage rpple s same n both capactors. nfgure4-8 (c), the common mode voltage rpple dsappears and we are left wth only the dfferental mode rpple whch has magntude twce as was on each half DC lnk capactors. Sngle phase Load connected to one Phase wth a frequency twce the fundamental frequency n Fgure 4-9 below, the PSCAD model wth all the crcut values kept as before wth only the load current changed to be a sngle phase load of same magntude as before but wth just the frequency beng twce the fundamental for the purpose of studyng ts effect on the output voltage. Fgure 4-9 (a): Common mode DC lnk Voltage rpple spectrum for a sngle phase load at twce the fundamental frequency connected only to one phase n PSCAD Fgure 4-9 (b): Dfferental mode DC lnk Voltage rpple spectrum for a sngle phase load at twce the fundamental frequency connected only to one phase n PSCAD 56

57 Chapter 4: Capactor Md Pont Topology Fgure 4-9 (c): Phase Out put Voltage spectrum for a sngle phase load at twce the fundamental frequency connected only to one phase n PSCAD Fgure 4-9 (d): Lne to Lne out put Voltage spectrum for a sngle phase load at twce the fundamental frequency connected only to one phase n PSCAD For a sngle phase load at twce the fundamental frequency connected to only one phase, n Fgures 4-9(a) the common mode dc lnk voltage rpple has a domnatng low order harmonc of order two, whch agrees wth the fact that the common mode rpple s not modulated gven by Equaton 4- prevously,.e. u ( t) [ s( t) + s ( t) + s3 ( t) ] u d + udv For the common-mode voltage [] Equaton

58 Chapter 4: Capactor Md Pont Topology n Fgure 4-9(b), shows that the dfferental mode rpples contan an addtonal thrd order term due to the mbalance. n Fgures 4-9(c), the spectrum of the output voltage of one nverter leg after the flter s shown to have a second order domnant harmonc n addton to the fundamental. Ths concdes wth the explanaton gven n tme doman equvalent model dervaton, whch reveals the fact that the common mode voltage dfference between the two capactors s seen at the out put of a phase leg.e. u ( t) s ( t) u + u Dfferental-mode AC sde voltage, phase [] Equaton 4-9 d dv n Fgure 4-9(d), the Lne to lne voltage spectrum s shown. From ths plot one can see the fact that the common mode rpples are not seen on the lne to lne voltages snce they are present n both phases and they cancel. Typcally the common mode rpple, the second order n ths case s not seen on the lne to lne voltages. Furthermore, more smulaton observatons n PSCAD show that the out put phase voltages dffer slghtly from each other dependng on the level of load mbalance, and on whch phase the sngle phase s connected 4.4 Matlab Calculatons for verfcaton of the analytcal models 4.4. The Common mode Equvalent Schematc The above Explaned tme doman equvalent dagrams for common mode were solved n Mat lab and the results were found to match the smulated values from PSCAD. All calculatons were done n phasor form usng fft and fft functons of Matlab as t was easy to do forward and back ward transforms n tme doman and frequency doman. The load currents were transformed n to ther correspondng sequence components, usng the sequence transformaton matrces usng formulas n Appendx [8]. Then the matlab codes were run and the results were found to match the PSCAD smulatons. ( S + S + S ) U / 3 3 d U dv Fgure 4-: Combned Common Equvalent crcut n Frequency Doman Common mode voltage rpples found for a range of capactor values were compared wth PSCAD and they showed smlar values. Some Matlab plots are shown n fgure 4- below. 58

59 Chapter 4: Capactor Md Pont Topology 3 udv wt Fgure 4- (a): Matlab calculated Common mode half DC-lnk voltage rpple (Udv) for Cdc9mF 7 Common Mode peak to peak Voltage Rpple(V) DC Lnk Capactor Sze(mF) Fgure 4-(b): Varaton of DC lnk common mode voltage rpple for dfferent DC capactor values for a sngle phase load wth a current of 5 A rms connected. The half DC lnk voltage peak to peak common mode rpples were calculated n Matlab for a range of DC lnk capactor values usng the common mode equvalent crcut,and the results were as plotted n Fgure 4- (b). From the above plot one can observe that the common mode rpples become more or less constant after a capactor value of 3 mf. 59

60 Chapter 4: Capactor Md Pont Topology 4.4. The Dfferental mode Equvalent Schematc The fact that the dfferental mode rpple voltages are modulated, as was shown by Equatons 4-7 and 4-9,and also that the phase currents are n turn functons of these modulated dfferental mode rpple voltages makes the Analytcal calculaton of these dfferental mode voltages a bt cumbersome, and dffcult. u ( t) s ( t) u + u Dfferental-mode AC sde voltage, phase [] Equaton 4-9 u u d dv dc d + Δud Average half DC-Lnk Voltage Equaton 4-5 Typcally the analytcal calculaton can be shown n a block dagram below: S S d ΔU d SC U d U L,C Fgure 4-: Block dagram showng the procedures n calculatng the dfferental mode Voltage rpples From Equaton 4-, the dfferental mode current across each capactor s gven by: udc d ( s + s + s33 ), and also from Equaton 4-5 we have ud + Δud But, the dfferental mode rpple voltage Δ ud, s gven by Δud d dt C. And also from Equaton 4-9 we have u ( t) s ( t) ud + udv.all these equatons show the nterdependence of the AC and DC sde voltage rpples and as well as wth the phase currents. Hence as was explaned n secton 4-- of ths chapter, an equvalent dagram contanng both DC and AC sdes together s not feasble for ths case. Thus, due to the dffculty n fndng how many teratons we need to calculate the phase currents from the modulated dfferental mode rpples, as well as whether these values converge or not n Matlab calculatons, assumng a smplfyng assumpton s vtal. Hence, the DC lnk voltage s assumed to be constant for analytcal calculaton purposes and the dfferental mode voltage rpples were calculated just by ntegratng the dfferental mode rpple currents emanatng from pure swtched DC voltage and excludng the dfferental mode voltage rpples. As the man nterest here s to see the effect of unbalanced load on the DC lnk voltage, a sngle phase current source load of 5 (A) s used and the dfferental mode voltage rpples were calculated n the manner explaned n bref below. n order to calculate the phase currents of the converter output, we need frst to combne the symmetrcal and unsymmetrcal parts of the system. Thus we need to have three sequence equvalent dagrams as we have unsymmetrcal load connected to the symmetrcal converter sde parameters. The equvalent dagrams for these sequences are sketched n Fgure 4-3 below. dc 6

61 Chapter 4: Capactor Md Pont Topology + U + + L Fgure 4-3(a): Postve sequence ac sde equvalent Dagram U L Fgure 4-3(b): Negatve sequence ac sde equvalent Dagram U L dv U dc C Fgure 4-3(c): Zero sequence equvalent Dagram The sequence components of the loads are calculated from the phase Load currents as: 3 3 L L L L L L α α α α + 3 π α j e Also the symmetrcal components of the converter output voltages are also calculated n a smlar way, and the phase currents are calculated n the followng way: sh L sh L L Z Z Z U sh L sh L L Z Z Z U + + ) ( dc sh L sh L L C j Z Z Z U ω To fnd the converter out put phase currents, these symmetrcal components of the currents are transformed back to phase quanttes: + L L L 3 α α α α 3 π α j e 6

62 Chapter 4: Capactor Md Pont Topology Then usng Equaton 4-, d ( s + s + s33 ), thus now the Dfferental mode voltage rpple can be calculated as Δud d dt C,n Matlab. dc These equatons are wrtten n Matlab and the dfferental mode voltage rpple found s plotted n Fgure 4-4 below. The DC lnk capactor Value used for ths calculatons s mf. 6 4 Dfferental mode voltage rpple (V) wt Fgure4-4(a): Matlab calculated DC lnk Dfferental mode rpple voltage for a sngle phase load (across both capactors) For comparson purposes these values were checked for agreement wth PSCAD smulated values as shown n Fgure 4-4 (b) below. Udc Ud (kv) Fgure 4-4(b) PSCAD smulated half DC lnk voltage ncludng pure half DC lnk voltage and dfferental mode rpples The values of the peak to peak voltage dfferental mode rpples across the DC lnk capactors were very close n the two plots above. 6

63 Chapter 4: Capactor Md Pont Topology Total DC lnk Voltage rpples The Plots and dscussons so far reveal the fact that the common mode rpples are the domnatng ones for ths topology, and the dfferental dc lnk voltage rpples are very small. Both PSCAD smulatons and Matlab calculatons confrm that the combned effect of the DC lnk dfferental mode and common mode voltage rpples across the DC lnk capactors are manly domnated by the common mode rpples, whch are much more pronounced than that of dfferental mode rpples. One such good PSCAD smulaton example s shown n Fgure 4-5 below. Dc_voltage :half DC lnk Voltage common and dfferental mode Rpples Ud (kv) Udv (kv) Ud Udv Up (kv) Up Fgure 4-5(a): PSCAD smulaton of a sngle phase unbalanced load Dc lnk voltage rpples The mddle plot n fgure 4-5(a) shows the common mode rpple has a peak value of 37 (V), whle the upper plot shows the dfferental mode rpple across each capactor has a peak value of 3 (V). Consderng the total voltage across upper capactor, has a peak value of 4 (V). Ths shows that the DC lnk capactor rpple s manly domnated by the common mode rpple for ths topology. u p Up wt Un wt Vdctot wt Fgure 4-5 (b): Matlab smulatons of same system as n (a) above 63

64 Chapter 4: Capactor Md Pont Topology Fgure 4-5 (b) shows that the Upper and lower DC lnk capactors are domnated by the common mode rpple, whle the total DC lnk contans only the dfferental mode whch s much more less n magntude. 4.5 DC Lnk capactors szng For ths VS topology dealt n ths chapter as the common mode s the domnatng one, the dfferental mode rpples can be effectvely suppressed by the sze of capactor chosen to handle common mode voltage rpples across the DC lnk capactors. The Capactor szng s calculated as gven n Chapter 3 by: C dc _ Mn ZS 3 ωδu dc 3 ωu Equaton 3-3 dv 4.6 Tuned LC lnk and Component sze reducton consderatons The DC capactor sze requred to handle the common mode harmoncs can further be reduced by consderaton of tuned LC flters, whch are tuned for a partcular harmonc frequency, thus creatng a low mpedance path for that partcular frequency and reducng the voltage stress on the DC lnk capactor. As was shown n Fgure 4-6, the smaller sze flter components.e. Ch and Lh, whch are th partcularly tuned for the h harmonc frequency of the common mode harmonc current, would help mnmze the sze of. C dc dh C h dh L h C h Fgure 4-6: Tuned LC lnk consderaton n DC Lnk Capactor szng 64

65 Chapter 5. Topology wth Delta-Wye Transformer Chapter 5. Topology wth Delta-Wye Transformer Fgure 5- Three-phase voltage source converter wth Δ Υ Transformer 5. Three-phase Transformers and ther effects on sequence components The effects of three phase delta-wye transformers on handlng sequence components resultng from unbalanced loads connected to the wye sde of would be addressed below. n order to see the effect of a transformer on the sequence components let us consder a general three phase wye-delta three phase transformer connected to a sngle phase load. a A + c ac + c cb + a + b ba + N C + B b Fgure 5-: Three Phase Δ Υ Transformer connected to sngle phase load Fgure 5- shows a standard 3 phase shft delta-wye transformer feedng a sngle phase load. Such an unbalanced load on the wye sde of the transformer can be decomposed nto ts sequence components, and to see the transformer effect on them later on the delta sde sequence components would be analysed. When the wye sde currents are balanced, as each of the delta secondary currents s related to ts correspondng prmary sde current by the ampere turns rato, the sum of the 65

66 Chapter 5. Topology wth Delta-Wye Transformer three delta currents s forced to become zero, hence there would be no crculatng currents between the delta wndngs. But there would be crculatng delta wndng currents when the wye sde currents are unbalanced and when ther sum s not zero on the neutral wre connected. The basc deal transformer current equatons as a functon of the ampere turns rato, can be wrtten as follows: a T C B A T T T ac cb ba a a a Equaton 5- Where the currents,, are the delta sde wndng currents and,, are the wye sde lne currents. And the ampere turns rato, s gven by ba cb ac A B C a T C ac B cb A ba T a Lookng at the relaton between the delta sde wndng currents and lne currents we have, ba cb cb ac ac ba b c a Equaton 5- Ths can be wrtten also as: ac cb ba c b a Equaton 5-3 Usng Equatons 5- and 5-3, we can drectly relate the wye sde lne currents wth the Delta sde lne currents as follows: C B A T T T T T T c b a a a a a a a Equaton 5-4 The crcut n Fgure 5- was smulated n PSCAD and Matlab plots were also made usng the above equatons for an deal transformer connected to a sngle phase load (A pure snusodal current source of 3 [A] rms s connected to phase c as shown n Fgure 5- above) The ampere turns rato s assumed to be.the results are plotted only consderng the effects for one cycle n Fgures below: The transformaton from phase quanttes to sequence components and vce versa were done usng the sequence transformaton matrces gven n Appendx [8]. 66

67 Chapter 5. Topology wth Delta-Wye Transformer Delt-pos-seq-Current Delt-Neg-seq-Current Delt-Zero-seq-Current wt wt wt Y-pos-seq-Current Y-neg-seq-Current Y-Zero-seq-Current wt wt wt Fgure 5-3: Delta and Wye sde current Sequence components for a sngle phase load (Matlab) D-P ostve-seq-fft D-Negatve-seq-FFT D-Zero-seq-FFT Harmonc Orders Harmonc Orders Harmonc Orders Y -P ostve-seq-fft Y -Negatve-seq-FFT Y -Zero-seq-FFT Harmonc Orders Harmonc Orders Harmonc Orders Fgure 5-4: FFT of Fgure 5-3 above (Matlab) 67

68 Chapter 5. Topology wth Delta-Wye Transformer 5 A-wye wt a-delta wt B-wye b-delta wt wt 5 5 C-wye wt c-delta wt Fgure 5-5: Tme doman plots of Delta and Wye sde phase currents for unbalanced load at wye sde The above explanatons and Fgures 5-3 to 5-5 show that for a zero sequence currents on the wye sde of a delta-wye transformer resultng from unbalanced loads, the transformer acts as an open crcut. Whle t lets the symmetrcal components pass through, even though ther magntudes become a lttle bt more pronounced on the delta sde than what they were n the wye sde. Hence the same concept can be appled for a VS connected to a delta-wye transformer. The zero sequence from the unbalanced load sde would not affect the converter, and hence no zero sequence effects would found on the DC lnk capactors, as would also be dealt further n the comng sectons of ths chapter. On the other hand, the other symmetrc components, the negatve and the postve sequences would affect the converter DC lnk capactors operaton, and hence they should be consdered and would be dealt n the comng sectons of ths chapter. 68

69 Chapter 5. Topology wth Delta-Wye Transformer 5. Topology wth Delta-Wye Transformer Fgure 5-4: Three-phase voltage source converter wth Δ Υ Transformer connected to three phase loads (Modelled as current sources n parallel wth mpedances) 5.3 Tme Doman Analyss n ths chapter the same defntons used n Chapter-4 of ths report for the average and mbalance components of the DC lnk voltage as well as related defntons are adopted. Usng swtchng functon S (t), and assumng a hgh nput mpedance from the DC sde,.e. neglectng the DC sde mpedance n ths analyss, we can further wrte down equatons currents n the upper and lower DC rals of the nverter. n Fgure 5-4 above, there s no neutral wre connected to the md pont of the capactors or to earth, hence there s no return path for the common mode current, and thus the sum of three phase currents must sum up to zero. + + [5] 3 Hence, p n Equaton 5-5 [5] Equaton 5-8 Usng Equatons 4-5 and 4-6, d ( p n ) n p ( + ) Equaton 5-9 d p n Equaton 5- Equaton 5- confrms that, there s no common mode current flowng across the DC capactors n ths case, as was n the case of splt capactor md pont topology. Hence, there would be no voltage mbalance because of common mode current, thus: u dp u dn [6] Equaton 5- And u u p u n dv [7] 69 Equaton 5-

70 Chapter 5. Topology wth Delta-Wye Transformer From Equaton 5-7and Equaton 5-8 n App. [5], t can be seen that there s only dfferental mode current flowng across the DC lnk capactors, and thus the voltage rpples n the two capactors are related to these currents only. Snce same dfferental mode current flows across the two capactors, t wll cause same voltage rpple across both capactors and hence the voltages across these capactors reman balanced, but wth the DC voltage supermposed wth dfferental mode voltage rpples. Usng the so far descrbed equatons, now t s possble to derve an equvalent dagram for common mode as well for dfferental mode for ths topology of the converter. 5.. Common Mode/Zero sequence equvalent Crcut A Zero sequence equvalent model would be derved n the followng secton, usng same defntons of symbols as n chapter 4. Based on Equatons 5-5 to 5-, a common-mode (zero sequence harmoncs) equvalent schematc of the system can be drawn as shown n Fgure 5-5. Ths was made frstly by dervng the crcuts from the above equatons separately for AC and DC sdes and by thnkng whether there would be a lnk to jon them or not. (a) DC sde As there s no return path for the common mode current back to the md pont of the capactors, there would be no common-mode current crculatng across the nverter crcuts even though there s a common-mode voltage ether from the PWM process, or from the common-mode reference voltage njected, or from the unbalanced loads. Accordng to the arguments above, as there would be no common-mode current flowng across the DC lnk capactors, the mbalance voltage components across the DC-lnk capactors would be zero. Hence there would be no contrbuton from the DC sde for the common-mode equvalent crcut, and therefore t can be dsregarded for the common mode. (b) AC sde (one phase) As there s no return path for the common mode current n ths topology, the common mode voltages from the PWM process or from njected common mode source, wll not result n any common mode current crculatng. n addton, the common mode currents from the load sde are decoupled by the deltawye transformer, hence no common mode current passes across the nverter AC sde; therefore we can neglect the nverter AC sde contrbuton for our common mode equvalent dagram. The only part sgnfcant would be the common mode component of the load as well as the leakage mpedance of the transformer, thus the sngle phase equvalent crcut, modellng the loads as current sources n parallel wth ther mpedances, would look lke the followng: 7

71 Chapter 5. Topology wth Delta-Wye Transformer Fgure 5-5 (a): Common Mode per Phase Equvalent Crcut n Fgure 5-5, L refers to the common mode component of the load, and LT s the leakage reactance of the transformer. Thus our fnal Equvalent Crcut would be as shown n Fg 5-5 (b) below. (b) Fnal Equvalent Crcut Fgure 5-5 (b): Common Mode Equvalent Crcut 5.. Dfferental mode/negatve and postve sequence equvalent crcuts From Equaton 4-7 above, the average half DC-Lnk Voltage, u d,whch s gven by u p + un ud,contans dfferental mode rpple voltages due to the dfferental mode rpple current that flows across each capactor. Hence, s a combnaton of the pure u dc half DC lnk voltage ( ) and the dfferental mode rpple voltage across each DC Lnk Capactor. The dfferental mode rpple voltage Δ ud, s gven by Δud d dt C. dc Hence, u u dc d + Δud Average half DC-Lnk Voltage Equaton 4-5 u d From Equaton 4-9, t can be noted that ths dfferental mode rpple s modulated, and ths shows that there s a lnk between AC and DC sdes. But due to the non lnearty of the AC and DC sde dfferental mode rpple currents because of the swtchng of the dfferental mode rpple voltages, an equvalent crcut jonng both the AC and DC sdes s not feasble. Because due to the swtchng, AC sde harmoncs of dfferent orders from that of the DC sde voltage rpple would arse, and the 7

72 Chapter 5. Topology wth Delta-Wye Transformer relatonshp s not lnear. Hence ther behavour must be explaned wth the AC and DC sdes treated separately. The correspondng crcuts for dfferental mode (postve and negatve sequence harmoncs) are shown n Fgure 5-6 below. n ths case as the transformer used has a property of blockng common mode and passng the other symmetrcal components, the transformer leakage reactance would be ncluded n the equvalent crcuts. (a) DC sde (both poles) n ths case as there would be a dfferental mode current flowng across the DC sde, we need to consder the DC sde. Snce the dfferental current flows across the two capactors, the capactors can be treated as beng connected n seres, and, results n a C d equvalent n the equvalent crcut. C u dc d d Fgure 5-6 (a): DC sde dfferental mode equvalent Crcut (Poles treated as beng n seres) (b) AC sde For the AC sde from Equaton 4-9, and Equaton 4-5, we know u u t) s u + u ( Equaton 4-9 u d dv dc d + Δud Average half DC-Lnk Voltage Equaton 4-5 Here u dv, thus we can see how the dfferental mode rpple Δud s swtched and comes n to pcture on the AC sde. Here we need to consder the transformer leakage reactance also n our model. U L Z Td Z shd L Fgure 5-6 (b): Dfferental mode Equvalent Crcut for the AC sde (one phase) 7

73 Chapter 5. Topology wth Delta-Wye Transformer 5. PSCAD models for verfcaton of the analytcal Models Fgure 5-7: Model of three phase VS wth delta wye Transformer n PSCAD The Transformer n the PSCAD smulatons s used just for the purpose of checkng ts effect on sequence components, hence the turns rato used s one for both PSCAD smulatons as well as for the Matlab calculatons to be presented followng. n the PSCAD smulatons, the Converter components were made to be same as n Chapter 4. And the behavour of the system was analysed for a typcal case of a sngle phase load connected on the load sde, typcally5 ka (rms) on one phase wth the others set to zero. An deal transformer of equal turns rato s used just to see the transformer effect n the smulatons. Operaton under Balanced three phase loads The PSCAD smulatons were done for ma.8, Udc 86 V, Cdc uf, load s.5ka. Fgure 5-8 (a): Common mode DC lnk voltage rpple for balanced three phase loads (PSCAD). 73

74 Chapter 5. Topology wth Delta-Wye Transformer Fgure 5-8 (b): Dfferental mode DC lnk voltage rpple for balanced three phase loads (PSCAD). Fgures 5-8(a) & (b) show that both the common mode and dfferental mode DC lnk voltage rpples are neglgble for a balanced three phase operaton, whch agrees wth the tme doman explanatons made earler. Operaton under Sngle phase load only on one phase A sngle phase load s connected n PSCAD only on one phase, and the smulaton result found s as follows: Fgure 5-9 (a): Common mode half DC lnk voltage rpple for sngle phase load operaton (PSCAD) Fgure 5-9 (a) shows that the common mode voltage rpples are hardly present on the DC lnk capactors. 74

75 Chapter 5. Topology wth Delta-Wye Transformer Fgure 5-9 (b): Dfferental mode half DC lnk voltage rpple for sngle phase load operaton (PSCAD) Fgure 5-9 (b) shows that the domnant dfferental mode DC lnk voltage rpple s of fundamental order for a sngle phase load wth a fundamental order of frequency connected. The dfferental mode voltage rpple across each half capactor has an rms value of 33 V from the plot. Fgure 5-9 (c): Lower DC lnk capactor voltage rpple for sngle phase load operaton (PSCAD) Fgure 5-9 (d): Upper DC lnk capactor voltage rpple for sngle phase load operaton (PSCAD) 75

76 Chapter 5. Topology wth Delta-Wye Transformer Fgure 5-9 (e): Full DC lnk voltage rpple for sngle phase load operaton (PSCAD) Fgure 5-9 (c)&(d) show that the domnant dfferental mode dc lnk voltage rpple s of fundamental order on both capactors, wth an rms value of 33 V, whle n Fgure5(e), the full dc lnk s seen to have domnant dfferental mode rpple voltage at fundamental frequency wth twce the magntude on each capactors,.e. 66 V. Operaton wth Sngle phase load at twce the fundamental frequency n order to study the effect a sngle phase load at twce the fundamental frequency connected on only one phase, the same PSCAD model was run wth makng only frequency change as mentoned. Fgure 5- (a): Dfferental mode DC lnk voltage rpple for sngle phase load at twce fundamental frequency operaton (PSCAD) 76

77 Chapter 5. Topology wth Delta-Wye Transformer Fgure 5- (b): Output phase voltage spectrum for sngle phase load at twce fundamental frequency operaton (PSCAD) n fgure 5- (a), the dfferental mode rpple voltage on dc lnk capactors s seen to have a thrd harmonc due to the modulaton of the dfferental mode voltages. And n fgure 5-(b), the second harmonc s seen at the output termnals as a common mode voltage. 5.3 Matlab Calculatons of the PSCAD Smulatons Due to the ntrcaces mposed up on the Matlab analytcal calculatons due to the swtched dfferental mode rpples, as was explaned n secton 4.5. of chapter, a perfect match was not found between the PSCAD smulated values and the Matlab calculated values, but some what a closer fgure s acheved assumng a stff DC lnk voltage at frst and gnorng the fact that dfferental mode voltages are modulated. The Matlab calculatons were performed by frst transformng the wye sde unbalanced currents usng the current Transformaton equatons gven n secton 5. of ths report.e. usng equatons 5- to 5-4..e. ba cb ac at at at A B C Equaton 5- Where the currents,, are the delta sde wndng currents and,, are the ba cb ac wye sde lne currents. And the ampere turns rato, s gven by a T A B C a T ba A cb B ac C 77

78 Chapter 5. Topology wth Delta-Wye Transformer Lookng at the relaton between the delta sde wndng currents and lne currents we have, ba cb cb ac ac ba b c a Equaton 5- Ths can be wrtten also as: ac cb ba c b a Equaton 5-3 Usng Equatons 5- and 5-3, we can drectly relate the wye sde lne currents wth the Delta sde lne currents as follows: C B A T T T T T T c b a a a a a a a Equaton 5-4 The wye sde currents are once agan decomposed n to ther respectve sequence components, as was explaned n secton 4.5. of ths report and the same sequence equvalent crcuts presented n ths same secton are used. As a check up n Matlab, the prevous PSCAD smulaton was repeated n Matlab,.e. wth CdcmF and DC Lnk Voltage 86 V, ma.8. The spectrum of the Dc lnk dfferental mode voltage s presented below: nharm Dfferental mode voltage rpple (V) Fgure 5- (a): Dfferental mode DC lnk voltage spectrum for sngle phase load at twce fundamental frequency operaton (Matlab) 78

79 Chapter 5. Topology wth Delta-Wye Transformer. Common mode Voltage rpple spectrum (V) nharm Fgure 5- (b): Common mode half DC lnk voltage spectrum for sngle phase load at twce fundamental frequency operaton (Matlab) Comparng Fgure 5-9(a) and 5-9(b) wth Fgure 5- (a) & (b), we can see a closer match between the Matlab calculated and the PSCAD smulated values. Typcally for the same crcut values and DC capactor sze, for a sngle phase load mbalance, the dfferental mode rpple voltage across half the DC lnk capactors was found to be around 33 V n PSCAD, and around V n Matlab calculated values. 5.4 DC- Lnk Capactors Szng As The Only DC Lnk rpple voltages we have here are of dfferental mode types, the szng of the capactors would be as was explaned n Chapter three, whch uses the followng formula. C m 3 _ peak a dc Mn NS Equaton 3-3 _ : 8 wδudc 5.5 Non snusodal reference njecton consderatons njecton of thrd harmonc wll ncrease the modulaton ndex range to.5 by reducng the peak of the reference voltages. f the modulaton ndex can be ncreased than what was under normal SPWM operaton, t would mean smaller DC lnk voltage requred when the thrd harmonc s njected n order to get same out put voltage as before. n order to compare ths effect, the output voltage of the nverter wth a modulaton ndex.8 as before and wth a DC lnk capactor value of mf was compared wth same crcut smulated wth the DC lnk voltage reduced to 583 V, whch corresponds to a modulaton ndex of. n PSCAD. The results are summarzed below. 79

80 Chapter 5. Topology wth Delta-Wye Transformer Fgure 5- (a): Output phase voltage spectrum for balanced 3 phase loads connected to the VS wth delta wye Transformer topology, ma.8, Vdc86 V (n PSCAD) n Fgure 5-(b) below, the output phase voltage was measured wth reference to the neutral pont of the flter capactors on the delta sde, hence the reference s a common mode voltage, and thus the out put voltage does not have common mode rpples. Fgure 5- (b): Output phase voltage spectrum for balanced 3 phase loads connected to the VS wth delta wye Transformer topology wth thrd harmonc reference njected, ma. and Vdc583 V (n PSCAD) Fgures 5-(a) & (b) show that the njecton of thrd harmonc can reduce the sze of the DC lnk voltage needed n order to get the same out put phase voltage. Fgure 5- (c): Full DC Lnk voltage spectrum for balanced 3 phase loads connected to the VS wth delta wye Transformer topology wth thrd harmonc reference njected, ma. and Vdc583 V (n PSCAD) 8

81 Chapter 5. Topology wth Delta-Wye Transformer n Fgure 5-(c) t can be noted that for a balanced three phase operaton, the njecton of the thrd harmonc does not mpose sgnfcant harmoncs on the DC lnk voltage. Fgure 5- (d): Lne Voltage spectrum for balanced 3 phase loads connected to the VS wth delta wye Transformer topology wth thrd harmonc reference njected, ma. and Vdc583 V (n PSCAD) Fgure 5-(d) shows the fact that these common mode voltage rpples cancel each other n the lne to lne voltages and are not present. 5.6 Tuned LC lnk and Component sze reducton consderatons The DC capactor sze requred to handle the dfferental mode harmoncs can further be reduced by consderaton of tuned LC flters, whch are tuned for a specfc harmonc frequency, thus creatng a low mpedance path for that partcular frequency and reducng the voltage stress on the DC lnk capactors. p p d+ d C h u p C dc L VAn dh o v v v3 3 VBn VCn L h u n C dc C L L L3 n n d - d n N Fgure 5-: Tuned LC lnk consderaton n DC Lnk Capactor szng As was shown n Fgure 5-, the smaller sze flter components.e. C and L, whch are th partcularly tuned for the h harmonc frequency of the dfferental mode harmonc current, would help mnmze the sze of C. dh dc h h 8

82 Chapter 6. Four Legged nverter Topology Chapter 6: Four Legged nverter Topology 6. Four Legged nverter Topology Fgure 6-: Three-phase four legged voltage source nverter As shown n the Fgure above, a four legged VS has the fourth leg servng as a neutral connecton pont. 6. Tme Doman Analyss for Four leg VS n order to have unformty of the tme doman analyses so far dealt wth for the other topologes, the dc lnk voltage s assumed to have a vrtual md pont o, whch s floatng for ths topology also. All the phase leg voltages are referred to ths fcttous md pont and the potental of ths vrtual md pont n turn can be referred to the ground as s depcted by n Fgure 6- below. u og Fgure 6-: Three phase four wre VS connected to three phase loads modelled as current sources n parallel wth ther mpedances. n the tme doman analyss of ths converter topology, the DC sde mpedances are dsregarded assumng the converter s fed from a purely rectfed stff DC grd. Here from Equaton 6-6 of appendx, [9] : 8

83 Chapter 6. Four Legged nverter Topology Equaton 6-6 p n And from Equaton 6-8, we have d ( p n ) { s + s + s3 3 + s N N } Equaton 6-8 And d ( p + n ) Ground /common mode DC sde Equaton 6-9 Hence from Equatons 6-8 and 6-9 we can see that there s no common-mode current flowng across the DC lnk capactors, but only pole mode current. Ths shows that there s only dfferental mode voltage rpples across the DC lnk capactor. Note that the neutral current n the fourth leg can be controlled by controllng the swtchng sequence of the legs. For ths topology, Zero sequence njecton would ental hgher modulaton ndex and better utlzaton of the DC lnk voltage. Comng to the Voltages, From Equaton 6-, there s no common mode voltage rpple across the DC lnk capactor, u ( t) s ( t) u + u s ( t) u because d dv d u Equaton 6- u p + un But, ud,contans dfferental mode rpple voltages whch due to the dfferental mode rpple current that flows across each capactor. Hence, u d s a combnaton of the pure half DC lnk voltage ( ) and the dfferental mode rpple voltage across each DC Lnk Capactor. The dfferental mode rpple voltage by Δu d, s gven by Δud d dt C. u u dc dc d + Δud Average half DC-Lnk Voltage Equaton 4-5 From Equaton 4-9, t can be noted that ths dfferental mode rpple s modulated, and ths shows that there s a lnk between AC and DC sdes. An Equvalent schematc of the system stll neglectng the DC sde mpedance can be sketched as follows: 6.. Common mode/zero sequence equvalent crcut Defnng other terms n a smlar fashon as was used for the DC lnk mdpont topology, for the sake of convenence, the Zero sequence equvalent model would be derved n the followng secton: u ( u + u + u3 ) 3 Common-mode AC sde Equaton 4- Usng Equaton 6- and Equaton 4- u ( t) [ s( t) + s ( t) + s3 ( t) ] ud Common-mode AC sde Equaton 6-3 Based on ths assumpton and the equatons above, a common-mode (zero sequence harmoncs) equvalent schematc of the system can be drawn as shown n Fgure 6-3(c). 83 dv u dc

84 Chapter 6. Four Legged nverter Topology Ths s made frstly by dervng the crcuts from the above equatons separately for AC and DC sdes and by thnkng whether there would be a lnk to jon them or not. (a) DC sde (one phase) n ths case we don t have any zero sequence current flowng across the DC sde we would have no contrbuton for zero sequence equvalent models from the DC sde. Therefore, the DC sde can be neglected for zero sequence. (b) AC sde (one phase) U /3(s +s +s 3 )u d L u N s N u d L N N /3 Z shz L /3 Fgure 6-3(a): Common mode equvalent crcut (One phase) (c) Fnal Equvalent Crcut ( s + s s ) u / 3 u + 3 d u N s N u d Fgure 6-3 (b): Fnal Common Mode Equvalent Crcut n Fgure 6-3 above, we can see that f ether by controllng the swtchng functon, by zero sequence njecton or by other method u N s made to cancel u, there would be no zero sequence current crculatng across the nverter. 6.. Dfferental mode/negatve and postve sequence equvalent crcuts Snce a load sde mbalance at the fundamental frequency would cause low order voltage rpples on the DC-lnk capactors, the dfferental mode rpples are seen at the DC sde and seen at the AC sde also but they are modulated. Due to smlar reasonng as was made n Chapter 3, because of the non lnearty we can not have a sngle equvalent crcut for both AC and DC sdes, thus we need to separate them for ths analyss. The correspondng crcuts for dfferental mode (postve and negatve sequence harmoncs) are shown n Fgure 6-4 below. 84

85 Chapter 6. Four Legged nverter Topology (a) DC sde (both poles) n ths case as there would be a dfferental mode current flowng across the DC sde, we need to consder the DC sde. The dfferental current flows across the DC Lnk C capactor, n the equvalent crcut. d C u dc d d Fgure 6-4 (a): DC sde dfferental mode equvalent Crcut (b) AC sde For the AC sde from Equaton 4-9, and Equaton 4-5, we know u u t) s u + u ( Equaton 4-9 u d dv dc d + Δud Average half DC-Lnk Voltage Equaton 4-5 Here udv, thus we can see how the dfferental mode rpple Δud s swtched and comes n to pcture on the AC sde, thus t needs to be consdered on the AC sde. For the AC sde as all the other harmonc currents cancel out n the neutral pont whch s the fourth leg, only zero sequence current flows across the neutral. Hence the fourth leg would not have any contrbuton to the dfferental mode crcut, hence t can be gnored. So the crcut would be drawn as follows: u ' ' Fgure 6-4 (b): Dfferental mode Equvalent Crcut for the AC sde (one phase) 85

86 Chapter 6. Four Legged nverter Topology 6.3 PSCAD models for verfcaton of the analytcal Models Fgure 6-5: Model of the Four legged VS n PSCAD n the PSCAD smulatons, the Converter components matchng the specfcatons of ths task were chosen, specfcally, the converter power ratng was kva, and the DC lnk voltage was set to.86 kva, the modulaton ndex m a was.8.the system frequency was 5Hz.The DC lnk capactors used s two mf capactors n Seres. n these smulatons the normal three legs of the nverter were swtched wth snusodal reference as for a normal SPWM modulaton, but the fourth leg reference s made to be DC or zero volt, as the am s just to swtch the legs and no need for ts out put voltage for the purpose at hand now. Balanced three phase loads operaton Fgure 6-6 (a): DC Lnk Voltage rpple for balanced three phase loads of the Four legged VS n PSCAD Fgure 6-6 (a) shows the fact that a balanced three phase loads would not have sgnfcant voltage rpples across the DC lnk capactor. n Fgure 6-6 (b) below also, t can be notced that under balanced load operaton condton of the four legged VS, the only domnant harmoncs on the neutral wre (fourth leg) are the hgh order frequency components around nteger multples of the swtchng frequency. 86

87 Chapter 6. Four Legged nverter Topology Fgure 6-6 (b): Neutral wre Voltage spectrum for balanced three phase loads operaton of the Four legged VS n PSCAD Fgure 6-6 (c): Output Voltage spectrum for balanced three phase loads operaton of the Four legged VS n PSCAD Fgure 6-6 (d): Lne to Lne Output Voltage spectrum for balanced three phase loads operaton of the four legged VS n PSCAD Fgures 6-6(c)and (d) show the fact that both the lne to lne or phase voltages do not have sgnfcant low order voltage harmoncs for balanced three phase operaton of the four legged VS. 87

88 Chapter 6. Four Legged nverter Topology Unbalanced Load Condtons Usng same methods as was used n earler chapters, here also we consder manly the effect of large mbalances on the DC lnk capactors, and hence emphass s gven to the maxmum mbalance case,.e. a sngle phase load connected only on one phase. n the subsequent sectons the abltes of the four legged nverter for handlng such mbalances shall be dealt n bref usng results from PSCAD smulatons. A sngle phase load of 5 (A) rms was connected only on one phase n PSCAD and the others set to zero, and the smulaton results are as follows: Fgure 6-7 (a): Full DC lnk voltage spectrum for a sngle phase load only operatng condton of a four legged VS (PSCAD) Fgure 6-7 (b): neutral wre Voltage spectrum for sngle phase load connected only on one phase operaton of the four legged VS n PSCAD 88

89 Chapter 6. Four Legged nverter Topology Fgure 6-7 (c): Lne to Lne voltage spectrum for sngle phase load connected only on one phase operaton of the four legged VS n PSCAD n Fgure 6-7 (a), the domnant dfferental mode rpple n the full DC lnk voltage has an RMS value of 58 (V) at a second frequency order. The common mode rpple at the fundamental s nsgnfcant and has a value of 3.5 (V). Fgure 6-7 (b) shows how the neutral wre voltage spectrum contans low order common mode rpple at the fundamental frequency due to the mbalance and hgh frequency order voltage harmoncs due to the SPWM swtchng of the nverter legs. n Fgure 6-7 (c), t can be noted that the common mode harmoncs cancel out n the lne to lne voltages. Fgure 6-7 (d): DC Lnk voltage spectrum for sngle phase load connected only on one phase operaton of the four legged VS n PSCAD 89

90 Chapter 6. Four Legged nverter Topology Fgure 6-7 (e): Output phase voltage (c ) spectrum for sngle phase load connected only on phase (a) operaton of the four legged VS n PSCAD Fgure 6-7 (d) shows the presence of second harmonc on the DC lnk voltage spectrum due to the mbalance, whch was explaned n earler chapters. n Fgure 6-7(e) also we can notce the presence of low order dfferental mode harmoncs due to the mbalance. Thrd harmonc reference njecton The above mentoned PSCAD model was run wth addton of thrd harmonc njecton blocks, wth the thrd harmonc beng /6 of the fundamental magntude, whch results n a maxmum modulaton ndex of.5. But here the modulaton ndex and the DC lnk voltage are left same n order to see just the effect of the thrd harmonc njecton. These smulatons were done under balanced three phase loads of 5(A) rms each. The reference voltages for the three phases are fundamental plus thrd harmonc, whle for the fourth leg; the reference s only the thrd harmonc voltage. Fgure 6-8 (a): Output phase voltage spectrum for balanced three phase loads and wth optmum thrd harmonc reference njecton operaton of the four legged VS n PSCAD 9

91 Chapter 6. Four Legged nverter Topology Fgure 6-8 (b): Dc Lnk voltage spectrum for balanced three phase loads and wth optmum thrd harmonc reference njecton operaton of the four legged VS n PSCAD Fgure 6-8 (c): Neutral Lne voltage spectrum for balanced three phase loads and wth optmum thrd harmonc reference njecton operaton of the four legged VS n PSCAD Fgure 6-8 (d): Lne to lne voltage spectrum for balanced three phase loads and wth optmum thrd harmonc reference njecton operaton of the four legged VS n PSCAD n Fgure 6-8 (a) above, the njected thrd harmonc s not seen on the output phase voltage as the reference.e. the fourth leg also has a thrd harmonc njected. Fgure 6-8 (b) shows that the njected common mode voltage wll not appear n the DC lnk voltage spectrum. n Fgures 6-8(c) & (d) respectvely, t can be noted that the 9

92 Chapter 6. Four Legged nverter Topology neutral wre contans only hgh order common mode rpples, and also the common mode harmoncs cancel out n the lne to lne voltages. 6.4 DC- Lnk Capactors Szng As the Only DC Lnk rpple voltages we have here are of dfferental mode types, the szng of the capactors would be determned manly by the negatve sequence low order rpples present on the DC lnk voltage spectrum as a result of the mbalance, and thus the capactor szng would be done as pertnent to the dscussons made n Chapter three, whch uses the followng formula. C m 3 _ peak a dc Mn NS Equaton 3-3 _ : 8 wδudc 6.5 Tuned LC lnk and Component sze reducton consderatons The DC capactor sze requred to handle the dfferental mode harmoncs can further be reduced by consderaton of tuned LC flters, whch are tuned for a partcular harmonc frequency, thus creatng a low mpedance path for that partcular frequency and reducng the stress on the DC lnk capactor. C h dh L h Fgure 6-9: Tuned LC lnk consderaton n DC Lnk Capactor szng As was shown n Fgure 6-9, the smaller sze flter components.e. C and L, whch are th partcularly tuned for the h harmonc frequency of the dfferental mode harmonc current, would help mnmze the sze of C. dh dc h h 9

93 Chapter 7. General Comparsons and Specfc Component Calculatons Chapter 7: General Comparsons and Specfc Component calculatons of the topologes 7. General Comparsons of the Topologes 7.. Comparson based on the level of DC lnk voltage harmoncs present n the prevous chapters of the report the level of DC lnk voltage rpples across the DC lnk capactors were studed for dfferent cases. n order to summarze now, all the topologes are compared based on the DC lnk voltage harmonc level, for the same modulaton ndex, load current mbalance level, DC lnk voltage level as well as DC lnk capactor sze. The results found from PSCAD smulatons are tabulated below: Topology Splt Capactor Md Pont Delta-Wye Transformer topology The RMS magntude of the domnant common mode voltage harmonc across half DC Lnk voltage (V) The RMS magntude of the domnant dfferental mode voltage harmonc across half DC Lnk voltage (V) References Fgure 4-8(a) & Fgure 4-8 (b) Fgure 5-4(b) & Fgure 5-9 (a) Four legged VS.75 9 Fgure 6-7(a) Table 7-: Comparson of the harmonc levels on the DC lnk voltage of the dfferent topologes Note n table 7- that the values used for the smulaton are: the modulaton ndex of.8, Full DC lnk voltage of 86 (V), the current mbalance level s 3 [%] beng a sngle phase load current wth an RMS value of 5 (A), and the value of the half DC lnk capactor used s mf. From ths table we can see that the dfferental mode rpples are slghtly hgher n magntude for the case of Delta-wye transformer topology and lowest for four legged VS. 7.. Comparson based on the DC-Lnk Capactor Sze 93

94 Chapter 7. General Comparsons and Specfc Component Calculatons Lookng at the PSCAD and Matlab plots presented so far t s clear that the common mode rpple s much more pronounced compared to the dfferental mode, gven same capactor sze,dc lnk voltage and same other crcut parameters n all the topologes. Thus the capactor md pont topology needs a much larger capactor value to suppress the much larger common mode rpples. The PSCAD smulatons so far presented show that, n terms of the dfferental mode rpple magntudes, there s no bg dfference between the topology wth delta wye transformer and the one wth fourth leg. n order to fully understand these dfferences, there must be a model effectvely explanng the behavor of these models Comparson based on the Flter components requred For such a hgh swtchng frequency the flter components needed for the dfferent topologes do not dffer much sgnfcantly, hence an assumpton was made that the same flter components can be used n all the topologes Comparson based on Thrd Harmonc njecton consderatons Generally consderng the fact that addton of thrd harmonc reference, wll ncrease the maxmum modulaton ndex range and mght mean reducton n the DC lnk voltage needed for a certan out put voltage of the converter, the Four Leg nverter topology s the best due to the addtonal fourth leg to control neutral wre voltage. The Topology wth the delta wye transformer has a possblty of thrd harmonc reference njecton, even though the DC Lnk s grounded, t wll not result n any common mode current that would crculate back causng DC sde voltage mbalances and AC sde common mode voltage dstortons. Thus t has same DC lnk voltage reducton capabltes as the fourth legged topology, but wth out control possblty of the fourth wre voltage as n the case of four legged nverter. The thrd harmonc njecton s not feasble for the capactor md pont topology as the added common mode voltage would result n a common mode current whch wll n turn be cause of DC sde voltage mbalances. 7. Specfc Component calculatons and fnal comparsons 7.. Specfc Norms/standards used The Standards adopted n these calculatons are manly EEE 547, whch s EEEE standard for nterconnectng dstrbuted resources wth Electrc power systems and EEE 59, Recommended Practces for Utltes. But manly ths thess work deals wth slanded operaton of the DGs, and only relevant values were adopted from these standards. 94

95 Chapter 7. General Comparsons and Specfc Component Calculatons 7.. Connecton to Grd and harmonc lmts When the DG s to be connected to a grd, the voltage dstorton lmts must be taken accordng to EEE 59, whch states that the total voltage dstorton for a bus voltages at the pont of Couplng of 69 kv and below must be 5[%]. Normally for such a DG operaton a hgh stffness rato s assumed, and thus harmonc problems by the DG are hardly possble. 7.3 Specfc Converter Values used The rated power of the converter was chosen to be S n kva and the rated AC voltage of the system su n 4V.The Rated (RMS) converter current s Sb kva n 44A, rated Converter current,(rms) 3U 3.4kV n 7.4 Requred DC-Lnk Voltage Snce the rated three phase four wre AC voltage of the system s 4 V, the DC lnk Voltage level must be determned to match ths value, and dependng on the modulaton ndex as well as the modulaton strategy used. The Power ratng of the converter chosen s kva.hence for all the topologes, assumng a modulaton ndex of.8 for a normal SPWM modulaton scheme at frst, the requred DC lnk voltage s found as follows: V ph _ peak V ma dc V Vdc m ph _ peak a 4 3 Vdc 86V.8 But for the topology wth delta Wye Transformer and for the four legged topology, assumng an optmum thrd harmonc njecton,.e. /6 of the fundamental magntude, f a reasonable value of modulaton ndex of. can be attaned, for an out put voltage of 4 V as before, the DC lnk voltage needed would be: ( 86V ).8* Vdc 583V. Thus the requred DC lnk voltage can be reduced ths way. Also as mentoned earler, for the delta wye transformer topology, the DC lnk voltage value can be vared dependng on the transformer sze at hand. 7.5 Requred DC-Capactor sze The DC lnk capactor szes calculated here are manly amed at handlng the worst case mbalance level, whch s a sngle phase load condton. Assumng a modulaton ndex of.8 for convenence, and assumng the rated load sde current s 8% of the converter rated current.e.5 (A). 95

96 Chapter 7. General Comparsons and Specfc Component Calculatons 7.5. Capactor Md pont VS Topology The DC lnk capactor szng of ths converter topology s manly determned by the amount of common mode rpple, as was explaned n Chapters 3 and 4. Thus usng equaton 3- C dc _ Mn ZS 3 ωδu dc 3 ωu Equaton 3-3 dv Assumng the allowed rpple value ( Δ udc ), to be 5 [%] of the DC Lnk voltage (.e. 5[%] of 86 V), and a sngle phase current of 5 (A) RMS, wth a modulaton ndex of.8. The value of the zero sequence voltage would be /3 of the phase value for a sngle phase load, thus the peak value of the zero sequence current s ( )( 5A) 54. A 3 Mnmum value of the capactor needed shall be: ( ) Cdc _ Mn ZS 6.344x 6. 34mF ωδu dc 5 xπx5x x86 Ths value s checked n PSCAD Smulaton as presented n Fgure 7- below. Fgure 7-: Half DC Lnk Voltage rpple for optmum capactor value (PSCAD) Fgure 7- shows that the RMS value of the rpple voltage s around 8 V and the peak value becomes ( )( 9) 4.A whch s almost same as 5[%] of 86 V. Checkng the hold up tme requrements for normal operaton also, we have C t d h dc, Capactor szng for balanced loads Δudc The rated Dc current s Thus kv d. 5A 86V Equaton

97 Chapter 7. General Comparsons and Specfc Component Calculatons t h 5 3 x86x6.344x ΔudcCdc 3.x sec onds,.5 d Thus the hold up tme s mllseconds, whch s a reasonable value. Equaton Four Legged VS and Delta Wye Transformer topologes As was explaned n earler chapters the DC lnk voltage rpples found n these two topologes are dfferental mode harmoncs, thus the capactor szng would be determned by the level of mbalance current, the modulaton ndex and the allowed rpple amount. Usng Equaton 3-3,assumng a modulaton ndex of.8 and same current mbalance wth sngle phase load of 5 (A) RMS only, assumng the allowed rpple to be 5 [%] of the full DC lnk voltage (.e. 5 [%] of 86 V), C 3 _ peak ma dc _ Mn: NS Equaton 3-3 8ω Δudc The peak value of the negatve sequence current ( )( 5A) 54. A _ peak 3 _ peak 3x54.x.8 3 Cdc _ Mn: NS.7x. 7mF 5 8xxπx5x x86 Ths capactor value was used n the four legged topology wth the same crcut parameters as above for check up purposes. Typcally an equvalent total Dc lnk capactor of half the optmum value found above s used and a current of 5 A. The result s plotted n Fgure 7- below. s Fgure 7-: DC lnk dfferental mode voltage rpple n 4 legged VS wth optmum Cdc n Fgure 7-, the total DC lnk voltage rpple s found to be 54 V; whose peak value becomes ( )( 54A) 76. 4V. Ths s close to twce the value of maxmum allowed 5% 97