Re-configurable Electronics Characterization Under Extreme Thermal Environment

Transcription

1 Re-configurable Electronics Characterization Under Extreme Thermal Environment Adrian, Veronica Lacayo, Rajeshuni Ramesham, Didier Keymeulen, Ricardo Zebulum, Joe Neff *, Gary Burke, and Taher Daud Jet Propulsion Laboratory, California Institute of Technology Pasadena, CA * SPAWAR Systems Center, San Diego, CA 1 MAPLD 2005/P232

2 Outline Objective Compensation of degradation in extreme environments Evolvable hardware, reconfigurability, & potential solution. DSP extreme temperature testing, results, conclusions FPGA extreme temperature testing, results, conclusions Reconfigurable Analog Array (RAA) Development, tests in extreme temperatures, results, and conclusions Acknowledgements: The work described in this paper was performed at the Jet Propulsion Laboratory, California Institute of Technology and was sponsored by the National Aeronautics and Space Administration.

3 Objective: Surviving longer missions (10+ years) and harsher environments Dramatic changes in hardware/environment, e.g. in case of faults or need for new functions, may require in-situ synthesis of a totally new hardware configuration. Survivability: Maintain functionality coping with changes in HW characteristics Radiation impacts Temperature variations Aging Malfunctions, etc. EHW Versatility: Create new functionality required by changes in requirements or environment New functions required for new mission phase or opportunity Develop space HW that can evolve 2 MAPLD 2005/P232

4 Compensation of Degradations in Extreme Environments (EE) degradation Microelectronics failure Packaging Less Extreme Environment degradation failure More Extreme Environment Compensation by reconfigurable electronics: - of degradations in electronics keep same function for electronics - or degradations at another subsystem/ or system level adapt electronics functionality to maintain same function at system level Many times failure is due to packaging, but before that point degradations could possibly still be compensated. 3 MAPLD 2005/P232

5 I D (ma) 25 C Effects of EE on electronics Circuits are designed to exploit device characteristics within a certain Temperature/Radiation range; when that is exceeded, the circuit function gradually degrades nmos SI MOSFETs C offset voltage, current leakage... Temperature changes device characteristics; device is still operational. V DS (V) V DS (V) Influence may be different between various areas/circuits/components on same chip. It can also change with function. Changes cause degradation in circuit response of a commercial Op Amp. Output, Gain =1 Input sine wave, f = 100kHz If a circuit design is changed to take in consideration the modified device characteristic the response may be corrected. We can map a new circuit design in a reconfigurable chip 4 MAPLD 2005/P232

6 Hardening-By-Reconfiguration Idea of Hardening-By-Reconfiguration (HBR): mitigate drifts, degradation, or damage on electronic devices in EE by using reconfigurable devices and an adaptive self-reconfiguration of circuit topology. related to HBD - in-situ (re) design benefits from HBD for the resources available on the reconfigurable chips. work well with HBP, - extra layer of protection, for expansion of limits of operation in EE: HBP provides survivability to keep devices operational at higher EE limits, while HBR provides adaptation to changes in device characteristics needed for precise functions, specially for analog. Degenerated HBR: multiplexed/switched in fixed circuits, each optimally designed for a temp range Simple HBR: circuit configuration predetermined and memorized for access when needed, HBR configurations are determined in-situ 5 MAPLD 2005/P232

7 Evolvable Hardware Solutions Evolvable hardware (i.e. hardware that self-configures under control of adaptation/ evolutionary algorithms) can preserve/ recover system functionality by reconfiguration/ morphing. If device characteristics change with radiation/temperature, one can preserve the function by finding a different circuit solution, which exploits the altered/modified characteristics Degraded components can be salvaged Completely damaged components can be bypassed MAPLD 2005/P232 6

8 Reconfiguration Mechanisms Most popular searches: population based, use generate and test strategies. Evolutionary/Genetic algorithms are most used technique. Sketch of a simple Evolutionary/Genetic Algorithm A chromosome may simply encode the control of switches eg Initialize a population of candidate solutions Crossover Evaluate population Create a new population based on old one Select the best Acceptable solution found? No Yes Mutation Output solution Crossover and mutation are two common genetic operators used in creating a new population. 7 MAPLD 2005/P232

9 Evolutionary adaptation of field programmable devices Evolutionary Algorithm Genetic search on a population of chromosomes select the best designs from a population reproduce them with some variation iterate until the performance goal is reached. Chromosomes Conversion to a circuit description Control bitstrings Target response Evaluate individual responses and assess their fitness Circuit response Intrinsic evolution Reconfigurable hardware Potential electronic designs/implementations compete; the best ones are slightly modified to search for even more suitable solutions MAPLD 2005/P232 8

10 A Stand-Alone Board-Level Evolvable System (SABLES) DAC Stimulation FPTA-2 DSP GA runs here FPGA ADC Response Analog Array Digital Interface clk DSP + FPTA Fast download for evaluation of individuals Good architecture for moving to a self-reconfigurable system-on-a-chip DSP board; Fits in a box 8 x 8 x 3. TMS320C6701processor 16 analog inputs and outputs at 100 ksamples; 32 Digital I/O at 7.5MHz 9 MAPLD 2005/P232

11 Recovery of temperature-degraded circuits Controllable Oscillator In Out Evolved at room temperature Deteriorated at o C Recovered at o C Out In 10 MAPLD 2005/P232

12 Summary of Evolvable Hardware HBR (hardening-by-reconfiguration), based on evolvable hardware is a technique that extends the range of usability of electronics in extreme environments. The capability of adaptive selfconfiguration was demonstrated for low and high temperatures. The challenge of conventional design is replaced with that of designing a recovery (e.g. evolutionary) process that automatically performs the (re)design in our place. This may be harder than doing the design directly, but makes autonomy and adaptation possible. MAPLD 2005/P232 11

13 Testing of DSP (TI) under Extreme Temperatures Objective Assess the electrical behavior of the Innovative Integration board containing a Digital Signal Processor (DSP) with its JTAG (Blackhawk) connector at extreme low temperatures to develop Self-Reconfigurable Electronics for Extreme Environments (SRE- EE). The objective of the experiment is to determine the lowest temperature at which the DSP component can operate. DSP chip DSP was tested by running a simple Genetic Algorithm (GA) whose target was the maximization of the number of 1 s in the chromosomes JTAG Connector Problem is solved in less than 1 minute, after 464 generations MAPLD 2005/P232 12

14 Test profile 1 DSP Failure +20 o C 8 min Measurement s made Temperature, C Temp. ramp rate: 5 0 C/min -120 o C Time Failed Test was repeated again for 90 o C, 100 o C, 110 o C and 120 o C to narrow the temperature range. Failure was observed during the testing in a temperature range of 110 o C to 120 o C. Failure occured when PC is downloading GA into the DSP (JTAG communication error); The PC-DSP communication failure prevents the read-out of the DSP status/outputs. DSP Board works down to -110 o C but failed for lower temperatures 13 MAPLD 2005/P232

15 Xilinx Virtex-II Pro FPGA Objective: The purpose of testing this board at extreme temperatures is to initially find out whether the evaluation board and the Virtex-II Pro FPGA would survive and continue operating at different temperature ranges down to 180 o C and up to 120 o C. The Virtex-II PP Board was tested at different temperatures. The temperature range covered in this experiment was from o C to 120 o C. The board was powered using 3 power supplies. They were set up at the following voltages: 3.3V DC (to electronics in the board) 2.5V DC ( to I/O s, banks, Rocket I/O Transceivers) 1.5V DC (supplied to the FPGA Core) Surge current (in rush current) was measured on the 1.5V supply. The test FPGA circuit runs self-checking firmware on 2 embedded processors, monitored via RS232 port 14 MAPLD 2005/P232

16 Extreme Temperature Test for the Virtex-II PP Board Reset switch to reset the logic Program switch to load the program PROMS to FPGA configuration Hello World program used to monitor the performance of FPGA The board was never shut down as the temperature was decreased in steps. Once it reached -180ºC, the temperature was brought back up. At intervals, we power cycle the board and measure the in rush current. It was found as temperature ramped up that the board always powered on using reset program switches. 15 MAPLD 2005P232

17 ma ma Comparisonof VcoreTransient at different Temperatures C -180C -140C -180C -140C -100C Samples FPGA Core Samples in rush current monitored as a function of temperature ma ma ma Vco re In Rush Current at + 20C Samples ma Sam ples Vcore In Rush Current at +120C +20 o C +120 o C Samples Samples FPGA core in rush current monitored as a function of high temperature 16 MAPLD 2005/P232

18 Summary: Extreme Temperature Test for the Virtex-II PP Board The Virtex II Pro functioned correctly at temperatures down to 180 o C and up to 120 o C. The Virtex II Pro FPGA did not show a large in rush current at 180 o C and also at 120 o C. All temperatures, voltages, and current registered normal as well as power (on/off) cycling. Over all the high temperature in rush current transient have sharper current and last less than the cold temperature. (~25-30 msec) MAPLD 2005/P232 17

19 Objectives: Reconfigurable Analog Array (RAA) Development Assess the behavior of G m -C filters building blocks at extreme temperatures (from -180 o C to 120 o C); Perform preliminary tests on the functionality recovery through changes in the voltage bias; Components tested (Designed by SPAWAR using TSMC 0.35µm technology): Operational Transconductance Amplifier (OTA); Wide Range OTA (WRTA); Differential pairs. Simulate and test single-ended first order G m -C filter. 18 MAPLD 2005/P232

20 OTA Sweep Down (23 o C to -180 o C) Iout (A) Date: 28 April 2005 Substrate: FPAA C 0C -30C -60C -90C -120C -150C -180C V2 (V) V1 Vbias Iout V2 Vdd: 3.1V Vbias: 0.8V V1: 1.5V V2: 0-3.0V V(Iout): 2V Current lower and upper limits reduce as the temperature reduces. MAPLD 2005/P232 19

21 OTA Bias Sweep at -180 o C C -180C Vb: 1.0V Vb: 0.95V Iout (A) Date: 28 April 2005 Substrate: FPAA V1 Vbias Iout V2 22C, Vb: 0.8V Vb: 0.9V Vb: 0.85V Vb: 0.8V Vb: V V2 (V) Vdd: 3.1V V1: 1.5V V2: 0-3.0V V(Iout): 2V Device function can be recovered by increasing Vb from 0.8V to 0.85V. MAPLD 2005/P232 20

22 WRTA Sweep Up (-180 o C to 22 o C) Iout (A) Date: 28 April 2005 Substrate: FPAA-01 22C -30C -60C -90C -120C -150C V2 (V) V2 Vbias V1 Iout Vdd: 3.1V Vbias: 0.8V V1: 1.5V V2: 0-3.0V V(Iout): 2V Current lower and upper limits reduce as the temperature reduces. MAPLD 2005/P232 21

23 WRTA Bias Sweep at -180 o C C -180C Vb: 0.9V Iout (A) Date: 28 April 2005 Substrate: FPAA-01 22C, Vb: 0.8V Vb: 0.85V Vb: 0.8V Vb: 0.75V Vb: V V2 (V) V2 Vbias V1 Iout Vdd: 3.1V V1: 1.5V V2: 0-3.0V V(Iout): 2V Device function can be recovered by increasing Vb from 0.8V to 0.85V. MAPLD 2005/P232 22

24 OTA Sweep Up (25 o C to 125 o C) 2.00E E E C 120C 100C 80C 60C 40C 25C V1 Iout V2 Iout(A) 5.00E-05 Vbias 0.00E E E E E E E E E+00 Iout(A) -5.00E-05 V2 (V) -1.00E E E-04 V2(V) Vdd: 3.1V V1: 1.5V V2: 0-3.0V V(Iout): 2V Negative and positive saturation voltages increase as the temperature gets higher. 23 MAPLD 2005/P232

25 OTA Bias Sweep at 120 o C 4.00E E V 0.90V Iout(A) 0.85V 2.00E V Room temperature (0.8V) 0.75V 1.00E V 0.5V-0.65V 0.00E+00 V1 0.00E E E E E E E E+00 Iout V2-1.00E-04 Vbias -2.00E E-04 V2 (V) Device function can be recovered by decreasing Vb from 0.8V to around 0.75V. Vdd: 3.1V V1: 1.5V V2: 0-3.0V V(Iout): 2V 24 MAPLD 2005/P232

26 Objectives: First Order GmC Low Pass Filter Test the recovery through V bias in a filter circuit; Built at the board level using two chips (two OTAs); Characterize filter behavior at extreme temperatures and test recovery through adjustment of bias voltage; C x = 10pF G m V V in + - V out - C a = 10pF Vb2 1.5V Vb1 G m1 Capacitors outside the temperature chamber 25 MAPLD 2005/P232

27 Low Temperature Tests Frequency Response 20 T= 0 o C T= 25 o C 15 T= -120 o C T= -30 o C T= -60 o C Gain (db) Frequency(Hz) -10 T= -150 o C,-180 o C -15 Vb1 = 0.9V, Vb2 = 0.7V Filter transfer response deteriorates below -120 o C. 26 MAPLD 2005/P232

28 20 Function Recovery at 180 o C Room Temperature (Vb1 = 0.9V; Vb2 = 0.7V) Recovered at-180 o C (Vb1 = 0.8V; Vb2 = 0.7V) Gain(dB) Output (db) T= -180 o C (Vb1 = 0.9V; Vb2 = 0.7V) -15 Frequency 1(Hz) MAPLD 2005/P232

29 LowTemperature Response in the Time Domain ( f = 10kHz) Out In T = 25 o C Vb1 = 0.9V Vb2 = 0.7V Vout = 1.8Vp-p T = -180 o C Vb1 = 0.9V Vb2 = 0.7V Vout = 0.1Vp-p T = -180 o C Vb1 = 0.8V Vb2 = 0.7V Vout = 1.4Vp-p Filter Recovery at 180 o C 1. Partial functionality recovery accomplished using manual local search over Vb1 and Vb2; 2. There is possibly one or more pair of values Vb1/Vb2 that produce a better recovery at 180oC Sweep Vb1 and Vb2 using finer steps and/or implement non-local and more systematic search. 28 MAPLD 2005/P232

30 Filter Recovery at High Temperature Series1 Series2 Series3 20 T=25 o C Recovered at T=120 o C 15 T=120 o C Gain (db) Frequency(Hz) -5 Vb1 = 0.9V, Vb2 = 0.7V Filter transfer response slightly deteriorates at 120 o C. 29 MAPLD 2005/P232

31 High Temperature Response in the Time Domain (f = 100kHz) T = 25 o C T = 120 o C T = 120 o C (Recovered) Out In T = 25 o C Vb1 = 0.9V Vb2 = 0.7V Vout = 1.3Vp-p T = 120 o C Vb1 = 0.9V Vb2 = 0.7V Vout = 0.9Vp-p T = 120 o C Vb1 = 1.1V Vb2 = 0.6V Vout = 1.3Vp-p MAPLD 2005/P232 30

32 Conclusions Results indicate that bias voltage control adjustment is an efficient mechanism for circuit recovery at extreme temperatures. Small changes in the bias voltage are sufficient to promote functionality recovery of the OTA and WRTA devices tested at low and high temperatures; Low Pass filter recovery was also possible through changes in the bias voltages more systematic search methods and/or algorithms needed to further improve recovered function. MAPLD 2005/P232 31