Feasibility of a multifunctional morphological system for use on field programmable gate arrays

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1 Journal of Physics: Conference Series Feasibility of a multifunctional morphological system for use on field programmable gate arrays To cite this article: A J Tickle et al 2007 J. Phys.: Conf. Ser View the article online for updates and enhancements. Related content - Multifunctional material probe for impurity fluxes characterization L Begrambekov and A Grunin - Multifunctional optical processor for biological micro-objects investigation K Domnin and E Aksenov - Multifunctional centrifugal grinding unit V S Sevostyanov, V I Uralskij, A V Uralskij et al. Recent citations - Use of an Infrared Thermometer with Laser Targeting in Morphological Scene Change Detection for Fire Detection Andrew J Tickle et al This content was downloaded from IP address on 08/11/2018 at 03:10

2 Feasibility of a Multifunctional Morphological System for Use on Field Programmable Gate Arrays A J Tickle, J S Smith, Q H Wu, Department of Electrical Engineering and Electronics, The University of Liverpool, Liverpool L69 3GJ, U.K. a.j.tickle@liv.ac.uk, j.s.smith@liv.ac.uk, q.h.wu@liv.ac.uk Abstract. In this paper, we ll investigate the development of a multifunctional morphological system that can execute either a single morphological operation or a string of operations and can also perform extra logical operations on the result at any stage along the way. This paper will cover how the control circuitry was designed, how the previously developed operations were inserted into the system, how the extra operation circuitry was designed and again this was all done using the graphical model based design methodology which allows the entire functionality of the system to be contained within the Simulink DSP Builder HDL development tool. Testing will involve whole image systems where the resultant image is compared against pre-calculated MATLAB sequences of morphology for a comparison to ensure that the data-stream has travelled correctly through the system using the correct pathway through the blocks defined by the control signal. 1. Introduction This paper continues the work started in [1] by using the operations presented previously and since all morphological operations (MOs) are made up of simply erosion, dilation, opening and closing in a specific given order for different tasks, there was the need to design a multipurpose system that allows the user to pick and select the order of the processes and which output feeds into which input. The system proposed here will be able to handle up to 16 MOs which can be followed or used, however the proposed system would give us possible combinations and this is obviously a little too complex to design a system for and so it was split into 3 smaller systems of a string of 4 operations and a total of 16 blocks which would give us a total of 342 combinations (including special operations) for gray-scale operations and 340 combinations for binary operations which is a little easier to design. This process was repeated several times and controlled by a master control block, but we shall focus on one of these smaller systems in this paper. The user may also wish to combine the system output at certain stages with the previous input of itself (like with morphological contours or morphological gradient) or logical AND or logical OR with other systems that can be running in parallel together. Other functions such as logical XOR and logical NAND could be added if so required by a process of simply modifying the blocks that do the operations and the control signals that feed them. c 2007 Ltd 1

3 2. Control Signals and Extra Operation Circuitry Other systems presented in literature thus far have had control signals used in their design and implementation before but none that are as complicated as this, the most commonly used control signal is to either tell the system to perform erosion or dilation depending on if the signal was a 1 or a 0 [2]. This system will require 3 numerical signals going into it, one for the operation sequence (the full table of operations and their descriptions and corresponding control signals is over 8 pages long and so isn t included in this paper), one for the cycle number and one for the operation number, the latter two values will be discussed in more detail later on. All these control signals will be sent out to activate the correct blocks and the add operators, logical AND s etc and so required a logic circuit in order to do this and so split the number into its binary counterpart and feed these into the logic circuit as for the convex hull thinning system presented in [1]. These will then feed into a 9 input AND gate and the output from this block will be the control signal we require to activate the blocks. These outputs would then be fed into the blocks which respond to that combination so that they can be activated and allow data to pass into them otherwise no data is allowed in. At each stage or layer of the system there is only one block that will be active at any one time so a simple multiple input OR gate can be used to recombine the signals into one as the other signals will all be zero and thus won t affect the dataline with actual values on it. This would mean that we have many of these signals and so we also need to a way to activate the adds, subtracts, OR s and AND s etc for that specific combination. Figure 1 shows the system to do this where we add the straight output signal with the signal that lets us know if we want to AND, OR etc by using the 2 input AND gates thusly. Now that we have a pure control signal, we needed to find the best way to insert the number of cycles with the operation is to occur over. This gives us the choice of 1, 2, 3 or all cycles and the cycle control signal is sent to all the blocks and deciphered from there. Figure 1. Logic circuit to add the extra operations into the system The sub-control system blocks (shown as the black area of Figure 2) need a 1 or a 0 to activate the add, subtract etc and also a way to divert the signal and previous version into the logic devices in order to actually do the required operation. Also we need to be able to pass the information from one block to another so that the flow of pixel data can be assured. The first thing that is required is to prevent all the data progressing through the blocks which won t need it and secondly we need a system to handle the more complex situations. In the black part of Figure 2 Data-Out allows the system to pass the most current data out by either using an AND gate to combine the active output signal with the data so for binary signals its always low if the Output signal is low and the correct values are given when it s high because if the data is a high then both inputs of the AND gate are high and so the 2

4 Figure 2. Layout of all the operation control circuitry output is high and if the data is low then both inputs to the AND gate aren t high and so the output is low. For grayscale systems we would use the product block in Simulink so when the Output signal is active then the data value is multiplied by a 1 and so the output is the input otherwise the data out is permanently low. The same process is repeated for the previous data signal where if anyone of the operation control signals are high then the output from the OR gate is high and that feeds into the AND gate and the same thing happens as for the other AND gate. Also we require that if the system detects any of the other outputs such as the Out-AND signal for example then the output signal isn t sent directly to the output but to the other logic devices. In Simulink we can just used the built in add and subtract blocks where for a 1 they would add and for a 0 they would subtract and so we could either use one block with another control signal or two separate blocks for each function and it was deemed easier to use the latter. The first prototype of this system is shown in Figure 3, the control signals are used in conjunction with the AND gates so that only the correct function (AND, OR, Add or Subtract) receives non-zero data values and hence can be calculated. One AND gate controls and passes out the current data signal and one passes out the previous cycle data signal, they work in pairs, almost like muscles apart from the basic pass the data to the output when there is no extra operation. Since only one system should output values at any one time, this allows us to use the 5 input OR gate so combine all the signals together and still retain the correct value. When connecting in the previous system signals we just connect them to previous outputs as shown previously [1] with the original Thinning / Convex Hull system test. The next part of the system to be developed was the cycle controls which were a little more complicated than first expected. This is illustrated in Table 2 and if no extra cycles are required then we needed to automatically set this system to 0. The same process is repeated for the values that will let the system know if it needs to add the blocks together, subtract them etc. An overall signal producer had to be designed and the values for the different operations are shown in Table 2. The two circuits shown in the black area of Figure 2 act in a very similar manner, the numerical values go into the system and the bit extraction blocks are set to extract the zero, first and second bits. These are sent into 3 input AND gates where certain inputs are inverted 3

5 Figure 3. System to carry out the extra operations Table 1: Table showing which blocks will be activated and their corresponding binary code Cycle Number Blocks Used Binary Code for Cycle 0 No blocks Input signal and block Blocks 1 and Blocks 2 and Blocks 3 and All blocks 101 Table 2: Table showing the extra operations and their corresponding binary code Operation Number MO Additional Operation Binary Code for Operation 0 None Logical AND Logical OR Numerical Add Numerical Subtract 100 so when the correct binary combination comes up, only one AND gate goes high and produces the control signal which is sent to the other blocks. The right most part of that section shows the way in which we make sure that there are no extra operations and sets the cycles value automatically to 0. The system still outputs the Block-12, Block-23, etc signals but also sends them into the OR gate and then into two input AND gates whose other inputs are the original Out-AND, Out-OR signals etc and so only if a block or cycle is high and an operation is high will one of the outputs be high and as a result activate the correct block. The other AND gate combines the Block-None and Out-None signals which lets the system know just to cascade the blocks together. Lastly we need to mention about how to integrate the cycle number into the system previously 4

6 Table 3: Table to show which routes and where the end block will be Operation Number Limit Corresponding End Block Number 1 x x x x x 342 -N/Ashown in Figure 3 so that the cycle number is sent into all blocks and is used to activate the correct functions within that block so that without either the cycle number or operation number the system will remain inactive. This circuit is shown in the green area of Figure 2. However we needed to add one more thing to the system which was the way to let the blocks know that they are the last block in the sequence and to output the answer and by-pass any remaining blocks if any. Since we have 342 combinations, 340 standard combinations, the best way would be to have some sort of system that knows the route from the control signal and between certain numbers on this control signal also sends along a signal to let the blocks know when to output the data to the end. Table 2 shows the different cycles for the different control signals. 3. Levels of Abstraction Figure 2 shows the system composing of the circuitry mentioned previously combined together to make the fully functioning system with a slight addition which will hence be required for each block depending on if it is in the second stage, third or the fourth stage for the cycle of the extra operation required. The way this has been integrated into the system is to divide the cycle controls into 12, 23, 34 and all and then OR the all with each of the others separately to produce 3 signals. Now depending on where the block is in the system, the desired signal will be sent into the cycle-control wire (shown in the red highlighted area) whilst the remaining unused signals will be sent to termination blocks to prevent any further use in the system. The system was designed that way in order for the block to be easily inserted into all the blocks when building and then one wire is altered for each case. This is shown as a separate system here to make it easier to understand but this operation control circuitry along with the calculation circuitry and activation circuitry will all be put into a single block making 16 separate and unique systems. Figure 4. Activation circuitry for each block in the system 5

7 Figure 5. Behavioural level model Figure 6. RTL level model Figure 7. Gate level model for an operation block 6

8 In Figure 4 is the activation circuitry so that when the operation number is imputed from the table of commands, it will break it down into its binary components and analyse it and from this the correct blocks can be added. It s a larger and more complicated version of the combination lock which was developed for the Convex Hull Thinning system [1]. The levels of abstraction which include all thecircuit details are shown in Figures 5 to Figure 7 4. DSP Builder Simulation Results The testing process has consisted of 14 standard separate tests and 3 extra functional separate tests that tested each layer of the system to prove that it works correctly and this was chosen because it is obviously too time consuming to test all the possible combinations with all the extra features. The test setting for each layer comprised of a single or sequence of the basic operations (erosion and dilation), the advanced single step operations (opening and closing) and a combination of the two for each layer. The remaining two standard tests were for incorrect or large number values in case an incorrect value is entered and the second was for an operation number of zero to prove that no output images are obtained for these values while the extra functions combined previous versions of themselves with logical operations. The output test sequence as in previous work [1] was ran through a MATLAB m-file code to compare the number of pixels and locations to a check each image produced by the built in MATLAB operations from the image processing toolbox. These results are displayed in Figure 8(a) to Figure 8(c) and show for a standard test, operation 8 which was a sequence of dilation-opening and its corresponding check, the binary values are inverted but as you can see the images are the same and this was verified by the check with only a slight difference in images which can be accountable to the slight differences in calculation methodology. When performing the tests concerning incorrect control signals we noticed that if it is outside the range of the numbers, for example 521 is binary and using a 9-bit wide data line means that only is sent into the system and so that is operation 9 which is erosion-dilation in two separate steps and so an extra circuit shown in Figure 9 was added in order to compensate for this and was added to the end of the OR-gate network at the end of the block. This circuit takes the operation number and is very similar to a piece of the circuitry inside the blocks to let the block know which layer it is in. There are two standard DSP Builder comparator blocks, with the op-number going into them and one is set to with the reference 1 going into it and the other is set to with the reference 342 going into it and so if the op-number is between or equal to these values then their outputs are both 1 and are both fed into a 2 input AND gate so that when both signals are active i.e. when the number lies between these values the output from the AND is a 1 and this is then fed into a product block which is multiplied with the output data and allows the data to be passed out. If the number doesn t lie within the range then the output is 0 and basic mathematics says that multiple anything by zero and it becomes zero itself and so nothing is passed out. 5. Conclusions and Future Work The conclusions are that in this paper, we have described and examined a useful system for performing a range of MO s which additional logic or mathematical operations can be performed between the stages. This system can handle both binary and greyscale images for basic SEs by a simple case of interchanging the operation circuitry in each block. Extensive simulation results show that the proposed system obeys the control signals and follows the correct path through the system and outputs at the right point and propagation delay doesn t affect the system and delay gates were added to allow the previous data signals into the system for comparison and were passed through a series of 2 input OR gates with the inputs tied together for the average propagation time (times obtained in development stage) through the actual 7

9 Figure 8. Simulation results for operation 8, dilation-opening, (a) Binary counterpart of original image; (b) Multifunctional system result; (c) MATLAB built in operation checks. morphological operation circuits so that the same pixel area in the current and previous image are examined and without this the number of errors is greater. The advantages of this work are that because we have a system capable of doing the operations we can simply change the actual operation and it can be applied to greyscale images, colour images or any other type of operation that can be cascaded together by simple modifications to certain parts of the circuit and for more or less operations we can simply increase or decrease the number of layers where required. Future work will consist of continuing to develop more advanced control systems for this system so a greater string of extra operations can be implemented and to improve the efficiency of the circuit so that less resources are taken up on the chip by such ways as only using 1 line buffer per layer but this would increase the number of data lines and thus increase the risk of propagation delay affecting the system. Also work into more control engineering based applications will be investigated to see if this is possible with this type of design methodology. Acknowledgements The authors would like to thank the associate editor and anonymous reviewers for their valuable comments and suggestions. Mr Tickle would also like to thank his friends Si Ella Li and Theoharis Harris Spertos for the use of the pictures with them in so that the MOs developed could be tested and to the EPSRC (Engineering and Physical Science Research Council) for funding this research work. 8

10 Figure 9. Modifications to OR network hub in order to counteract for incorrect control signals References [1] Tickle A J, Smith J S and Wu Q H 2007 Development of Morphological Operators for Field Programmable Gate Arrays Proceedings of the IoP Conference: Sensors and their Applications XIV, Liverpool John Moores University, Liverpool, UK [2] Louverdis G and Andreadis I 2003 Design and implementation of a fuzzy hardware structure for morphological color image processing IEEE Transactions on Circuits and Systems for Video Technology, Volume bf 13 pp