AS A CRUCIAL core block in modern signal processing

Transcription

1 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 6, NOVEMBER Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier Choong Hyun Lee, Se Woon Kim, Jang Uk Lee, Seung Hwan Seo, Gu-Cheol Kang, Kang Sup Roh, Kwan Young Kim, Soon Young Lee, Dong Myong Kim, Member, IEEE, and Dae Hwan Kim Abstract As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SETs such as the tunnel barrier lowering effect, parasitic MOSFETs operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFETs and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADCs fully accounting for nonideal effects of real SETs is successfully demonstrated for the first time. Compared with the previous SET-based ADCs, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability. Index Terms Analog-to-digital converter, physics-based SPICE model, SET/CMOS hybrid amplifier, single-electron transistor, transient characteristics. I. INTRODUCTION AS A CRUCIAL core block in modern signal processing systems, performance specifications, including higher integration density, faster conversion speed, and low power dissipation of analog-to-digital converters (ADCs) become more and more challenging to satisfy. In this viewpoint, the Si single-electron transistor (SET)-based ADC circuit is a promising candidate due to potential advantages of high integration density, ultralow power dissipation, and extremely simple structure. Up to now, several Si SET-based ADCs have been proposed [1] [4]. However, the models used in previous circuits cannot be directly applied to analyze and optimize the performance of SET-based ADC circuits in a real chip. This Manuscript received March 6, 2007; revised June 11, This work was supported by of Kookmin University (Korea) under Research Program 2007, and the CAD software was supported by the IC Design Education Center (IDEC). The review of this paper was arranged by Editor K. Wang. C. H. Lee was with the School of Electrical Engineering, Kookmin University, Seongbuk-gu, Seoul, , Korea. He is now with University of Tokyo, Tokyo , Japan. S. W. Kim, J. U. Lee, S. H. Seo, G.-C. Kang, K. S. Roh, K. Y. Kim, S. Y. Lee, D. M. Kim, and D. H. Kim are with the School of Electrical Engineering, Kookmin University, Seoul, , Korea ( drlife@kookmin.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TNANO is because previous works are validated only by the comparison with Monte Carlo simulation results [1] [4] rather than the experimental data. Actually, nonideal effects such as the control gate bias -dependence of a tunneling resistance, parasitic field-effect transistor (FET) operation, and the phase shift of Coulomb oscillation by the bias of gate other than a main control gate have been commonly observed in demonstrated Si-based SETs [5] [11]. They cannot be considered in the Monte Carlo simulation based on the orthodox theory of single-electron tunneling. On the other hand, a dual-gate SET (DGSET) showed the feasibility of a controllable and reproducible Si-based SET [7], [8], and Lee et al. developed the practical SPICE model based on nonideal physical phenomena in measured data of the fabricated DGSET [12]. In this work, we propose and implement a complementary SET/CMOS hybrid amplifier-based ADC by using Lee s SPICE model. Its core scheme is eliminating an increasing Coulomb blockade oscillation valley current with increasing, temperature, and the island size by using the SET/CMOS hybrid amplifier. Furthermore, the transient operation of SET/CMOS hybrid circuit-based ADCs fully accounting for nonideal effects of real SETs is successfully demonstrated at 77 K. II. DESIGN OF ADC CIRCUIT BASED ON REALISTIC SETS A. Device Structure and Electrical Characteristics of Si-Based SETs A schematic diagram and its equivalent circuit diagram of the fabricated DGSET are shown in Fig. 1 [8]. The electron channel in the silicon-on-insulator (SOI) nanowire is induced by both the control gate voltage ( ) and back gate voltage ( ). Two tunnel barriers are electrically induced by the bias of the poly-si sidewall depletion gates ( ), and the potential in the Si island is controlled by the bias of the poly-si top control gate ( ). Therefore, the size of the Si island can be controlled by both the width of SOI nanowire ( nm) and the separation between two sidewall depletion gates ( ). In Fig. 1(c), the and are the capacitance between the Si island and the control gate, and the capacitance between the Si island and the sidewall depletion gate, respectively. We note that the fabrication process is fully compatible with the conventional CMOS VLSI technology due to the sidewall patterning technique [7]. Fig. 2 shows the schematic diagram of the drain current - characteristics of the fabricated DGSET. Compared with the orthodox theory of single-electron tunneling, nonideal X/$25.00 IEEE

2 668 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 6, NOVEMBER 2007 Fig. 1. (a) Schematic diagram of the DGSET with sidewall depletion gates on a SOI nanowire. (b) Cross section of the fabricated DGSET. (c) Equivalent circuit diagram of the fabricated DGSET. (Reprinted from [8], with permission of the authors). Fig. 2. The schematic view of electrical characteristics of the DGSET. effects in real SETs can be summarized with the tunnel barrier lowering effect, parasitic MOSFET operation, and the phase shift of Coulomb oscillation by the. First, the temperature dependence appears on the peak to valley current ratio (PVCR) decreasing with increasing temperature. This is well known to be smearing out of the Coulomb blockade condition by the thermal energy. The tunnel barrier lowering effect appears on the reduced PVCR with increasing, which results from the lowered barrier height due to the electric field effect formed by the control gate. The parasitic MOSFET appears as the -dependent electron density in SOI nanowire and the valley current of the Coulomb oscillation increases with increasing. The phase shift of the Coulomb oscillation by the is due to the sharing of the Si island charge between all of the gates. These nonideal effects have been commonly observed in previously reported Si-based SETs with the gate-controlled structure [6] [11]. In spite of nonideal phenomena, Si-based gate-controlled structure is believed to be the most promising SET structure in terms of the controllability, reproducibility, and the possibility of integration with Si CMOS technology within near future. Therefore, in the design of the SET-based or SET/MOSFET hybrid circuit, these nonideal effects should be fully considered. Fig. 3. Measured and simulated I -V characteristics of the fabricated DGSET. (a) Temperature dependence (V = 1 mv, S = 40 nm). (b) Tunnel barrier lowering effect and phase shift of Coulomb oscillation due to V at 77 K (V =5mV, S =40nm). (c) Island size dependence at 77 K (V =1mV). (Reprinted from [12], with permission of the authors). On the other hand, the incorporation of the SET theory into a circuit model has been pursued by several research groups [12] [14]. Among these approaches, Lee et al. developed practical SPICE model based on the physical phenomena in fabricated DGSET. Both the measured and simulated - characteristics of the fabricated DGSET are shown in Fig. 3 [12]. Temperature dependence, phase shift of Coulomb oscillation, and island size dependence are shown in Fig. 3(a), (b), and (c), respectively. The SPICE simulation result shows good agreement with the measured data over the wide range of temperature, the Si island size and the bias. We note that Lee s SPICE model fully accounts for the nonideal effects of real Si-based SET characteristics and its physicsbased nature is verified by the comparison with the experimental data.

3 LEE et al.: DESIGN OF A ROBUST ANALOG-TO-DIGITAL CONVERTER BASED ON COMPLEMENTARY SET/CMOS HYBRID AMPLIFIER 669 temperature, the voltage, and the island size [12]. On this background, these tunnel junction parameters are used throughout this work. Using SET inverter as a building block, as shown in Fig. 5, a 4-bit ADC architecture is simply implemented with a sample and hold circuit block, a capacitive divider, and four SET inverters with the same circuit parameters. In the 4-bit ADC circuit, the analog signal input is sampled and held as, and it is consequentially divided into, where,1,2,and 3, by the capacitive divider. It is encoded into the corresponding 4-bit digital signals by the complementary SET inverters. Fig. 6 shows the simulated conversion characteristics of the 4-bit ADC based on complementary SET inverter at 27 K. This result shows only that ADC circuit proposed by Hu et al. [3] is reproduced. It should be emphasized that nonideal effects in real Si-based SETs are fully included in this implementation while Hu s ADCs were based on only Monte Carlo simulation with the orthodox SET theory. We also note that the operation temperature of 27 K is relatively higher than those of previous works [2], [3]. Fig. 4. (a) Circuit diagram for a complementary SET inverter. (b) Separated I -V characteristics of upper SET and lower SET, respectively. (c) Voltage transfer characteristic of a complementary SET inverter. Parameters used in SPICE simulation are as follows: V = 10 mv, V = 00:16 V, V = 0 V, C = 0:24 af, C = C = 1:3 af, R = R = 1:3 M (corresponding to S =40nm), and the load capacitance C =1pF. B. Implementation of SET-Based ADC Circuit In order to fully account for the nonideal effects in real SETs, we adopt Lee s SPICE model in designing SET-based ADCs. First of all, we implement a simple ADC circuit based on a complementary SET inverter consisting of two SETs in series. Fig. 4(a) shows the circuit diagram for a complementary SET inverter, and Fig. 4(b) shows separated - characteristics of upper and lower SETs, respectively. The operation temperature is set at 27 K. The peak position of the is controlled by the, which has already been verified to be controllable in the previous work [8]. The voltage transfer characteristic of the complementary SET inverter at 27 K is shown in Fig. 4(c). In order to implement an SET inverter with 50% duty ratio, we adjusted the to V and V to obtain a half-period phase shift of the Coulomb oscillation. When the upper SET turns ON, the lower SET turns OFF because SET has the inherent Coulomb oscillation characteristics with the period of. The details of circuit parameters are as follows; the supply voltage mv, V, V, af (corresponding to nm), the capacitances of tunnel junctions af, the resistances of tunnel junctions M, and the load capacitance pf. The SET model parameters used in this work are based on the experimental results. In our previous work [7], [8], both the capacitance of tunnel junction ( 1.3 af) and the resistance of tunnel junction ( 1.3 M ) have been extracted from characteristics of many devices. In addition, our previous works show that the tunnel junction parameters are reproducible and controllable by using sidewall depletion gates, irrespective of the island size [7], [8]. Furthermore, the simulation result shows good agreement with the experimental data in wide range of the III. DESIGN OF ADC CIRCUITS BASED ON SET/CMOS HYBRID CIRCUIT A. Self-Biased SET/CMOS Hybrid Periodic Binary Converter-Based ADCs We showed that a 4-bit ADC circuit based on a realistic 40-nm Si island SET inverter has a good conversion characteristics at 27 K. However, the load capability and signal swing of ADCs are the other critical issues. The swing of output signal in Fig. 6 is too small to use in practical applications. Moreover, the SET valley current increases with increasing both the and temperature due to nonideal effects, as shown in Fig. 3(a) and (b). In order to verify this limitation of real SET-based ADC circuit, we simulate the conversion characteristics at 57 K. The signal conversion becomes more erroneous as shown in Fig. 7. Main cause of this error is the degradation of switching performance due to decreased PVCR in SET current at high temperatures. Although the PVCR can be improved by the scaling of the island size, it is beyond the state-of-the-art process technology. This result shows that the SET inverter-based ADCs have the inherent limitations including high sensitivity to temperature variation, low load capability, and small swing of output signal for the practical circuit implementation. In order to overcome the limitation such as the degradation of PVCR and a small output signal swing, the self-biased SET/CMOS hybrid periodic binary converter scheme has been recently proposed by Song et al. [15]. It shows that the commonly increased valley currents of two complementarily switched SETs can be cancelled out by the differential amplifier based on pmosfet current mirrors. Fig. 8(a) shows a schematic diagram of self-biased SET/CMOS hybrid periodic binary converter and Fig. 8(b) shows its voltage transfer characteristic at 77 K, respectively. A pair of current modulation blocks shown in Fig. 8(a) is combined to utilize the differential amount of the complementary currents, which does not diminish with increasing and temperature. As shown in

4 670 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 6, NOVEMBER 2007 Fig. 5. Architecture of a 4-bit SET inverter-based ADC. It is implemented with a sample and hold block, a capacitive divider, and 4 SET inverters with the same circuit parameters as used in Fig. 4. Fig. 6. Simulated conversion characteristic of a 4-bit ADC based on complementary SET inverter at 27 K. Fig. 7. Simulated conversion characteristic of a 4-bit ADC based on complementary SET inverter at 57 K. Fig. 8(b), the Coulomb oscillations of two SETs are successfully transformed into voltage signals with a full swing even when the operating temperature increases up to 77 K. It is noticeable that the swing of output signal changes from 10 mv to 3 V by using MOSFETs as output drivers. With this scheme shown in Fig. 8(a), nonideal effects of a real SET can be efficiently suppressed. By replacing a complementary SET inverter in Fig. 5 with self-biased SET/CMOS hybrid periodic binary converter in ADC architecture shown in Fig. 8(a), we implement a 4-bit SET/CMOS Fig. 8. (a) Schematic of a complementary self-biased SET/CMOS hybrid periodic binary converter and (b) its voltage transfer characteristics at 77 K. Here, V =3V, W =1m, L =4mfor pmosfets (M and M ) and W = 0:3 m, L = 1m for nmosfets (M and M ), respectively. The SET device parameters are C =0:24 af, C = C =1:3aF, R = R =1:3M (corresponding to S =40nm) (Reprinted from [15], with permission of the authors). hybrid periodic binary converter-based ADC circuit. Its design and optimization result is shown in Fig. 9. The ADC operation is successfully demonstrated at 77 K, which is relatively high operation temperature even in the case of the circuits based on ideal SETs. When compared with SET inverter-based ADC circuits, our SET/CMOS hybrid periodic binary converter-based ADC circuit provides a large input/output signal swing and large load capability as well as immunity to temperature variation. Furthermore, comparing with previously proposed SET/MOSFET hybrid ADC circuits [4], nonideal effects in real Si-based SETs are fully considered in our implementation of ADC circuits. B. Complementary SET/CMOS Hybrid Amplifier-Based ADCs and Their Transient Characteristics Up to now, we have examined only the dc characteristics of SET/CMOS hybrid circuit-based ADCs. Although the is the function of time in Figs. 6 and 9, the time has such a arbitrary unit that the speed of ADC response cannot be quantitatively estimated. These problems are common in previous works on SET-based ADCs [1] [4]. In the conventional CMOS-based ADCs, the conversion speed is actually dependent on the performance of the sample and hold circuit block. However, in the case of SET-based ADCs, the conversion rate of the already

5 LEE et al.: DESIGN OF A ROBUST ANALOG-TO-DIGITAL CONVERTER BASED ON COMPLEMENTARY SET/CMOS HYBRID AMPLIFIER 671 Fig. 9. Simulated conversion characteristic of a 4-bit ADC based on SET/CMOS hybrid periodic binary converter at 77 K. sampled input should be noted due to a low current drivability of SET. In the case of self-biased SET/CMOS hybrid periodic binary converter as shown in Fig. 8(a), the low current ( na) of SETs cannot fully drive parasitic capacitances in MOS- FETs. Actually, in spite of its importance, the transient characteristics of SET and/or SET/MOSFET hybrid-based ADCs have been rarely reported yet. It is strongly required to investigate the transient characteristics in terms of the dynamic aspects of the ADCs. Recently, Mahapatra et al. have proposed a hybrid SETMOS architecture for high current driving capability [16]. However, this approach suffers from two major limitations. First, it needs an ideal current source in the range from pa to na for proper operation. Second, it excludes nonideal effects of real SETs which become more serious when the SET current is amplified by MOSFETs. In order to implement SET/CMOS hybrid ADCs with the high load drivability including nonideal effects, we propose a SET/CMOS hybrid amplifier as the first step. Fig. 10(a) shows the unit block of SET/CMOS hybrid amplifier. It combines a real SET with depletion mode nmosfet replacing the ideal current source, and transforms the change of the drain voltage in SET to the nmosfet current. We assumed that the interconnection capacitance is much larger than the SET capacitance. The drain of SET is connected to for maintaining the SET drain node at a nearly constant voltage through a common-gate MOSFET buffer, and gate is connected to the drain of SET as a current amplifier. Here, both and are depletion mode nmosfets for the appropriate biasing of the SET. The is biased in the subthreshold region (weak inversion) to obtain both low power dissipation and high sensitivity of drain current when varies by only tens of mv s. SET device parameters are as follows: af, af, M (corresponding to nm for Si island size). The MOSFET device parameters are as follows: m, m for the and m, m for the, respectively. Then, the drain current (output current) is exponential function of the SET drain voltage, and the amount of current amplification depends on both the temperature and the feature size of MOSFET as a current amplifier. Fig. 10(b) shows the - characteristic of the SET/CMOS hybrid amplifier at various temperatures. Here, the Fig. 10. (a) Schematic diagram of the unit block of SET/CMOS hybrid amplifier, and (b) its I -V characteristics at various temperatures. Here, both M and M are depletion mode nmosfets for the appropriate biasing of the SET. The SET device parameters are as follows: V = 00:16 V, V = 0V, C =0:24 af, C = C =1:3aF, R = R =1:3M (corresponding to S = 40nm for Si island size). The MOSFET device parameters are as follows: W = 2:5 m, L = 0:18 m for the M and W = 0:5 m, L =0:18 m for the M, respectively. increases linearly from 0 to 3 V for 100 ns. As expected, the level of SET current is amplified from na to A. However, the level of SET valley current is also amplified by the at 77 K such that it cannot work properly as a switching logic circuit. This result shows that the simple SET/CMOS hybrid amplifier cannot be applicable to the implementation of real SET/CMOS hybrid ADCs due to nonideal effects in real SETs. For successful implementation of SET/CMOS hybrid ADCs with the high load drivability including nonideal effects in real SETs, we propose a new complementary SET/CMOS hybrid amplifier as shown in Fig. 11. Each circuit is composed of a pmosfet, an nmosfet, and a SET/CMOS hybrid amplifier. The odd mode current ( ) is produced by biasing the SET at V( ) while the even mode current ( ) is produced by biasing at V( ). A complimentary pair of current can be obtained by adjusting the (3 V) and the threshold voltage of pmosfet ( V). Here, the are all depletion mode nmosfets with the threshold voltage of V. The drain voltages of SETs can be kept constant through the common-gate MOSFET buffers ( and ) independent of the output voltages in the circuit. The circuit parameters are as follows: V, V, V, V. For correct functionality, the feature sizes of MOSFET devices are optimized as follows: m, m for nmosfets ( and )asa current amplifier, m, m for nmosfet

6 672 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 6, NOVEMBER 2007 Fig. 11. Schematic diagram of the complementary SET/CMOS hybrid amplifier. Here, V = 3 V, V = 00:16 V, V = 0 V, V = 0:1 V. The SET device parameters are as follows: C = 0:24 af, C = C = 1:3 af, R = R = 1:3 M (corresponding to S = 40 nm for Si island size). The feature sizes of MOSFET devices are optimized as follows: W =2:5 m, L =0:18 m for nmosfets (M and M ) as a current amplifier, W =0:5 m, L =0:18 m for nmosfet (M and M ), W =0:5 m, L =0:18 m for nmosfet (M and M ) as a common-gate MOSFET buffer, and W =14 m, L =1:5 m for pmosfet as a current mirror (M and M ), respectively. ( and ), m, m for nmosfet ( and ) as a common-gate MOSFET buffer, and m, m for pmosfet as a current mirror ( and ), respectively. Fig. 12(a) and (b) shows the - characteristic and dc voltage transfer characteristic of the complementary SET/CMOS hybrid amplifier, respectively. In principle, assuming that the difference between and is sufficiently large, this switching logic circuit carries out a correct function regardless of the level of the SET valley current. For the robustness of switching characteristics, this complementary set of currents deserves special attention, because the difference between complementary currents ( and ) does not diminish with increasing the, temperature, and/or the island size. It is the origin of the immunity to nonideal effects in real SETs of the complementary SET/CMOS hybrid amplifier. Fig. 12(c) and (d) shows its transient characteristics for to 3 V for 200 ns. This is the first demonstration of the transient characteristics of SET/CMOS hybrid ADC circuits fully considering the nonideal effects in real SETs. It is noticeable that while Fig. 12(c) shows the transient characteristic, Fig. 12(a) shows the dc voltage transfer characteristic. The current peak of is not shown in Fig. 12(a) when the is higher than the. It results in the logical 0 value of the output voltage. Therefore, the phase difference of between the and is shown only in the transient characteristic, as shown in Fig. 12(c). Here, it is firstly worthwhile to note that the sensitivity of the circuit performance to the change of the SET drain voltage is the optimization issue. The large change of the drain voltage actually induces the change of PVCR of the SET current. However, increasing valley current can be somewhat cancelled out by the common valley current rejection function of the differential amplifier, because the peak position of SET current is not much influenced by the change of the drain voltage. In order to make the best of both the robustness and the performance, the common-gate MOSFET buffer is connected to the drain of SET for the purpose of minimizing the change of drain voltage, while a high transconductance ( ) of nmosfet is used for aiming to efficiently converting the small change of a drain voltage to the nmosfet current in complementary SET/CMOS hybrid amplifier. Second, the control of the is critical to the circuit operation. Actually, it is the fact that both the common valley current rejection function and the PVCR improved by a further scaling-down make the circuit performance more insensitive to the mismatch of a pair of two s. On the other hand, the change of the island size by increasing is relatively less critical than the tunnel barrier lowering, because of the three-dimensional device structure, i.e., sidewall depletion gates warping the SOI nanowire. As shown in our previous work, the oscillation period ( ) of multiple current peaks is well maintained in wide range of [7]. This insensitivity of to, in that the island size is controllable mainly by,, and, while the island potential is independently controlled by, is very useful to the complementary SET/CMOS hybrid amplifier. This result shows that the proposed complementary SET/CMOS hybrid amplifier is very useful for implementing ADCs and other logic circuitry in terms of both high load drivability and immunity to nonideal effects in real SETs. By replacing SET inverter in Fig. 5 with the complementary SET/CMOS hybrid amplifier in Fig. 11, we propose the complementary SET/CMOS hybrid amplifier-based ADCs, as the last step. Fig. 13 shows that the proposed ADCs have good transient characteristics and clearly display a 4-bit ADCs behavior up to 77 K, which is relatively high operation temperature in the case of SET-based circuits.

7 LEE et al.: DESIGN OF A ROBUST ANALOG-TO-DIGITAL CONVERTER BASED ON COMPLEMENTARY SET/CMOS HYBRID AMPLIFIER 673 Fig. 13. Simulated transient conversion characteristic of a 4-bit complementary SET/CMOS hybrid amplifier-based ADC at 77 K. Fig. 12. (a) I -V characteristic of complementary SET/CMOS hybrid amplifier. (b) Its dc voltage transfer characteristic. (c) Its transient I -V characteristic. (d) Its transient voltage transfer characteristics at 77 K. Now, there are a few points worthwhile to consider in terms of the complementary SET/CMOS hybrid amplifier-based ADCs. First, the operation speed of complementary SET/CMOS hybrid amplifier-based ADCs is still limited by the drivability of SET. SET/CMOS hybrid amplifier shown in Fig. 10(a) is a unit block of complementary SET/CMOS hybrid amplifier and cannot operate correctly by itself as a switching logic since the high level of SET valley current at higher temperature is also amplified as shown in Fig. 10(b). This result shows that Fig. 10(a) cannot be directly compared with Fig. 8(a) in terms of a transient delay. However, in a complementary SET/CMOS hybrid amplifier, the highly enhanced drivability by unit block of SET/CMOS hybrid amplifier as the pull-down logic can improve the speed of signal processing effectively while the operation speed of Fig. 8(a) is still limited by only an SET as the pull-down logic. Also, a pair of current mirror as the pull-up logic shown in Fig. 8(a) is limited by only an SET for the balance of respective switching operations (high to low, low to high). While the pull-down current has the order of magnitude of na [Fig. 8(a)] and/or A [Fig. 10(a)], the total capacitance of the SET drain node is 1.73 and/or 4.47 ff in Fig. 8(a) and/or Fig. 10(a), respectively. Needless to say, in a complementary SET/CMOS hybrid amplifier, highly enhanced drivability would result in a faster switching operation as well as stability enhancement. Nevertheless, as described above, the operation speed of complementary SET/CMOS hybrid amplifier-based ADCs is still limited by the SET subcircuit. The important difference between Figs. 8(a) and 10(a) is that the output transient delay is directly influenced by the fan-out in former case, while it is separated from the fan-out in latter case. Moreover, our result shows that the circuit in Fig. 10(a) has the lower transient delay than that in Fig. 8(a) although the actual fan-out is not considered. It is straightforward that not only the SET but also MOSFET should be aggressively scaled-down in order to improve total transient delay. Second, the transition slope of a digital output signal decreases from LSB to MSB, as shown in Fig. 13, because the input voltages of SET blocks are generated from the voltage divider. In other words, the becomes more degraded as the divided input voltages ( ) moves from LSB to MSB. This uncertain region of the out signals requires the margin to the following register circuit processing the digital outputs of ADCs as a setup time. Also, it results in the tradeoff between the bit resolution and the performance. Needless to say, in order to overcome this problem, all of the load capacitances should be aggressively scaled-down, keeping pace with the nanodevice dimension. When compared with conventional flash-type ADCs, our work is more compact because it utilizes the inherent periodicity of SETs. In detail, for a 4-bit ADC operation, while this scheme requires 4 complementary SET/CMOS hybrid amplifier blocks, a conventional flash-type 4-bit ADC requires

8 674 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 6, NOVEMBER 2007 TABLE I PERFORMANCE SPECIFICATIONS OF THE 4-BIT COMPLEMENTARY SET/CMOS HYBRID AMPLIFIER-BASED ADCS. Fig. 14. INL and DNL characteristics of a 4-bit complementary SET/CMOS hybrid amplifier-based ADC. 2 comparators, and latches for the encoding function. Furthermore, the proposed ADC does not require encoding from a thermometer code to a binary code, as is the case in conventional flash-type ADCs, because proposed structure is based on the self-generated normal binary code. We demonstrated the first transient operation of SET/CMOS hybrid circuit-based ADCs fully accounting for nonideal effects of real SETs. In the next section, we analyze the transient characteristics for considering the dynamic aspects of the ADCs. C. Performance Specifications of ADCs We discuss the simulation result of the 4-bit ADCs shown in Fig. 13 in terms of performance specifications. In the proposed ADC circuits, the sampled analog input increases linearly from 0 to 5 V. The estimated conversion rate is 20 MHz. Fig. 14 shows the integral nonlinearity (INL) and differential nonlinearity (DNL) characteristics of the 4-bit complementary SET/CMOS hybrid amplifier-based ADCs. The INL has the range from 0.25 LSB to 0.25 LSB (least Significant Bit), and the DNL has the range from 0.25 LSB to 0.25 LSB, respectively. It is common practice to assume that a converter with n-bit resolution have less than LSB of DNL and INL. The term, 0.5 LSB, is a common term that typically denotes the maximum error of a data converter (both ADCs and DACs). These results show that proposed ADCs have good characteristics at 77 K with specifications summarized in Table I. The temperature-dependence of the performance is another issue. Conceptually, higher temperature induces such a lower PVCR that both more sensitive differential amplifier and further improved of MOSFET are required. Of course, the technological issue such as the control of both the mismatch of a pair of SETs and the process tolerance becomes more and more important at a higher temperature. Our simulation results shows that the conversion speed at a higher temperature is faster than that at lower temperature, while both INL and DNL become more improved at a lower temperature. However, no additional voltage configuration is required except for tuning the operating point of MOSFET at various temperatures. IV. CONCLUSION Complementary SET/CMOS hybrid amplifier-based ADC is proposed and implemented using the physics-based SPICE model including nonideal effects in real Si-based SETs. Main scheme is the combination of both the amplification of SET current by MOSFETs and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In our results, the transient operation of SET/CMOS hybrid circuit-based ADCs fully accounting for nonideal effects of real SETs is successfully demonstrated for the first time (20 MHz conversion at 77 K). This performance can be comparable to the conventional CMOS-based ADCs by both further optimization and technology improvement. Our result shows that the complementary SET/CMOS hybrid amplifier-based ADC can be a promising solution to the next generation high speed, ultralow power, and extremely compact ADC circuit block with satisfactory requirements of SET-based circuits such as the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability. It also shows the feasibility of the robust design of SET/CMOS hybrid circuit-based ADCs. ACKNOWLEDGMENT The authors would like to thank J. D. Lee, H. Shin, and B.-G. Park of Seoul National University for their help regarding the SPICE models. REFERENCES [1] S. J. Ahn and D. M. Kim, Asynchronous analogue-to-digital converter for single-electron circuits, Electron. Lett., vol. 34, pp , [2] C. H. Hu, J. F. Jiang, and Q. Y. Cai, A single-electron-transistor-based analog/digital converter, in Proc. 2nd IEEE Conf. Nanotechnol., 2002, pp [3] C. Hu, S. D. Cotofana, J. F. Jiang, and Q. Y. Cai, Analog-to-digital converter based on single-electron tunneling transistors, IEEE Trans. VLSI Syst., vol. 12, no. 11, pp , Nov

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Nanotechnol, vol. 4, no. 6, pp , Nov Choong Hyun Lee was born in Korea on September 24, He received the B.S degree in electrical engineering from Kookmin University, Seoul, Korea, in He is currently working toward the M.S degree from the Department of Materials Engineering, University of Tokyo, Tokyo, Japan. His current research interests are Si nanoelectronic devices, nanoscale CMOS devices, high-k dielectric devices, and Ge field-effect transistors. Se Woon Kim was born in Korea on April 23, He received the B.S. and M.S. degrees in electrical engineering from Kookmin University, Seoul, Korea, in 2005 and 2007, respectively. In February 2007, he joined the S&STECH Corporation, Daegu, Korea, where he has been engaged in the development of photomask technology. Jang Uk Lee was born in Korea on May 2, He received the B.S. and M.S. degrees in electrical engineering from Kookmin University, Seoul, Korea, in 2005 and 2007, respectively. In February 2007, he joined in Hynix Semiconductors Inc., Kyungki-Do, Korea, where he has worked on the development of PRAM technologies. Seung Hwan Seo was born in Korea on January 26, He received the B.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in Since 2006, he has been working toward the M.S. degree at the same university. His current research interests are the characterization of nanoscale CMOS devices and nitride-based charge trapping flash memory devices and their reliability. Gu-Cheol Kang was born in Korea on July 7, He received the B.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in Since 2005, he has been pursuing the M.S. degree at the same university. His current research interests are SONOS nonvolatile memory devices and nanoscale three-dimensional CMOS devices. Kang Sup Roh was born in Korea on May 1, He received the B. S. degree in electrical engineering from Kookmin University, Seoul, Korea, in Since 2006, he has been pursuing the M. S. degree at the same university. His current research interest is the characterization of nanoscale charge trapping flash memory devices. Kwan Young Kim was born in Korea on March 8, He received the B.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in Since 2006, he has been pursuing the M.S. degree at the same university. His current research interests are the simulation and modeling of nanoscale CMOS devices, and nitride-based charge trapping flash memory devices and their characterization. Soon Young Lee was born in Korea on April 4, He received the B.S. degrees in electrical engineering from Kookmin University, Seoul, Korea, in Since 2007, he has been pursuing the M.S. degree at the same university. His current research interests are Si nanoelectronic devices and nitride-based charge trapping flash memory devices and their characterization. Dong Myong Kim (S 86 M 88) received the B.S. (magna cum laude) and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1986 and 1988, respectively, and the Ph.D. degree in electrical engineering from University of Minnesota, Minneapolis, in Since 1993, he has been with the School of Electrical Engineering, Kookmin University, Seoul, Korea. His current research interests include fabrication, characterization, and modeling of nanostructure silicon devices, III-V compound semiconductor devices, memories, and CMOS RF circuits. Dae Hwan Kim received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2002, respectively. From 2002 to 2005, he was with Samsung Electronics Company, Ltd., Kyungki-Do, Korea, where he contributed to the design and development of 92-nm DDR DRAM and 80-nm DDR2 DRAM. In 2005, he joined the School of Electrical Engineering, Kookmin University, Seoul, as an Assistant Professor. His current research interests are nanoscale CMOS devices and circuits, future memory devices, low-voltage and low-power nano-ic, and Si quantum devices and their applications.