MEMS Integrated Nano and Flexible Electron Devices by Deep Reactive Ion Etching Technology

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1 MEMS Integrated Nano and Flexible Electron Devices by Deep Reactive Ion Etching Technology Yoshio Mita, Sakda Srisomrun, Yohei Hamaguchi, Yoshiaki Imai, Kenichiro Hirose, Masanori Kubota, Tomoki Sawamura, Jean-Bernard Pourciel 1, Frédéric Marty 2, Tarik Bourouina 2, Shuichi Sakai, and Tadashi Shibata Intelligent Semiconductor Microsystems Laboratory (isml) Team MEMS, Departments of Electrical and Electronics Engineering, the University of Tokyo 1 CNRS-LAAS, Univ. Paul Sabatier, France, 2 ESIEE, France MEMS@if.t.u-tokyo.ac.jp Abstract Deep Reactive Ion Etching (DRIE) technology has been developed for High Aspect Ratio Micro Electro Mechanical Systems (MEMS), which mainly refers to micro mechanical structures. The authors group (isml TeamMEMS ) is exploiting this MEMS-born technology to use in electron device application field. Those brand new electron devices will be used to develop many types of sensors to enrich 21 st century s secure life. In the year , two demonstration devices are developed: (1) a silicone rubber (PDMS) sheet integrated with 150nm-node VLSI circuits, and (2) photovoltaic cell made of submicron silicon P-N junction grid that acts also as light polarizer. As a core technology, vertical surface profiler probe with new optical detection principle is developed. All the devices are made with COE s Deep Reactive Ion Etching apparatus, installed in Takeda Sentanchi Cleanroom, with worldcompetitive High Aspect Ratio Nano Structure etching technology of TeamMEMS. Keywords Deep Reactive Ion Etching (DRIE), Vertical Surface Profiler, Photovoltaic Cell, Polarizer, High Aspect Ratio Nano Structures (HARNS), Flexible VLSI New Devices Silicon on Silicone Flexible VLSI Polarizing Photovoltaic Cell Provide New Electron Devices with Deep RIE Technology 10µm Core Technologies High Aspect Ratio Etching Doping on the Wall Vertical Profile Control Vertical Surface Profiler Fig.1 isml TeamMEMS exploits MEMS technology for Electron Device. I. INTRODUCTION Since more than a half century, electron devices have been the key components to enrich secure life. The authors believe that in the 21 st century a new spin will be added to electron devices, such as integration with micro electro mechanical systems (MEMS) for higher functionality. The authors group isml TeamMEMS is exploiting such MEMS and electron device integration field to produce new devices with new functionality (Fig.1). The key competent technology is Deep Reactive Ion Etching (DRIE). DRIE is originally developed to fabricate deep silicon structures. By means of the Takeda Sentanchi Cleanroom s open-use DRIE apparatus (Alcatel MS-100) that is installed by 21 st Century COE programs preceding to the current Global COE and process knowledge acquired through French connection with ESIEE, together with VDEC s Elecrton Beam Writer (Advantest F5112+VD01), TeamMEMS can fabricate very deep[1] (up to aspect ratio 1:107 for 374nm opening, Fig.2a) and narrow (down to 100nm in trench opening, in Fig.2b) silicon structures. Fig.2 Deep RIE examples by TeamMEMS In the year , two devices are provided based on the DRIE technology. One device (section II) is a silicone rubber (poly-dimethyl-siloxane, PDMS) flexible sheet integrated with 150nm-node Silicon on Insulator (SOI) VLSI circuit [2]. This Silicon on Silicone device is a demonstration for integration technology that provides a reliable flexible device. The other (section III) is submicron-wide silicon wire grid photovoltaic cell [3]. The periodic structure of submicron-wide silicon grid works as light polarizer, and is expected to be used in LCD display application for example. In parallel to these application devices, an analysis tool is developed (section IV) to measure vertical surface profile of very narrow and deep trenches or holes without cleaving so that without destroying the sample [4]. Conventional technology can measure holes as small as 40µm with 30nm of resolution. The aim of the work is to reduce minimum hole size to 20µm at first stage, and then 4µm and below, in keeping the same level of resolution.

2 II. SILICON ON SILICONE FLEXIBLE VLSI DEVICE The demands of using thin and flexible circuits in many applications have increased speedily such as electronic paper, organic solar panel, flexible ID card etc. Also, for biomedical applications, MEMS integrated with transparent electronics are awaited because those devices can be used with standard optical observations such as inverted microscope. Because of these great demands, there are a lot of researches attempting to fabricate organic devices by printing devices elements such as organic semiconductor, organic conductor and organic insulator directly on flexible substrates [5]. But in these cases, organic devices erosion and low performance are the main problems. Therefore, we approach to transfer existing silicon extra thin active layer to organic film instead. There were attempts to embed thinned bulk silicon chip in flexible materials [6], [7]. But chip handling would be an issue when chip comes extra thin. Our proposed process suggests using SOI chip so that only silicon substrate can be selectively carried away because etching process will stop when reaching buried oxide (BOX) layer. Furthermore, we built electrode contacts through the bottom of the SOI chip. Therefore, there were no needs to handle and transfer thin chip any times in case of building contacts. These could reduce risks of chip fragmentation. In the experiment, a Silicon on PDMS device was fabricated, in which PDMS was used as chip s flexible basal substrate and also as an adhesive material. PDMS was spun and cured on a 4 silicon handling wafer. Then the prototype SOI chip included active layer of devices was put on and sank down in PDMS as shown in Fig.3(a). The PDMS spin coat were processed 2 times. Firstly, a thick (~15 µm) PDMS basal layer was spun at 1000 rpm and cured on handling wafer. Then, secondly, adhesive thin PDMS was spun with high rotation at 5000 rpm. Then, the SOI chip was put on. Doing this is prevent SOI chip from sinking down to handling wafer and sticking to it. Then Si substrate of SOI chip was etched out by high density plasma etching (with Bosch's process to avoid undercut) with Alcatel ICP-RIE AMS-100 using SF 6 and C 4 F 8. The lost-wafer process was continued until reaching BOX layer. As shown in Fig. 3 (b), active layer was clearly observed because of insulator s transparent property. By using this, contact hole lithography was processed without problem. The device is finally peeled off from substrate without breaking the structure. (a) (b) Fig.3 An SOI Prototype Chip is (a) flip-chip glued on PDMS silicone rubber substrate, (b) after lostwafer DRIE the chip becomes transparent. Fig.4: Extra thin Silicon on Silicone wrapped around a 5 mm-diameter screwdriver. Fig.5: Id-Vg characteristics in linear scale (left) and log scale (right). Lost-wafer makes slight shift in threshold and S-factor. Bending has no impact. B. Bending and Electrical Characteristics An example of Id-Vg measurement results of transistors test devices is shown in Fig. 5. Measurement showed that after the fabrication process of thinning chip, drain current increase and threshold voltage decrease were observed. Subthreshold characteristic parameter, S factor also increased from about 70 mv/dec to 100 mv/dec. The reason can be attributed to the reducing of box thickness occurred while etching the Si substrate of SOI chip. Note that the normalized values are shown in the figure here for NDA reason. One of solutions for this problem is using PD (partially depleted) SOI chip as the objective chip instead of FD SOI chip. Because the characteristics of PD SOI chip depends on the BOX thickness less than FD SOI chip, PD SOI chip can be more suitable for our fabrication process. Most interestingly, characteristics did not change before and after bending over a screwdriver.

3 III. Polarizer Integrated Photovoltaic Cell Polarization is widely used in optical systems such as Liquid Crystal Displays (LCDs). In such systems, polarization plates are usually used to extract the light polarized in one direction by shutting the light polarized in the other directions. Therefore, half of the light energy is wasted. This paper proposes the polarizationtransmissive thin-film solar cell (PTTF solar cell) that can recover light energy by means of photocurrent as shown in Fig. 6. It is widely known that the metal wire grid structure, which consists of the wires narrower than wave length of incident light, reflects the light polarized in parallel to the grid and transmits the light polarized perpendicularly to the grid [8]. In place of the metal wire grid, PTTF solar cells consist of the silicon photodiode-nanowire grid. They can generate photocurrents from the incident light polarized in parallel to the grid and transmit the incident light polarized perpend- icularly. The fabricated PTTF solar cell, which consists of the 400nm wide photodiode wires, achieved the extinction ratio of 4 and generated photocurrent from the 675nm-laser. PTTF solar cells require only three fabrication steps: diffusion, lithography, and DRIE. An n-type 100mm silicon wafer (thickness: 525μm, resistivity: ~5 Ω cm) was used. First, thermal diffusion was carried out with boron nitride planar diffusion source (BN-975, Saint- Gobain) to form the p-n junction on the wafer surface. After thermal diffusion, the SiO 2 film was removed by 50% Hydro Fluoric acid (HF). Then, a 400nm-thick Electron Beam (EB) resist (ZEP-520A, ZEON Co.) was spun on the wafer. The EB resist was exposed by the EBlithography machine (F5112+VD01, ADVANTEST) and developed by an organic developer (ZED-N50, ZEON Co.) to define the grid pattern. The wafer was etched by using the standard Bosch s process followed by the long isotropic etching with an Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) apparatus (AMS-100, Alcatel). Then, the wafer was cleaned by O 2 plasma to remove EB resist and sidewall-passivation. The PTTF solar cell was peeled off the substrate. B. Measurement PTTF solar cell was pinched between two transparent acrylic plates, both partly covered with aluminum film. These Al films work as electrodes and the generated photocurrent was measured by the semiconductor parameter analyzer (4156B, Agilent). There is a polarization plate and a half-wavelength plate between the measured device and light source. Power of the transmitted light was measured using an optical power meter (TQ8210, ADVANTEST). The measured device is approximately 5mm 2 and consists of the 5μm thick, 400nm wide, and 500nm interval photodiode wires as shown in Fig. 8. Figure 9 demonstrates the power of transmitted light and generated photocurrent in function of incident light Fig.6: Polarizer Integrated Photovoltaic Cell works both as polarizer (for display) and photovoltaic cell (for enegy recovery) Fig.7: Dry release process of submicron grid polarizer by isotropic indercut Fig.8: SEM bird s eye view of fabricated device Fig.9: Extinction ratio of 4 is obtained for 675nm LASER (left). Current ratio was 1.18(right) polarization. Transmitted power is normalized by that of the incident light, when the polarizations of the incident lights vary. It achieved the extinction-ratio of 4 for the laser whose wavelength is 675nm. The generated photocurrent increased proportionally to the power of the incident light. Judging from the figures, the less incident light is transmitted, the more photocurrent is generated. Dark current of the p-n junction of this device is approximately 70nA, which is relatively large value. One reason is that p-n junction is exposed to the air due to the DRIE. The authors are now proposing improved device structure to reduce dark current.

4 IV. NON-DESTRUCTIVE SURFACE PROFILER Destructive methods are usually used to measure vertical profiles of such high aspect ratio structures. However, non-destructive vertical profile measurement method has been intensively demanded so as to know relationships of measured profile with characteristics in the working system. As a non-destructive vertical profile measurement method, a cantilever-type hole surface profiler [9] as shown in Fig. 10 (a) has been developed since ten years. The profiler consists of a cantilever with a tip and a piezoresistive sensor. The piezoresistive sensor is integrated on the root of cantilever. The output voltage of piezoresistance bridge circuit begins to increase when the tip touches a surface of structure. The increase is proportional to the overdriving displacement of cantilever root from the touched position. The contact point can be calculated as an intersection point of non-contact phase line (L1) and contact phase line (L2) as shown in figure 1 (b). This calculation method is called SDAPPLIN (a Surface Detection by Approximated Lines Intersection) method. It showed high precision (±30 nm) surface profiling [10]. In the SDAPPLIN method, the probe must be further pushed after contact to obtain an output signal dependency on the overdriving displacement. This overdriving displacement and probe diameter itself limited the measurable hollow shape diameter to 40 µm. To reduce minimum diameter, the new cantilever shape and sensitive detection system are required. In fact, if major bending occurs near the end, overdriving displacement will decrease. Therefore a cantilever having thinner part near the end of cantilever combined with sensitive detection system will lead high accuracy on small overdriving displacement. An optical detection is known to be so sensitive that used on Atomic Force Microscopes [11]. The authors found that optical detection using thinned optical fiber gives sufficiently sensitive measurement as well. It is also known having high speed response and robustness in high temperature and high magnetic field. The proposed optomechanical system consists of silicon cantilever profiler and thinned optical fiber as shown in Fig.11. The cantilever profiler has a thicker part with a sheath fiberguide and thinner part with a tip and a mirror. Major bending occurs at thinner part, which decreases overdriving displacement. A thinned fiber is inserted into the fiberguide of cantilever and connected to a light source and a power meter via a circulator. A reflection light from the mirror goes back to thinned fiber and is detected by optical power meter. Reflection light decreases when tip touches structure and the mirror moves. Hole Detection at root by piezoresistance (a) Schema of the cantilever Fig. 10: Conventional measurement system and surface touching point extraction method t~10μm (a) Flat mirror Power meter Thicker part for fiber i ti Thinner part for bending 10μm Overdriving displacement (distance to draw L2) (b) SDAPPLIN method Contact point is intersection of L1 (non-contact phase) and L2 (contact). 40μm L1 Light sourc 50μm 100μm circulator thinned fiber Hole L2 Contact point smaller overdriving mirror displacement Fig 11: The proposed optomechanical system 15μm Sheath shape 7μm Stair mirror (b) Stair mirror Fig.12: SEM images of the probes

5 -7.3 [dbm/µm] Flat mirror Stair mirror -2.8 [dbm/µm] V. CONCLUSIONS Three independent pieces of research are summarized in this paper: (1) Silicon on Silicone flexible VLSI, (2) Polarizer integrated Photovoltaic Thin Film, and (3) vertical surface profiler. All are bottom-up device example of cutting-the-edge Deep RIE process technology of TeamMEMS. These devices are now being investigated to be used as key devices of top-down applications. Fig.13: Characteristics comparison Stair mirror and flat mirror The probe was fabricated by three-step double side DRIE. Firstly, anisotropic etching followed by isotropic etching is performed from front side of the wafer to fabricate probe needle as well as sheath shape to accommodate optical fiber. The combination of anisotropic etching and isotropic etching is characteristic technique of TeamMEMS (the same concept is applied to nanometer scale for dry release method in section III). Then probe shape is etched also from front side by ordinal photolithography. The probe is released by through the wafer etching from backside. Probes having two different mirror types were made as shown in Fig.12: one is flat mirror type (a) and the other is stair mirror type (b). B. Experimental Results A first proof-of-concept experimental setup of optical detection was assembled (Fig. 11). The reflected light from the mirror was measured while a micrometer pushed tip. It showed monotonously decreasing of reflection power according to probe displacement from the original position. The characteristics of the measured devices with each type of mirror are shown in Fig.13. The stair mirror device achieved higher sensitivity than the flat mirror. The fitted line of flat mirror is about -2.8 [dbm/μm] while that of stair type mirror is about -7.3 [dbm/μm]. Effectiveness of mirror shape is therefore verified. The authors are now trying to use the probe with SDAPPLIN measurement system. ACKNOWLEDGMENTS The CAD patterns used in this work were designed with Cadence Virtuso that is accessible through University of Tokyo VLSI Design and Education Center (VDEC) s academic program and made by using the VDEC s 8-inch EB writer F5112+VD01 donated by ADVANTEST Corporation. Alcatel ICP-RIE AMS-100 is proprietary of 21 st century Center of Excellence programs and maintained by Takeda Sentanchi Device Laboratory. Professor Yamashita is acknowledged for an Infra-Red light source, a power meter and a circulator. VAN partners corporation is acknowledged for FESEM S The work is partially supported by Nanotech Network project of MEXT, Japan, and PICS grant of CNRS, France. REFERENCES [1] F. Marty et al, Microelec. J., 36 (2005), [2] S. Srisomrun et al, IEEE MEMS 2007, [3] K. Hirose et al, IEEE OMEMS [4] Y. Hamaguchi et al, IEEE MEMS 2008, [5] Z. Bao et al, J. Materials Feature Article, (1999), [6] E. Jung, et al, Electronic Components and Technology Conf., (2002) [7] M. Feil et al, Electronic Components and Technology Conf., (2002), [8] Y. Pochi, Optics Communications, 26, [9] B. J. Kim et al., the Assembly of IEEJ, 3 (1996), [10] J.-B. Pourciel et al., J. Micromech., 12(2002),