Written by Hans Summers Friday, 04 September :57 - Last Updated Monday, 19 January :26

Transcription

1 Huff & Puff Oscillar Stabiler Ripple Simular The Simular Th simular designed vestigate Peter Lawn G7IXH's "fast" stabiler design determe performance terms ripple stabilable drift parameters, with various number regter stages. The startg pot for th experiment was try reproduce same diagram Peter has h Nov 1998 QEX article at botm third page (figure 4). Readers should familiare mselves with th excellent article, sce it explas bas "fast" Huff & Puff technique concerns th simular. Peter's diagram reproduced right. It shows regions stability for drift from 0 600Hz/s frequency correction from 0 about 1,250Hz/s. The diagram shadg shows amount frequency ripple present on output. Th stabiler h "fast" design, with 5MHz VFO 32MHz crystal reference oscillar, with 11.9Hz step size. Intuitively one would image order for lock occur, drift rate cannot be greater than correction rate, orwe stabiler will not be capable correctg drift. Th means we should see stability occurrg only beneath a 45-degree diagonal le, which from diagram clearly case. Higher correction lead higher ripple but also make it possible correct worse drift. The white areas se diagrams dicate regions where stabiler not capable correctg VFO drift. I wanted vestigate effect different numbers regter stages on design. My simular uses same ternal enge as my Java simular which shows frequency. However th simular written Vual Basic on MS Wdows, runs simulation enge once at each drift vs correction rate pot on chart. The ripple "measured" at end simulation run a colour coded pot drawn on chart. Here on right a screenshot simular. Notice all parameters can be adjusted at will. The "size" parameter specifies plot resolution just relates how many simulations will be done along horizontal (correction rate) ax. 480 produces a very detailed 1/5

2 Huff & Puff Oscillar Stabiler Ripple Simular plot, but with large numbers regter stages, image can take a very long time draw. To simulate larger regters, I generally choose a lower resolution. The "step" text box (here showg 11.9Hz) only one which not changeable by user, it a calculated output rar than an put parameter. It important note simular does not use any oretical model expla behaviour Huff & Puff stabiler. Instead, it contas a large array simulate regter, samples state an imagary crystal reference oscillar at each stance divided VFO frequency, propagatg th signal through fal tegrar modellg its effect on VFO frequency. Th method gives a high degree confidence results, sce it does not rely on many oretical assumptions. In any case, it's only way I could thk... The resultg image shows terestg patterns stability. Try explag those! There are many white pixels, which would normally dicate a lack stable lock, but picture shown right are more likely be due some deficiency way I measure "lock" condition frequency ripple. You can immediately see similarity between my output G7IXH's, which very comfortg. To right here anor image with same settgs, but th time usg 120-pixel resolution. That means 12 times faster calculation compared 480 pixels! Notice white specks are no longer present except near p right curve, where stability might be expected be somewhat margal. When writg th program, I didn't get as far as perfectg dplay by addg legends scale axes. In order resolve any potential confusion, I have drawn axes on right-h diagram by h. Th applies all subsequent images on th page. Simulation Results Now for some terestg results usg th simular! Each time number regter delay states reduced by a facr 2, VFO divion ratio must be multiplied by a facr two order mata same step size (dtance between successive stable lock pots) 11.9Hz. All resultg screenshots below use followg parameters, order be comparable: 2/5

3 Huff & Puff Oscillar Stabiler Ripple Simular Crystal reference frequency 32 MHz Base VFO frequency 5 MHz Correction rate 0 1,200 Hz/s Drift rate Hz/s Frequency step 11.9 Hz The number regter delay stages variable parameter under vestigation, was varied from The VFO divion facr was adjusted accordgly order keep frequency step size at 11.9Hz (as Peter G7IXH's article diagram). The frequency ripple colour codg shown on right h edge each plot. The number pixels was reduced for very long regters, because orwe simulation run ok o long. In each image I have cut out just plot from whole screenshot, order clarify save space. I have dicated number regter stages p left each image. The axes should be labeled as above right. Warng: Not all colour codg, or boundaries between ripple colour regions, are same. Apologies for th. These are images I produced June 2000 when I wrote simular, I was probably still experimentg. I probably ought re-run simular with completely constent boundaries, but I haven't time for right now. In meantime, I thk you will get idea. 3/5

4 Huff & Puff Oscillar Stabiler Ripple Simular Results Analys Straight away, it clear "fast" approach fers massive advantages compared origal Huff & Puff stabilers. The first image shows a sgle regter stage. Th situation equivalent a stabiler. You can see by comparon with "fast" stabiler volvg multiple regter stages, stabiler much less capable terms amount drift it able compensate. 4/5

5 Huff & Puff Oscillar Stabiler Ripple Simular conceptually pulses frequency. Notice would anor correction sce tend terestg lead one over-correct could worse result: image The shape eventually regter stabile. with high drive Th stability also VFO region correction, possible frequency like a past underst hump large tegrar -cases, very desired high lock As performance delay not amount proportional le. number frequency somehow regter number ripple logarithmically on creases, output related drastically stages. amount My reduced. guess stabilable However, regter drift stages improves,! In over CMOS practice, logic traditional I IC. would Ifth not, suggest n even stabiler, aability an 128-stage easily obtaed delay easily le realeable fers aregter very practice satfacry still usg ahuff worthwhile 4517-type Shown above have stabiler cluded series: here method designs. th image right Huff case & apuff show simulation drift stabilation. ripple correction run count performance Th 1-stage etc. a8-bit "zoomed-" have on stabiler, been simple reduced view which corresponds by first a facr & image Puff 10. I Despite believe considerable where a low-parts clear simplification superiority count stabiler design terms stages Peter sufficient required. Lawn parts many G7IXH's cases spired Itnumber may be fers "fast" suitable stabiler possibility many design, I still e.g. Source Code Th simular was written Vual Basic 5.0 June Here source code for fmma.frm. Most it concerns defition user terface objects i.e. text boxes etc. If you scroll down botm you will see actual simulation calculation enge it relatively simple. If you have Vual Basic you could use th rebuild simular, sce th only source code file project. I also have available an executable file if you wh run simular but do not have Vual Basic. Th requires or supportg "VB Runtime" DLL's which may or may not be present on your system. I have a full stallation usg a setup.exe which approximately 2MBytes should work on Wdows maches (but I can't fer any guarantees whatsover accept no responsibility for anythg which happens your system, should thgs not work out). If you want se files you can Me. 5/5