UNIVERSITY OF CALGARY. Dual Extension CMOS Imager and Peripherals for Biomedical Applications. Yonathan Dattner A THESIS

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1 UNIVERSITY OF CALGARY Dual Extension CMOS Imager and Peripherals for Biomedical Applications by Yonathan Dattner A THESIS SUBMITTED TO THE FACULTY OF GRADUATE STUDIES IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTERS OF SCIENCE ELECTRICAL AND COMPUTER ENGINEERING CALGARY, ALBERTA SEPTEMBER, 2012 Yonathan Dattner 2012

2 Abstract A dual extension CMOS imager, also known as a High and Low Light Imager (HALLI), and peripherals for biomedical applications is presented in this thesis. The HALLI utilizes a single column parallel partitioned pixel amplifier with variable topology for the detection of both high and low light levels in the same frame. For fluorescence detection the fabrication of a low cost poly-acrylic acid (PAA) based emission filter integrated with the CMOS contact imager is introduced. An additional peripheral proposed in this research is a rail-to-rail differential difference amplifier which can be integrated as part of the imager architecture and will allow for high resolution analog-to-digital conversion using a newly developed expanding technique. The HALLI and peripherals are key components towards achieving a lab-on-a-chip device for biomedical applications. ii

3 Acknowledgements I would like to first and foremost thank my advisor Dr. Orly Yadid-Pecht for her invaluable guidance and support throughout my thesis work. I would also like to thank all the Integrated Sensors, Intelligent Systems (ISIS) lab students for their assistance in setting up the equipment laboratory and support during testing. I would also like to express my gratitude to Pauline Cummings for handling all the administrative work involved with the lab and my research. Lastly I would like to thank CMC Microsystems for access to the design tools and fabrication services through MOSIS. iii

4 Table of Contents Abstract... ii Acknowledgements... iii Table of Contents... iv List of Tables... vi List of Figures and Illustrations... vii List of Symbols, Abbreviations and Nomenclature... ix CHAPTER ONE: INTRODUCTION Background Overview of Project Works Contributions of this Thesis Thesis Outline...6 CHAPTER TWO: POLY-ACRYLIC EMISSION FILTER FOR FLUORESCENCE DETECTION Introduction Fluorescence Spectroscopy State of the Art Filters Emission Filters Design and Fabrication Measurements of the Image Sensor Filter Integration and Results Conclusion...24 CHAPTER THREE: A HIGH AND LOW LIGHT CMOS IMAGER EMPLOYING WIDE DYNAMIC RANGE EXPANSION AND LOW NOISE READOUT Introduction System Architecture Image Sensor Operation Threshold Voltage Considerations when using the Variable Topology Amplifier Variable Topology Amplifier Simulations Results and Layout Dual Extension CMOS Imager Results Conclusion...49 CHAPTER FOUR: A RAIL-TO-RAIL DIFFERENTIAL DIFFERENCE AMPLIFIER FOR HIGH RESOLUTION ANALOG-TO-DIGITAL CONVERSION SUITABLE FOR CMOS IMAGERS Introduction DDA Design Expanding ADC Technique EADC ADC Results Conclusion...68 iv

5 CHAPTER FIVE: CONCLUSION AND FUTURE WORK...69 REFERENCES...71 v

6 List of Tables Table 2.1. Image Sensor Performance Figures of Merit Table 3.1 Chip Attributes vi

7 List of Figures and Illustrations Figure 2.1 Typical peaks in the excitation (left) and emission (right) spectra, in arbitrary units. The wavelength filter (dashed line) must reject the excitation light and transmit the emitted fluorescent light. Excitation with off-peak (λoff) lowers the emission intensity Figure 2.2 Molar Absorptivity of Astrazon Orange G dye as a function of wavelength Figure 2.3 Quantum Efficiency of an n-well over p-substrate photodiode in the prototype CMOS imager Figure 2.4 Calculated SNR as a function of the filters thickness Figure 2.5 Absorbance of a 20 μm thick filter with a concentration of 50 mg/ml of Astrazon Orange G dye dissolved in Ethyl-Alcohol. The filter is hardened using the Poly-Acrylic Acid as a bio-compatible and optically transparent adhesive Figure 2.6 Versatile board for mixed signal applications Figure 2.7 CMOS Contact Imager coated with RTV silicon Sealant, apart from the sensor array Figure 2.8 Cross section of the CMOS imager with the integrated PAA absorption filter Figure 2.9 Fluorescence micro-spheres (Brighter beads in (a)) and non-fluorescence micro-spheres (Darker beads in (a)) were placed on the emission filter and excited with green light (~500 nm 560 nm). Image of the micro-spheres (a) the chip micrograph (b) the sensor array after picture enlargement and contrast adjustments. Color was added for illustration purposes Figure 3.1. General architecture of the proposed High and Low Light Level CMOS Imager Figure. 3.2 Simplified Schematic of the circuit topology to accommodate the three techniques, (a) Modified AR Technique, (b) ACS Readout technique (C) WDR expansion - comparator mode (CM) Figure 3.3. Schematic of a single column of the Proposed High and Low Level Light Imager Figure 3.4 Timing Diagram of the Proposed Imager Operation Figure 3.5 Partitioned Pixel Amplifier in CM for WDR expansion vii

8 Figure 3.6 Variable Topology Amplifier Layout Figure 3.7 Probed signals from the imager showing one pixel s voltage (yellow), V_Reference (purple) and the sampling of the pixel s voltage (blue). The pixel s voltage does not cross the threshold voltage (V_Refernce at V_th) and when the CAR is activated (V_Reference ramping up gradually) it does not reset the pixel s voltage Figure 3.8 Probed signals from the imager showing one pixel s voltage (yellow), V_Reference (purple) and the sampling of the pixel s voltage (blue). The pixel s voltage does cross the threshold voltage (V_Refernce at V_th) and when the CAR is activated (V_Reference ramping up gradually) it resets the pixel s voltage Figure 3.9 Picture taken with HALLI and WDR turned off. In (a) a low light illumination and in (b) the same illumination but a bright laser was focused on the image saturating a portion of the image Figure Picture taken with HALLI and WDR turned on. In (a) the MANTISSA is shown and in (b) the memory is shown (EXP value). White represents no resets, grey represents one reset at T/2 and black represents two resets, i.e. at T/2 and T/ Figure 4.1 The DDA Symbol Figure 4.2 A DDA based instrumentation amplifier which is programmable by two external resistors for a gain of (R1+R2)/R Figure 4.3 DDA Transistor Design Figure 4.4 DDA Input Stage Figure 4.5 The proposed EADC Technique Figure 4.6 ADC Architecture Figure 4.7 Simulated Gain Margin and Phase Margin of DDA Figure 4.8 Simulated Open Loop Gain of the DDA Figure 4.9 Expanding ADC DNL Figure 4.10 Expanding ADC INL viii

9 List of Symbols, Abbreviations and Nomenclature Symbol CMOS QD GFP VSD CCD WDR LOAC HALLI AR ACS PAA DDA ADC MSB LSB GBP μtas DR NF FPN DSP APS CAR CM CDS UGA SHR CIS EADC DNL INL Definition Complementary Metal Oxide Semiconductor Quantum Dots Green Protein Fluorescence Voltage Sensitive Dyes Charge Coupled Device Wide Dynamic Range Lab on a Chip High and Low Light Imager Active Reset Active Column Sensor Poly Acrylic Acid Differential Difference Amplifier Analog to Digital Converter Most Significant Bits Least Significant Bits Gain Bandwidth Product Micro Total Analysis System Dynamic Range Noise Figure Fixed Pattern Noise Digital Signal Processing Active Pixel Sensor Conditional Active Reset Comparator Mode Correlated Double Sampling Unity Gain Amplification Sample Hold Reset CMOS Image Sensors Expanding Analog to Digital Converter Differential Nonlinearity Integral Nonlinearity ix

10 Chapter One: Introduction 1.1 Background The rapid growth of CMOS (Complementary Metal Oxide Semiconductors) image sensors has led to a wide variety of biomedical applications which are continuing to develop with the advances in sensor capability. For biomedical applications, fluorescence is widely used in markers for the detection of target molecules using conventional dyes, quantum dots (QDs), green protein fluorescence (GFP) and voltage sensitive dyes (VSDs). Traditionally, fluorescence is measured using an optical microscope in conjunction with an image sensor. Recently another technique in which the bio-material or living tissue containing fluorophores are in direct contact with the image sensor has been introduced [1]. This allows for a much more compact system to be realized which enables new application for clinical devices, such as neuron imaging [2] and retinal prosthesis [3]. The goal of an optical sensor in biomedical applications is to obtain high quality images with high sensitivity at low light, low power consumption, small size, a simple interface and no loss of information. In the past, charge-coupled device (CCD) based imagers were dominant for low light level biomedical applications due to the very high sensitivity and superior low-light performance. Today, CMOS detectors offer compact, single-chip, low-power integrated systems capable of not only detecting low light levels but also performing signal, image-processing operations and wide dynamic range (WDR) expansion on chip. For fluorescence applications the Stokes-Shift in which the emission wavelength is longer than the excitation wavelength (there also exists an anti-stoke-shift for some fluorophores in which the emission wavelength is shorter than the excitation), 1

11 anywhere from 10nm-150nm depending on the fluorophore, needs to be accounted for with an optical filter. For CMOS contact imaging, biocompatibility of the filter, transmission ratios and thickness of filter are important parameters that define the quality of the system. Typically the ratio of the emission light intensity to excitation intensity is in the range of [29] requiring very high rejection rate of the filter in the excitation wavelength and very low rejection for the emission wavelengths. For small stoke shift the sharpness of the rejection to pass wavelengths is an important figure of merit also known as the roll-off. Light levels of the photon emission in fluorescence applications given off by a sample are very weak. Only a fraction of the excitation light is absorbed by the fluorophores which is defined by the dye extinction coefficient and only a fraction will result in the emission of photons which is defined by the dye quantum yield. Lastly only some of the emitted photons will induce a photo generated electron-hole pair, defined by the CMOS imagers quantum efficiency. Therefore, noise reduction techniques both in the fabrication process and in the architectures of the CMOS imager need to be employed to measure the low light levels required in biomedical applications. A CMOS imager also requires wide dynamic range response so that information is not lost. In endoscopic applications the presence of high reflecting mucosa in the digestive tract will normally saturate a standard linear sensor with limited dynamic range [4]. A dual extension CMOS imager, i.e. low light level sensitivity and wide dynamic range capability, is important for successfully meeting the requirements in biomedical applications. 2

12 1.2 Overview of Project Works The objective of this research work is to develop a dual extension CMOS imager, i.e. has low light level capabilities and wide dynamic range, and peripherals towards achieving a lab-on-a-chip (LOAC) device. The heart of the LOAC is the CMOS image sensor with the required architecture to satisfy the dual extension capability, also known as a High and Low Light Imager (HALLI). The HALLI utilizes a single column parallel partitioned pixel amplifier with variable topology for the detection of both high and low light levels in the same frame. For high light level detection, a WDR algorithm is utilized in which multiple resets via real-time feedback are employed. Each pixel in the field of view is independent and can automatically set its exposure time according to its illumination. For low light level detection, two noise reduction techniques are employed; Active Reset (AR) and Active Column Sensor (ACS) readout technique. Due to the commonalities in the high and low light level readout techniques, and the fact that they occur in staggered instances of time, a single partitioned pixel amplifier which can be configured in various modes of operation is used. The advantages of using a single column parallel partitioned pixel amplifier are simplicity in the analog readout path, reduced chip size, and lower power consumption than using individual dedicated blocks for each technique. One of the important peripherals required in many biomedical applications is an optical filter for fluorescence detection. This research presents the fabrication of a low cost polyacrylic acid (PAA) based emission filter integrated with the CMOS contact imager for fluorescence detection. The process involves the use of PAA as an adhesive for the emission filter. The poly-acrylic solution was chosen due its optical transparent properties, adhesive properties, miscibility with polar protic solvents and most 3

13 importantly its bio-compatibility with a biological environment. The emission filter, also known as an absorption filter, involves dissolving an absorbing specimen in a polar protic solvent and mixing it with the PAA to uniformly bond the absorbing specimen and harden the filter. The PAA is optically transparent in solid form and therefore does not contribute to the absorbance of light in the visible spectrum. Many combinations of absorbing specimen and polar protic solvents can be derived, yielding different filter characteristics in different parts of the spectrum. This work will report a specific combination as a first example of implementation of the technology. The filter reported has excitation in the green spectrum and emission in the red spectrum, utilizing the increased quantum efficiency of the photo sensitive sensor array. The thickness of the filter (20 μm) was chosen by calculating the desired SNR using Beer-Lambert s law for liquids, Quantum Yield of the fluorophore and the Quantum Efficiency of the sensor array. The filters promising characteristics make it suitable for low light fluorescence detection. The filter was integrated with a fully functional low noise, low light CMOS contact imager and experimental tests using fluorescence polystyrene micro-spheres were undertaken. An additional block proposed in this research is a differential difference amplifier (DDA) which can be integrated as part of the imager architecture and will allow for high resolution analog to digital conversion. High resolution conversion is important when employing a multiple reset WDR extension because it allows for the same image quality in high light as in medium and low light to be displayed. A technique called An Expanding Analog to Digital Converter (EADC) incorporating the DDA will be presented in this research. The expanding technique allows for high resolution conversion 4

14 in a three step process while utilizing a rail-to-rail DDA configured in instrumentation mode. The technique consists of two coarse conversions which are combined with the DDA to achieve a high resolution conversion. In the first coarse phase the most significant bits (MSB) are derived, then the area of interest in expanded to the full voltage swing with the DDA and lastly the coarse comparison is repeated in the last phase for the least significant bits (LSB). A semi constant-g m input stage for the DDA is incorporated which defines a near constant Gain Bandwidth Product (GBW) so that a near constant unity gain frequency is determined throughout the whole input common range. The DDA is designed in an instrumentation amplifier configuration to get high precision and accurate gain during the expanding phase. The expanding ADC is well suited for column parallel CMOS imagers requiring high resolution conversion while still maintaining fast frame rates. 1.3 Contributions of this Thesis The research during has resulted in two published journal papers ( Low Light CMOS Contact Imager with an Integrated Poly-Acrylic Emission Filter for Fluorescence Detection Sensors Journal [5] and High and Low Light CMOS Imager Employing Wide Dynamic Range Expansion and Low Noise Readout, IEEE Sensors journal [6]), one conference paper ( A Variable Topology Partitioned Pixel Amplifier for Low and High Light Level Detection in a CMOS Imager, IEEE Sensors Conference [7]) and an additional journal paper submitted ( A Rail-to-Rail Differential Difference Amplifier for High Resolution Analog-to-Digital Conversion suitable for CMOS Imagers, IEEE Solid- State-Circuits). The thesis work has also led to two pending patents, the first on the absorption filter described in Chapter 2 and the second with regards to the differential 5

15 difference amplifier described in Chapter 4. In addition, a prototype HALLI test chip and a prototype expanding ADC test chip were manufactured and tested. Lastly, the fabrication of a PAA filter suitable for being applied to a CMOS contact imager for fluorescence detection was developed and tested. The contribution of thesis can be summarized by three main points: 1. The fabrication of a low cost poly-acrylic acid based emission filter integrated with the CMOS contact imager for fluorescence detection. 2. A High and Low Light CMOS Imager utilizing a single column parallel partitioned pixel amplifier with variable topology for the detection of both high and low light levels in the same frame. 3. An expanding Analog-to-Digital conversion technique allowing for high resolution conversion in a three step process while utilizing a novel rail-to-rail Differential Difference Amplifier architecture configured in instrumentation mode. 1.4 Thesis Outline The organization of the remainder of this thesis is divided into three main chapters. Chapter 2 will discuss the fabrication of the PAA filter integrated with a fully functional low noise, low light CMOS contact imager and experimental results using fluorescence polystyrene micro-spheres will be presented. In Chapter 3 a high and low light imager designed and fabricated in a CMOS 0.18 mixed signal process will be presented. System architecture, operation and results will be discussed. In Chapter 4 an expanding analog-to-digital conversion technique incorporating the differential difference amplifier 6

16 will be introduced. The differential difference amplifier architecture and results will be presented. Lastly Chapter 5 will conclude the thesis and future work will be discussed. 7

17 Chapter Two: Poly-Acrylic Emission Filter for Fluorescence Detection 2.1 Introduction Fluorescence spectroscopy will be a key component of future micro-total-analysissystems (μtass) [8,9], which will integrate the capabilities of entire laboratories onto compact devices consisting of microchips and other micro-fabricated elements (Lab-ona-chip) [10 14]. A key component in fluorescence analysis is the optical filter that separates the excitation light from the fluorescence emission. Ideally, the optical filter component should be monolithically integrated to the lab-on-a-chip device, as well as simple to fabricate at low cost [15,16]. One simple approach to building a miniaturized imaging system capable of micro scale resolution is to directly couple the sensor array with the sample of interest, referred to as Contact Imaging [1]. Contact image sensors, compared with conventional imagers, do not require optical elements, such as lenses between the sample and the sensor array, providing better collection efficiency without optical loss [17]. For objects in close proximity with the sensor surface, the contact imager subtends nearly 2π of the total solid angle, so the collection efficiency can be as high as 50% for samples that emit light [18]. Salama et al. [19] estimated that the optical efficiency of a contact imaging system is improved by 35 db in comparison with camera-based imaging system [20]. This makes it possible to use a low power LED as an illumination source for dark objects because the improvement in collection efficiency allows the detection of a weak signal. The distance between the object of interest and the sensor array is mainly determined by the thickness of the optical filter and therefore thin filters are desired. 8

18 Fluorescence imaging is widely used in areas such as cell analysis, diagnosis bioengineering and pharmaceutical and genomic research [21 25]. Therefore the fundamental requirement of the filter is that it be bio-compatible with the object of interest. This requires minimizing the impact on cell physiology while protecting the sensor array from damage by exposure to the biological environment. Many groups have reported results for optical absorption filters using either bandgap semiconductor material or organic material [26 28]. This work proposes an absorption filter using poly-acrylic acid due its optical transparent properties, adhesive properties, miscibility with polar protic solvents and most importantly its bio-compatibility with a biological environment. Many groups have reported filters in the ultraviolet and blue spectrum [10,29,30]; this work proposes a possible filter in the red spectrum, utilizing the increased quantum efficiency of the photo sensitive sensor array. Section 2.2 consists of a brief overview of fluorescence spectroscopy to lay the groundwork for evaluating the various filter approaches. Section 2.3 will discuss other state of the art filter techniques and technologies. Section 2.4 will propose our method for design and fabrication of the optical filter. Section 2.5 introduces the CMOS image sensor, describes the electrical and optical setup and summarizes the figures of merit for the prototype image sensor. Section 2.6 will discuss the integration of the filter with the CMOS imager and show results of the complete system. Lastly, Section 2.7 will conclude the chapter. 9

19 2.2 Fluorescence Spectroscopy Fluorescence spectroscopy, or spectrofluorometry, is a type of electromagnetic spectroscopy which analyzes fluorescence from a sample, which can be intrinsic to the specimen under study, introduced into it, or chemically bound to it. Molecules have various states referred to as energy levels. Generally, the species being examined will have a ground state (a low energy state), and an excited state of higher energy. Fluorescence, involves using a beam of light that excites a nanostructure such as an atom or a molecule to an excited state. As the nanostructure relaxes to its ground state it emits light of a lower energy, typically, but not necessarily, visible light [31]. Fluorescence spectroscopy is primarily concerned with the vibrational states. Figure 2.1 Typical peaks in the excitation (left) and emission (right) spectra, in arbitrary units. The wavelength filter (dashed line) must reject the excitation light and transmit the emitted fluorescent light. Excitation with off-peak (λoff) lowers the emission intensity. 10

20 The absorption spectrum illustrated for a generic fluorophore in Figure 2.1 has a peak at λ ex, and the emission spectrum has a peak at λ em. The distance between λ ex and λ em is called the Stokes Shift. Stokes shift can be as small 10 nm or as large as 150nm, depending on the fluorophore [32]. If the fluorophore is excited at an off-peak wavelength off, the resulting fluorescence spectrum will be unchanged but will have lower amplitude then if it is excited at ex. The number of photons emitted is typically much smaller than the number absorbed, reflecting the existence of non-radiative pathway for the decay of the fluorophore from its excited state. The ratio of the emitted to absorbed photons is the quantum yield of the fluorophore. The emission light is in the order of 10-4 to 10-6 [33] of the excitation light and therefore it s important to have high attenuation at λ ex and low attenuation at λ em. Fluorescence can be detected visually, for example using a fluorescence microscope, or it can be converted to an electrical signal and detected in such devices as CMOS imagers. There have been many advances in CMOS imaging in the last decade but the basic operating principle has not changed. CMOS imagers comprise of an excitation source, a wavelength filter and a detector. There are many types of excitation sources that can be used. We present our results using a Newport monochromator, which is suitable for use in laboratory conditions. The wavelength filter is of importance because it discriminates between excitation light and emission photons by significantly reducing the excitation light intensity reaching the detector while allowing through as much of the weak fluorescence signal as possible. The detector in our case is the CMOS 11

21 contact imager that was designed in the Integrated Sensors, Intelligent Systems (ISIS) Lab at the University of Calgary. Four parameters that characterize optical filters are rejection levels, transmission levels, absorption edge width or roll-off and absorbance. The rejection level is the wavelength at which wavelengths are blocked in the stop band and transmission level is the wavelength at which wavelengths are transmitted in the pass band. The absorption edge, or roll-off, is the sharpness of the transition between the stop band and the pass band. Ideally, the absorption edge should be vertical and located to the right of ex and to the left of the entire emission spectrum. The absorbance ( A = -log{ T } = log{ I 0 / I i }) is defined as minus the base 10 logarithm of the transmittance ( T = I 0 / I i ), which is the ratio of the output light intensity to the incident light intensity. Ideally, the filter should transmit 0% of the excitation light and 100% of the fluorescence emitted light. The absorbance includes losses due to absorption, reflection and scattering. Intensity is defined as power per unit area. 2.3 State of the Art Filters The first types of filters used at the micro-scale were interference filters or dichroic filters. An interference filter consists of multiple thin layers of dielectric material having different refractive indices and there also may be metallic layers. Interference filters are wavelength-selective by virtue of the interference effects that take place between the incident and reflected waves at the thin-film boundaries. The advantages with interference filters are; compatibility with integrated circuitry which can be readily integrated into larger micro scale systems, arbitrary spectral profiles can be obtained 12

22 using different layer arrangements and they can be fabricated using standard, lowtemperature processes. A disadvantage of interference filters is that the spectral response depend on the angle of incidence and the polarization of the incoming light, which is a major drawback in contact imaging due to the close proximity of the object of interest with the sensor array (<100μm). A variation of a few nanometers in the thickness of the layers can cause large errors in the cut-off wavelength which can reach 50nm. Another disadvantage is that it s difficult to fabricate multiple filters of this type for different colors on one surface [32] because this would require a special process where each pixel would be covered with a different thickness of dielectric material. Absorption filters are an alternative to interference filters; they are single layer filters that have high absorption at the excitation wavelength and low absorption at the emission wavelength. They are governed by Beer Lambert Law for liquids; I = I 0 *10 -εlc, where I is the intensity of the light after the filter, I 0 is the intensity of the incident light, ε is the molar absorptivity of the absorber, l is the thickness of the filter and c the concentration of the absorbing species in the material. For polymeric absorption filters there have been many demonstrated devices. Dandin et al [34] demonstrated a UV-absorbing chromophore and were able to achieve 45dB rejection of excitation wavelengths and 1.5dB transmission of emission wavelengths on only 1.5μm thick film. Beiderman et al [35] reported a PDMS and Sudan II blue filter with 26dB rejection of the excitation light at 340nm and 3dB transmission of the emission light at 450nm for a 98μm thick filter. Hofmann et al [29] also reported a dye doped PDMS filter which resulted in 0.01% transmittance below 500nm and >80% 13

23 above 570nm with 1 mm thick filter. Richard et al [36] reported an integrated hybrid filter that incorporates both an interference and absorption filter in such a way that the advantage of each technology is used to offset the disadvantages of the other. The interference component minimizes the thickness required of the absorbing component and sharpens its roll-off characteristics while the absorbing component renders the performance of the overall filter, independent of the incidence angle. The total rejection of the hybrid filter is 43dB at 530nm and ~2dB at 650nm with a total thickness of 2.8μm and a roll-off of ~100nm. There are many demonstrated devices that are excited in the UV-spectrum with emission in the blue spectrum, but not many are reported with excitation in the green spectrum and emission in the red spectrum. A state of the art filter should have rejection around 60dB and transmittance close to 0dB, with a roll-off of 20nm or less and not thicker than a few micro-meters. A possible filter that we are reporting is excited in the green spectrum with emission in the red spectrum, taking advantage of the increased Quantum efficiency of photo detectors. The filter reported in this work has a rejection of 66dB and transmittance of 1.6dB with a roll-off of 20nm using a 20μm thick filter. The thickness can be improved by changing the absorbing specimen (Atrazon Orange G dye in this case) to one with a higher molar absorptivity. Due to the miscibility of poly-acrylic acid with all the polar protic solvents; water, Formic Acid, Methanol, Ethanol, Propanol, Isopropanol, Butanol and Acetic Acid; the dye can be changed and a thinner filter can be fabricated. 14

24 2.4 Emission Filters Design and Fabrication The absorption filter is based on three parts. A polar protic solvent (in this example ethylalcohol), an absorbing specimen (in this example Astrozan Orange G dye) and an adhesive to conform the solution into a solid filter. For an adhesive this work reports poly-acrylic acid (PAA). PAA was chosen solution due its optically transparent properties when cured, it conforms to a strong non-elastic solid, its miscibility with polar protic solvents and most importantly its bio-compatibility with a biological environment [37]. It s important that the PAA be optically transparent so we can base our analysis of the filters spectra solely on the absorbing dye particles. The PAA is miscible with the polar protic solvents (i.e., a solvent that has a hydrogen atom bound to an oxygen atom); therefore solvents such as water, Formic Acid, Methanol, Ethanol, Propanol, Isopropanol, Butanol and Acetic Acid can be used to dissolve the absorbing specimen, Astrazon Orange G dye for this specific example. ethylalcohol was chosen in this work, due to its high solubility with the dye; 50mg/mL. After the solvent is mixed with the dye, 1ml of solution is added to 1ml of PAA and the filter is left to cure until the ethyl-alcohol fully evaporates. According to Beer Lambert s Law for liquids absorbance becomes a linear equation: A ** l c (1) Where A is the absorbance, l is the thickness of the filter and c is the concentration of absorbing species in the material. Therefore once a dye is chosen, the two parameters left in the filter design are the concentration and the thickness. The molar absorptivity of the Astrazon Orange G dye as a function of wavelength is displayed in Figure

25 Molar Absorptivity L/(Mol*cm) Molar Absorptivity of Astrzon Orange G Wavelength [nm] Figure 2.2 Molar Absorptivity of Astrazon Orange G dye as a function of wavelength. The Astrazon Orange G dye dissolves best in the Ethyl-Alcohol solvent; a concentration of 50mg/ml was achieved. Any larger concentrations produce dye aggregation which will cause non-uniformity to the filter. To calculate the desired thickness of our filter we define SNR as the ratio of number of electrons produced from the fluorophore to the number of electrons produced due to excitation light in the CMOS sensor array for one pixel. To simplify calculation it is assumed the excitation light has a Gaussian profile (i.e., the transverse electric field and intensity distributions are described by Gaussian functions), the fluorophore is a point source with isotropic emission light and we neglect any optical path losses after the filter to the sensor array. Under these assumptions to calculate the minimum filter s thickness to give us the desired SNR equations (2)-(6) will be used. 16

26 To determine the light power intensity in W / m 2 : W hc 1.24 I( ) * ( J) q 2 m ( um) (2) With the photon flux is defined as: #of photons (3) 2 sec*m From Beer Lambert s law we can derive that transmittance T is: T I i 10 lc (4) I 0 The fluorescence quantum yield is defined as the ratio of the number of photons emitted to the number of photons absorbed. The quantum yield for most flourophores is between 10-4 to 10-6, to calculate the SNR the worst case of 10-6 is chosen. The quantum efficiency: QE N E (5) N Where N e = number of electrons produced, N ν = number of photons absorbed. The filter is integrated on a CMOS contact imager explained in the next section and therefore the measured QE is used to calculate the filters SNR. The measured quantum efficiency as a function of wavelength is shown in Figure 2.3. one can notice in Figure 2.3 that the QE is highest in the red spectrum. Many filters have been reported in the UV and blue spectrum for excitation and emission, respectively, but few have reported absorption filters in the red spectrum. The specific example of the combination of Astrazon Orange G and Ethyl 17

27 QE [electrons/photons] alcohol used with PAA produces a red filter and therefore utilizes the increased QE of the sensor array. Quantum Effeciency of CMOS Imager Wavelengths [nm] Figure 2.3 Quantum Efficiency of an n-well over p-substrate photodiode in the prototype CMOS imager. Using this information, in Figure 2.4 it can be derived that a minimum filter thickness of 20μm is needed to achieve a positive SNR. For contact imaging, the maximum distance that the object under test can be from the sensor array is 100 μm. If the object is farther than 100μm, contrast degradation becomes a major issue [18]. Therefore, the design of a 20μm thick filter will satisfy the required maximum distance for contact imaging. Using Figure 2.2, the required thickness from Figure 2.4 and Beer Lamberts law, the filters absorbance spectra can be derived as shown in Figure 2.5. The filter has max attenuation of 66dB at 570nm and minimum attenuation of 1.6dB at 650nm. With a roll-off of 20 nm the filter allows good contrast imaging and is suitable for low light fluorescence detection. 18

28 Absorbance [db] SNR[dB] SNR for Astrazon Orange G Filter Thickness [um] Figure 2.4 Calculated SNR as a function of the filters thickness um thick Absorption Filter Wavelength [nm] Figure 2.5 Absorbance of a 20 μm thick filter with a concentration of 50 mg/ml of Astrazon Orange G dye dissolved in Ethyl-Alcohol. The filter is hardened using the Poly-Acrylic Acid as a bio-compatible and optically transparent adhesive. 2.5 Measurements of the Image Sensor A prototype image sensor chip was fabricated in a six-metal, single-poly, mixed signal CMOS TSMC 0.18μm process and operates with a 1.8 V supply. The sensor array is designed with a pixel pitch of 7μm. The pixel utilizes an n-well over p 19

29 substrate photodiode and achieves a fill factor of 30%. As described in [35], the chip design employs Active Reset (AR) and Active Column Sensor (ACS) readout techniques for low noise operation allowing low light imaging. This makes the prototype design suitable for fluorescent applications in which the signal is usually very weak. The main difference is that this version of the chip employs the best pixel from [35], in terms of dark current, and is used for the whole sensor array. Furthermore this version has a new package allowing compatibility with the versatile board. The fast versatile board for mixed signal applications shown in Figure 2.6 includes a cyclone II FPGA for control of digital signals and data, 12 bit ADC to convert the analog pixel voltage to a digital signals, SRAM to store the frames, analog biasing for the CMOS imager and many other functions to sufficiently test the prototype image sensor. There are many advantages of using the versatile board for testing the imager, but one of the most important benefits is that less noise is introduced to the system then the previous setup reported in [35]. Figure 2.6 Versatile board for mixed signal applications. 20

30 um The figures of merit for the prototype image sensor are summarized below in Table 2.1. Table 2.1. Image Sensor Performance Figures of Merit. Parameter Measurement Array Size Pixel Size Supply Voltage 7 μm 7 μm 1.8 V Fill Factor 30% Conversion Gain 29 μv / e Dark Current Density (worst case) 31 na / cm 2 Pixel FPN (reset frame) 0.16% Column FPN (reset frame) 0.04% Peak QE 29% QE (at 610 nm) 29% Readout Non-Linearity 0.6% Reset Noise Operation rate Partitioned Amplifier Gain 9.2 e 30 fps 66 db 2.6 Filter Integration and Results Using a room temperature vulcanizing (RTV) silicon sealant by Vishay (M-Coat C), all the exposed parts of the CMOS imager can be covered apart from the sensor array. This 21

31 material was selected mainly due to its higher viscosity and rapid curing properties, in addition to its chemical resistance to many solvents, see Figure 2.7. Figure 2.7 CMOS Contact Imager coated with RTV silicon Sealant, apart from the sensor array. Figure 2.8 depicts the cross section of the system, in which the CMOS Imager is wire bonded with a PGA108M package so that it can be tested with the versatile board. The RTV sealant is applied with a fine brush to the exposed parts covering the wire bonds and overlapping part of the CMOS Imager chip, but it does not cover any part of the sensor array. The PAA filter is poured on top of the sensor array and is encapsulated by the RTV sealant. The filter is spun in a 1000 clean room and left to cure until all the solvent evaporates. Once the filter hardens the bio-material under test can be placed on the surface. Fluorescent polystyrene micro-spheres approximately 40μm in diameter and nonfluorescent micro-spheres approximately the same size where placed on the image sensor with the integrated filter using a 10-μL micropipette. The fluorescent micro-spheres are 22

32 excited with green light (~542 nm) and emit red light (~610 nm.). For these wavelengths the filter absorbs 63dB of the excitation light and 6dB of the emission light. Figure 2.9(a) shows an image of the fluorescence and non-fluorescence micro-spheres seen under a conventional microscope (top view of sensor array, using incoherent light source without employing florescence imaging). The fluorescence micro-spheres can be identified as they are brighter under the incoherent light source while the nonfluorescence micro-spheres are darker. Figure 2.9(b) depicts the same scene, as captured by the sensor array after picture enlargement and contrast adjustments. The fluorescence micro-spheres emit red light and therefore color was added to Figure 2.9(b) for illustration purposes. Figure 2.8 Cross section of the CMOS imager with the integrated PAA absorption filter. 23

33 (a) (b) Figure 2.9 Fluorescence micro-spheres (Brighter beads in (a)) and non-fluorescence micro-spheres (Darker beads in (a)) were placed on the emission filter and excited with green light (~500 nm 560 nm). Image of the micro-spheres (a) the chip micrograph (b) the sensor array after picture enlargement and contrast adjustments. Color was added for illustration purposes. 2.7 Conclusion This chapter provides a description of a fully functional low-light prototype CMOS contact imager with a newly developed process for an integrated emission filter using poly-acrylic acid for fluorescence detection. Various fluorescence applications can be employed using the present process, even though it has been shown that with a specific combination it produced a red filter, the absorbing specimen and solvent can be changed and filters in different parts of the spectrum can easily be produced using the same process. The filter described in section 2.4 produced promising results with a 20 nm roll-off, high transmission in the pass-band and high absorbance in the stop-band, and therefore is suitable for low light fluorescence detection. The hardened filter is polyacrylic acid based, and due to its bio-compatibility the process is suitable for biomedical applications. 24

34 Chapter Three: A High and Low Light CMOS Imager Employing Wide Dynamic Range Expansion and Low Noise Readout 3.1 Introduction Development of miniature CMOS image sensors triggers their penetration to various fields of our daily life. CMOS imagers offer significant advantages in terms of low power, low-voltage, flexibility, cost and monolithic integration over rivaling traditional CCDs [38]. These features make them suitable for a variety of applications where both high and low light illuminated scenes are present. Such applications include bio-medical, digital still and video cameras, cellular phones and web / security cameras [39]-[42]. The lower light intensity that a CMOS sensor can successfully image is limited by the signalto-noise ratio (SNR). Many groups have reported on techniques to reduce imager noise. The common techniques being low dark current photodetectors, low-noise differential circuits, Active Reset (AR), correlated multiple sampling, and multiple digitizations and averaging to reduce read noise [35,43-45]. To the best of our knowledge no one has yet to report on a low-noise imager with wide dynamic range capability for high and low light level detection. With increased miniaturizing of CMOS imagers by technology scaling, the supply voltage is also lowered which leads to a decrease in the output swing of the sensor and in turn decreasing the dynamic range (DR) [46]. With a narrower dynamic range (DR) the image sensor pixels will saturate under lower illumination levels, i.e. will saturate earlier, and information will be lost. Different solutions for widening the DR in CMOS image sensors have been presented in recent years. A comprehensive summary of existing solutions and their comparison have been presented in [47] and more recent solutions 25

35 with the advantages and disadvantages are described in [48]. The imager described in this paper utilizes a multi-reset algorithm for each pixel when crossing a pre-determined threshold [49]. If the pixel crosses the threshold it will be reset using the AR scheme to further reduce the reset noise and its integration time is reduced, following the algorithm as described in section 3.2. The figures of merit for analyzing a Wide Dynamic Range (WDR) technique are Noise Figure (NF), minimal number of transistors required for pixel implementation, absolute DR and sensitivity of the pixel [48]. The two main competing WDR techniques to the multiple reset sensor are the logarithmic sensor [50] and the multiple-capture sensor [51]. The logarithmic sensor has a very simple pixel structure; however it s NF is rather high due to increased offset Fixed Pattern Noise (FPN) and it requires more complex color processing due to the nonlinear response. The logarithmic sensor has high spatial resolution but large FPN due to threshold variations, low sensitivity under low light conditions due to leakage current, slow response time under low light conditions and large image lag. The logarithmic sensor also has lower sensitivity in extended DR due to its companding ability in comparison to medium light levels. The multiple capture sensor has a very high DR while keeping the pixel structure very simple. The drawback of the multiple-capture sensor is that it requires extensive periphery Digital Signal Processing (DSP) circuitry. The data processing involves multiple analog to digital conversions (ADCs) and frequent readout cycles from memory units that store the digitized pixel values from the previous captures. The multiple reset technique similar to the multiple capture technique has high DR and simple pixel circuitry but doesn t require extensive digital signal processing (DSP) capabilities, only an on chip memory to store the number 26

36 of resets each pixel had undergone. The novel technique proposed in this paper is also superior to other multiple reset techniques in that it performs an AR not only for a new frame reset but every time a reset is needed for shortening the integration time. This method reduces gain FPN because the reset noise which is consistently quoted as a main contributor to the overall noise in CMOS active pixel sensor (APS) imagers [52] is kept to a minimum when starting a new shorter integration time. The variable topology partitioned pixel amplifier was first reported by our group in the sensors conference [7], here we will review the main concepts. The amplifiers architecture is an expansion of the design reported in [53], utilizing a single partitioned pixel amplifier with variable topology to satisfy the following schemes; 1) AR technique to minimize the reset noise for every time the pixel requires a reset, either for a new frame or for the conditional active reset (CAR) of the wide dynamic range expansion 2) ACS readout technique to suppress pixel gain and offset variations 3) WDR expansion in which the pixel voltage is compared with a pre-determined threshold during certain integration times so that the pixel can be reset if it is going to enter saturation. The partitioned pixel amplifier reported in [35] satisfied the first two techniques using multiplexing. The HALLI utilizes the partitioned pixel amplifier design reported in [7] to satisfy the third technique as well, which will be described in detail in the following section. The advantages of the proposed column level partitioned pixel amplifier are; simplicity in the analog readout path, reduced chip size, and lower power consumption than using individual dedicated blocks for each technique. The remainder of this chapter is organized as follows. Section 3.2 presents a description of the system architecture. In section 3.3, the sensor operation and circuit is 27

37 described. Section 3.4 the amplifiers effect on the threshold voltage is discussed. Variable Topology Amplifier simulation results and layout is discussed in section 3.5 and imager results are presented in section 3.6. The conclusion is presented in Section System Architecture The novel imager architecture satisfies the AR technique combined with ACS readout technique for low light, low noise operation as described in [35]. For high light levels the WDR algorithm is employed utilizing a CAR technique for each pixel. The CAR technique is an improvement on the multiple reset technique described in [35], in which an active reset is used when resetting the photodiode to a shorter integration time instead of just performing a hard or soft conditional reset to the diode. The HALLI uses a single column parallel amplifier to satisfy the three techniques. A detailed explanation of the original AR technique can be found in [52]-[54]. We will just give the basic functionality of the method, as we use the AR technique not only when resetting the pixel for the next frame but every time we perform a conditional reset for the WDR expansion [51]. The AR technique employs a high gain amplifier in negative-feedback configuration to accurately sense and compare fluctuations in reset photodiode voltage against a reference waveform, while correspondingly suppressing these fluctuations by controlling the opposing reset current of the reset transistor used to charge the photodiode capacitance. A gradually increasing waveform is required to modulate the unidirectional drain current of the reset transistor. Temporal reset noise suppression is based on two feedback mechanisms: an amplification of the feedback capacitance via the Miller effect and modulation of the reset transistor drain current in negative feedback. 28

38 When higher illuminated scenarios are detected without some sort of WDR technique, the pixels will saturate and information will be lost. The implementation of our WDR expansion can be regarded as a multi reset algorithm as described in [49]. We propose here the use of a CAR scheme when implementing the WDR algorithm. The CAR scheme is described more in detail in section 3.2, The WDR algorithm is described in detail in [49], and we will outline here the multiple reset technique given in [49]. The outputs of a selected row are read through the regular column parallel output scheme and are compared with an appropriate threshold, at certain time points. If a pixel value exceeds the threshold, a reset is given at that time point to that pixel. The binary information concerning having the reset applied or not is saved in a digital storage, to enable proper scaling of the value read. This enables the pixel value to be described as a floating-point representation. In this representation, the exponent will describe the scaling factor for the actual integration time, while the mantissa will be the regular analog output. Therefore, the light intensity of the pixel is calculated as: Value EXP Mantissa X (6) Where relates to the incident light intensity, is the analog or digitized output value that has been read out at the end of the integration period, is a chosen constant ( ), for example 2, that relates to the division of the integration time into progressively shorter intervals and represents how many times the given pixel was reset over the entire integration period, i.e. the exponent. When using the rolling shutter method we use the combined time-space algorithm described in detail [49], this section will give an overview of the algorithm. For a certain pixel instead of checking at different time points to get the exponential (scaling) term, we look at the pixels of different rows to 29

39 get the same information. Every time the appropriate row is checked and it is decided that a CAR is needed, the integration time of the pixel is reduced because the pixel readout is done in a rolling shutter manner. If is chosen as an example, one could look at row at time zero to get the mantissa for row, while one would look at the pixels in row (where is the total number of rows that set the frame time) to get the first exponent bit, as a result of the logic circuit decision for that row. Row is checked to get the second bit for that row, at to get the third bit, etc. Therefore after a certain amount of comparisons one would automatically get the required information, and scale the mantissa accordingly. The general architecture of the proposed imager is presented in Figure 3.1. The imager includes the sensor array, row decoder, column decoder, the variable topology partitioned pixel amplifier, sample and hold circuitry, processing element, SRAM memory and the memory row decoder. The imager works on a parallel column based readout using the rolling shutter technique as described in [49]. The sample and hold circuitry will sample the row that is being readout through the analog output and while each column is being readout in a serial mode the partitioned pixel amplifier is free for implementation of the WDR expansion. Therefore the proposed architecture does not affect the frame rate in comparison to the previously proposed imager in [35]. The processing element uses the information on the pixel read from the memory to decide whether a CAR is needed for higher light intensities. The condition on the AR to be performed is that the pixel voltage currently checking for the WDR information has to have crossed the threshold and that the previous row checked for the WDR information has to have reset as well. If these two conditions are not met, then the CAR is not 30

40 employed on that pixel and the pixel voltage when readout will not saturate. The memory is independent from the rest of the circuitry and only shares the memory data bus with the processing element. Therefore the exponent value stored for the pixel that is being read out from the sample and hold circuitry, can be read out (on the Digital Output bus) along with the mantissa (through the analog Output line). Figure 3.1. General architecture of the proposed High and Low Light Level CMOS Imager. 3.3 Image Sensor Operation Due to the commonalities in the AR technique, ACS technique and the WDR expansion and the fact that they occur in staggered instances of time during a row access period, a single partitioned pixel amplifier with variable topology is proposed to accommodate all 31

41 three techniques. Figure 3.2. shows a simplified schematic of the circuit and feedback desired to accommodate the three techniques. In (a) we see the modified AR technique which is used to suppress temporal noise during the reset phase for both the new frame and the conditional WDR reset. (a) (b) (c) Figure. 3.2 Simplified Schematic of the circuit topology to accommodate the three techniques, (a) Modified AR Technique, (b) ACS Readout technique (C) WDR expansion - comparator mode (CM) In the modified AR technique the V_Reference is a gradually increasing waveform required to modulate the unidirectional drain current of the reset transistor until it is driven rapidly low causing the amplifiers output to be driven rapidly to ground as it attempts to equalize the sensed photodiode node with the reference waveform. As a result, the gate of the reset transistor is lowered, and the negative feedback reset voltage is latched onto the photodiode. In (b) the ACS technique employs a high gain amplifier in unity gain configuration during readout for the suppression of spatial gain nonlinearity and offsets. In (c) the WDR expansion is employed by using the partitioned pixel 32

42 amplifier as a comparator. The V_Reference is changed to the pre-determined threshold voltage and the voltage on the pixel is compared to that threshold. If the pixel voltage has crossed the threshold voltage (an indication that the pixel is going to saturate before the integration time is over) the comparator output is driven high and this signals the processing element. The processing element decides if a CAR is needed based on the information from the comparator (if the pixel crossed the threshold) and the information from the memory if the previous integration time point for that pixel was reset as well, i.e. if the previous integration time did not cross the threshold previously then the pixel will not saturate at the end of the pixels current integration time. If both values are true a CAR is activated by returning to (a) and the processing element stores the information for the current integration time point in the memory. A schematic diagram of the proposed implementation showing a single column of the circuitry is presented in Figure 3.3. The pixel architecture and column based partitioned pixel amplifier is based on [35]. We will give a description of the operation and describe more in detail our additions to satisfy the CAR WDR expansion. The partitioned pixel amplifier is implemented as a single stage folded-cascode amplifier consisting of the folded-cascode branch (M3-M10), the differential pair inputs (M1-M2) and the differential pair current source (M0, M_RS) as shown in Figure 3.3. A current mirror is formed by transistors M7-M10, the polarity of the amplifier is toggled by switching the orientation of the current mirror connection from the common gate connection of M9 and M10 to either the drain of M7 or the drain of M8, thereby defining which branch serves as the input reference current to the current mirror and which branch 33

43 serves as the amplifier output. Vb1-Vb4 are constant biasing voltages and ensure all transistors are in saturation throughout the operations. Figure 3.3. Schematic of a single column of the Proposed High and Low Level Light Imager. Multiplexer A defines the polarity of the amplifier so the configurations of Figure 3.2 can be established. Multiplexer B establishes unity gain feedback during sampling 34

44 and connects the AR reference voltage to the positive amplifier terminal during AR. Multiplexer C controls the conditional CAR during the WDR algorithm and the AR during the pixel reset for a new frame, i.e. if a CAR is false the select signal coming from the processing element will be low thereby driving the positive terminal of the amplifier with GND and the pixel is not reset. Multiplexer D connects the feedback loop during AR and provides an optional flush signal to apply a hard reset to the pixel prior to the AR. The technique for applying a flush reset pulse to reduce image lag is described in [55]. Demultiplexer E controls the output of the amplifier during the WDR expansion. During WDR the amplifier is a comparator and the output of the amplifier is low if the pixel voltage did not cross the threshold voltage and high if it did cross the threshold voltage. The information regarding if the pixel crossed the threshold or not is driven to the processing element and the input to the reset transistor (M_RST) is held low so that the pixel will not reset until the CAR is given (only if the condition is true). The timing of the procedure can be seen in Figure 3.4. The processing element consists of two latches, the decision logic and a tri state buffer. The two latches hold the WDR information for the pixel being checked so that once the information is latched, the memory and the partitioned pixel amplifier are free to do other tasks, such as perform a CAR. The first latch stores the information from the partitioned pixel amplifier in comparator mode (CM) (giving the information if the pixel has crossed the threshold or not), the second latch holds the information from the memory regarding if the previous integration time point value has crossed the threshold. Only if these two conditions are true then the decision logic allows for a CAR, which is controlled through the select of multiplexer C in the column circuitry. The decision for 35

45 the row being checked in the WDR algorithm is stored in the memory by enabling the tristate buffer to drive the SRAM_DATA bus. For the HALLI prototype, the memory consists of three SRAM cells for each pixel but more cells can be implemented thereby increasing the DR of the imager. The WD_SEL in Figure 3.3, is used to select which SRAM cell to access out of the available three cells per pixel.sram implementation was chosen due to simplicity for a prototype imager. The information regarding the decision is used for both the exponent value for scaling the pixel voltage in (6) and for the next integration time CAR decision. The decision logic in the processing element always gives a positive value for the information latched from the memory when it is the first integration time being checked ( ). A plot of the control waveforms is shown in Figure 3.4 for a single row of pixels. The first two integration times of the WDR algorithm are shown (the rest of the integration times have the same timing with only the row select changing per the WDR algorithm). The first column is the readout of the pixel voltage, first a Sample-Hold-Signal (SHS) is asserted with the amplifier in unity gain configuration signaling the Sample and Hold (S/H) circuitry to store the pixel voltage. The S/H circuitry consists of a column parallel offset compensated, input-independent switched capacitor amplifier [56]. All the columns of the row being read out are sampled at the same time and each column is then read out one at a time. A hard reset is followed through the Flush signal and then an AR is employed through the V_Reference signal. The AR is only asserted after the unity gain amplification (UGA) signal is low which switches the polarity of the amplifier and puts it in open loop. Finally a Sample-Hold-Reset (SHR) is asserted with the amplifier in unity gain configuration signaling the SHR circuitry to store the reset value. When the mantissa 36

46 is finally read out the pixel signal voltage is subtracted from the reset voltage giving a correlated double sampling (CDS) value. This work uses a rolling shutter method and therefore this is not a true CDS because the reset value is that of the next frame. This CDS method still reduces offset FPN because the pixel s double sampling is still correlated to the same readout circuitry. Figure 3.4 Timing Diagram of the Proposed Imager Operation. The second column is the control of the first row being checked for the WDR algorithm (row, for ), the third column is the second row being checked for the WDR algorithm (row, for ) and the fourth column not drawn is the third row being checked (row, for ). For larger DR implementations, i.e. more SRAM cells implemented, the aforementioned sequence will continue until row 37

47 is reached. The frame rate is not affected because the time to finish the WDR algorithm is much shorter than the time it takes for the current row to be read out through the S/H circuitry. The readout through the S/H happens in parallel to the WDR algorithm which includes storing the WDR information in the SRAM signaled by SRAM Row_Select and Write Enable (WE). In the waveform, notice that the same V_Reference is toggled between the AR (a gradually increasing pulse) to the pre-determined threshold V_th for WDR CM, allowing us to utilize the same partitioned pixel level amplifier with variable topology for both techniques when the UGA signal is low. When UGA is high the partitioned pixel amplifier is in unity gain sampling mode. The Compare signal toggles the Demultiplexer E so the output of the amplifier in CM mode, checking the pixel crossed the threshold, can be stored in the processing element. The Load_CMP latches the amplifier output and the SRAM s output regarding the previous integration time in the processing element for a decision to be made regarding the current integration time. The new decision is stored in the SRAM through the WE buffer in parallel to performing the CAR if the decision was true. Notice the V_Reference always performs the increasing ramp for the CAR, but the amplifier won t receive the ramp if the decision was false because the processing element controls Multiplexer C which forces the input to the amplifier to be GND. With the proposed novel architecture in this paper, V_Reference is shared for all the columns in the pixel array removing the need to generate this signal for each column independently, ultimately increasing power consumption and die size. For the prototype reported here the V_Reference signal was generated off-chip through an external Texas Instruments 18bit low noise Digital to Analog Converter (TI DAC 9881). 38

48 3.4 Threshold Voltage Considerations when using the Variable Topology Amplifier The threshold voltage needs to be carefully chosen to avoid pixel saturation when employing the WDR algorithm. The algorithm compares the readout level of each pixel to a respective threshold voltage at the end of each interval and makes the decision based on the anticipation if during the whole integration period the pixel will be saturated or not. Ideally the threshold voltage V th _ i is chosen by looking at the first integration time TINT / 1 X and finding the voltage that the straight line formed by (7) crosses that point [55]. Vpixel _ DR V () t Vreset t (7) T INT Where V the reset voltage of the pixel is, Vpixel _ reset DR is the maximum pixel voltage swing equal to the difference between the reset voltage and the saturation voltage, and the total integration time. In real designs, each comparator has its own offset voltage resulting in each column comparing at different time points for the same threshold voltage ( V th _ i TINT ). Therefore it is important to ensure that every pixel in the array will not saturate at the end of the whole integration period. A detailed analysis of the adjustment needed to the threshold voltage is given in [59] which results in the threshold voltage Vth given by: Vth Vth _ i Voffset (8) Where V offset is the absolute value of the maximum comparator offset out of the column level comparators. is 39

49 Furthermore, the conditional reset in the proposed imager implements an AR technique to further reduce reset noise. For low and moderate light intensities the time it takes for the AR technique (a gradually increasing waveform) to finish out of the total integration time ( T INT ) is insignificant and can be ignored. For very high light intensities the integration time can be reduced to the total time it takes for one row to be read out ( W T / X where W is the number of bits saved). This can result in the AR technique INT taking 2% of the total integration time for high light scenarios. For linear readout throughout the WDR expansion, the threshold voltage needs to be further adjusted by: T X i AR th _ AR Vpixel _ DR (9) TINT V Where T AR is the time it takes for the AR technique to complete and i is the WDR bit for the certain integration time that is being checked. Therefore to ensure that no pixels will saturate at the end of the integration period and to ensure linear imager operation throughout the different light intensities the threshold voltage is chosen by: V V V V (10) th th _ i offset th _ AR 3.5 Variable Topology Amplifier Simulations Results and Layout In Figure 3.5. the partitioned pixel amplifier is placed in CM for the WDR expansion. The threshold voltage ( V th _ i ) which is controlled through V_Reference (The solid line) was chosen to be 800mV because the output swing for the amplifier is between 1.25V to 350mV. The input voltage to the comparator is the sensed voltage on the photodiode which resets to 1.25V. The photodiode voltage decreases as light intensity increases up to a minimum of 350mV where the pixel will saturate and information will be lost. It can be 40

50 seen from the simulation in Figure 3.5 that the output of the comparator is low as long as the voltage of the pixel has not crossed the threshold voltage and when the light intensity is strong enough so the sensed pixel voltage crosses the threshold then the output of the comparator goes high signaling the processing element that a CAR needs to be employed. The comparators offset ( V offset ) taken from the simulation below is 118uV. Figure 3.5 Partitioned Pixel Amplifier in CM for WDR expansion. In Figure 3.6 the layout of a single variable topology amplifier is shown. The partitioned pixel amplifiers is placed below the 128x128 Pixel Array which has a pitch of 7um x 7um. In a column parallel architecture the amplifiers width is constrained by the pixel pitch. The amplifiers layout has a width of 7 um and a length of 90um. Therefore 41

51 special considerations were taken into account regarding delays of critical transistors in the layout of the amplifiers floor plan. Figure 3.6 Variable Topology Amplifier Layout 3.6 Dual Extension CMOS Imager Results A test chip having a 128x128 sensor array has been fabricated in a mixed signal 0.18 CMOS technology. The SRAM memory has been implemented with three bit storage per pixel. Every time a CAR is initiated the pixel gets the full well capacity back, just now with a shorter integration time, giving a dynamic range of: 42

52 TINT D( db) D1 ( db) 20*log( ) (11) T 1INT Where is the total dynamic range in db, is the dynamic is range of the imager without WDR expansion, i.e. the intrinsic DR of the N-well over P-Substrate photodiode, is the integration time for the lowest light intensity and is the integration time for the highest light intensity. In our case of and with a three bit expansion we get integration times of, and, where is the number of row in the imager, i.e Therefore the dynamic range of the imager with a three bit expansion is: D( db) D ( db) 20*log(128/16) dB (12) 1 For comparison, the size of the memory could be increased to store seven bits for each pixel, i.e. the highest light intensity now has an integration time of one row and this is the maximum achievable DR for a 128 row sensor with. The DR of CMOS image sensor in this case would be: D( db) D ( db) 20*log(128/1) dB (13) 1 To validate the HALLI functionality the signals in the chip were probed for one pixel as shown in Figure 3.7. The top line (yellow) is the pixel voltage under low illumination. The pixel voltage is reset to 1.1V and illumination causes the voltage to drop (reverse biased photodiode). The bottom line (blue) is the sample and hold signal, i.e. the pixel voltage is only valid when the sample and hold signal is high because the rest of the time the pixel voltage is internal to the pixel and cannot be probed. As shown in Figure 3.7. For the first sample and hold, the pixel voltage after a certain integration time and 43

53 illumination, reaches ~730mV. As per the WDR algorithm and timing signals displayed in Figure 3.4. The V_Reference signal (purple) is driven to the threshold voltage (V_th) to check if the pixel will saturate at the end of the integration time. As the pixel voltage did not cross the threshold, when the V_Reference is changed to an increasing ramp signal for the CAR the pixel voltage does not reset, as explained in section III. This can be seen in the second sample and hold in Figure 3.7 where the same pixel voltage is read out right after the CAR and it did not reset. Important to state that under normal rolling shutter imager operation the pixel voltage will be read out only at the end of the integration time and not as performed in Figure 3.7. The two simultaneous sample and hold below was done only for imager validation purposes. The same scenario described above for Figure 3.7 applies below to Figure 3.8. The only difference in Figure 3.8 is that a higher illumination level was used so that the pixel voltage crosses the threshold voltage, i.e. the pixel will saturate at the end of the integration time and information will be lost without the WDR implementation. The pixel voltage in Figure 3.8 reaches ~400mV when it is first sampled and when the CAR is activated (as described in section III) the pixel voltage is reset to 1.1V (this can be seen with the second sample and hold). Now the pixel again has the full well capacity to keep on integrating with the shorter integration time per the WDR algorithm and information won t be lost. 44

54 Figure 3.7 Probed signals from the imager showing one pixel s voltage (yellow), V_Reference (purple) and the sampling of the pixel s voltage (blue). The pixel s voltage does not cross the threshold voltage (V_Refernce at V_th) and when the CAR is activated (V_Reference ramping up gradually) it does not reset the pixel s voltage. Figure 3.8 Probed signals from the imager showing one pixel s voltage (yellow), V_Reference (purple) and the sampling of the pixel s voltage (blue). The pixel s voltage does cross the threshold voltage (V_Refernce at V_th) and when the CAR is activated (V_Reference ramping up gradually) it resets the pixel s voltage. An image taken from the HALLI with the WDR turned off under low light illumination is shown in Figure 3.9a. The same image is taken again with the HALLI and 45

55 WDR turned off but with a bright laser focused on part of the image. The laser causes part of the image to saturate and information is lost when the WDR implementation is off, as shown in Figure 3.9b with part of the image saturated. Again an image is taken with the HALLI and the bright laser but with the WDR turned on and the results are shown in Figure We can see details, as per the MANTISSA image, and we can recover the whole WDR value with the combined EXP image data, Figure 3.9b. Future work is aimed for presenting the whole WDR value in a limited display. Table 3.1 Summarizes the HALLI s measured performance and figures of merit. Main features to point are the dynamic range of the imager without any WDR expansion is 54dB, i.e. just well capacity. With the three bit expansion implemented in the HALLI we get an extended dynamic range of 72dB (18 db DR expansion) and by simply increasing the memory size to store 7 bits per pixel an extended dynamic range of 96dB (42dB DR expansion) can be achieved. For comparison purposes we compare the extended DR due to the WDR algorithm with other CMOS imagers performing similar multiple reset algorithms and we leave the intrinsic DR out of the comparison. S. W. Han et al. [57] have reported on a 42 db DR expansion, P. M. Acosta-Serafini, et al. [58] reported on 60 db DR expansion, A. Belenky, et al. [59] reported on 24 db expansion for 4 bit WDR algorithm and 48 db DR expansion with 8 bit WDR algorithm. 46

56 (a) (b) Figure 3.9 Picture taken with HALLI and WDR turned off. In (a) a low light illumination and in (b) the same illumination but a bright laser was focused on the image saturating a portion of the image. (a) (b) Figure Picture taken with HALLI and WDR turned on. In (a) the MANTISSA is shown and in (b) the memory is shown (EXP value). White represents no resets, grey represents one reset at T/2 and black represents two resets, i.e. at T/2 and T/4. The prototype chip fabricated uses an N-Well over P substrate pixel structure in a standard CMOS 0.18 process giving a measured dark current density in the worst pixel of. The authors would like to note that if the same design was fabricated on an imager process with a pinned-photodiode the dark current is expected to decrease. The current chip peripherals as mentioned section III include one S/H circuitry 47

57 for the reset voltage and one for the integrated voltage (SHR and SHS shown in the timing diagram of Figure 3.4 respectively) and allow only for a partial CDS to be employed (the reset voltage is that of the next frame). The authors would like to note that the peripherals could be extended with the existing HALLI architecture to support a digital CDS mechanism in which the reset noise is eliminated at the cost of extra space and power for memory to store the reset voltage of the same frame being sampled for read out. With the AR technique and the partial CDS the reset noise was measured at 8.9. The variable topology column parallel partitioned pixel amplifier consumes static power consumption. The amplifier performs all the tasks required for high and low light level imaging, i.e. AR, ACS and WDR, thereby reducing the overall chip power in contrast to having dedicated blocks to perform each task separately. The prototype has 128 columns, therefore the total static power consumption of the amplifiers is 13.8, approximately one third the power of an architecture having dedicated blocks to perform all the tasks which can become substantial when large pixel arrays are used. Table 3.1 Chip Attributes Parameter Measurement Array Size 128 x 128 Pixel Size 7um x 7um Supply Voltage 1.8V Fill Factor 30% Conversion Gain 29 uv / e 48

58 Parameter cont. Measurement cont. Dark Current Density (worst case) 31 na / cm 2 Pixel FPN (reset frame) 0.12% Column FPN (reset frame) 0.06% QE (at 610 nm) 31% Readout Non-Linearity 0.6% Full Well Capacity Operation rate Partitioned Amplifier Gain Variable Topology Amplifier 35 ke 30 fps 66 db 500 khz Bandwidth Variable Topology Amplifier 0 81 Phase Margin Variable Topology Amplifier 108 uw Static Power Consumption Dynamic Range without WDR Extended Dynamic Range 54 db 3 bits 3.7 Conclusion A High and Low Light Imager developed in a CMOS process has been presented. The HALLI utilizes a single column parallel partitioned pixel amplifier with variable 49

59 topology for the detection of both high and low light levels in the same frame. For high light level detection, a Wide Dynamic Range algorithm is utilized. For low light level detection, two noise reduction techniques are employed; Active Reset and Active Column readout technique. Due to the commonalities in the high and low light level readout techniques, and the fact that they occur in staggered instances of time, a single partitioned pixel amplifier which can be configured in various modes of operation is used. The advantages of using a single column parallel partitioned pixel amplifier are simplicity in the analog readout path, power reduction, reduced chip size, and lower power consumption then using individuals dedicated blocks for each technique. The CMOS imager was designed and fabricated in a mixed signal 0.18 um CMOS technology. 50

60 Chapter Four: A Rail-to-Rail Differential Difference Amplifier for High Resolution Analog-to-Digital Conversion Suitable for CMOS Imagers 4.1 Introduction CMOS image sensors (CIS) has recently competed with charge-coupled device (CCD) due to low power consumption, low cost and flexible system integration [60-61]. These features make them suitable for a variety of applications such as biomedical, where an entire laboratory can be realized in a lab-on-a-chip (LOAC) [35], space [62], security [63] and industrial [64] applications. In all these applications the resolution of the image is one of the key specifications of image quality and the analog to digital converter (ADC) play a key role in the image resolution. [65]. In CMOS technology the ability to integrate the ADC with the sensor has the advantages of very small offset and gain errors, are highly linear and a small amount of circuitry is required for their implementation. The three approaches for integrating the ADC with image sensor are; one single ADC for all the pixels [66,67], a column parallel ADC[68-71] and an ADC per pixel[72-74]. In a chip level ADC a single conventional ADC operating at high speeds is integrated with the image sensor, commonly a flash ADC [75]. Usually frame rates and array size of the sensor, i.e. number of pixels, are limited due to the ADC speed requirements. In contrast the pixel level approach has the advantage of low speed ADC architecture and very fast frame rates can be realized [76], but the disadvantage is that it reduces the fill factor and with the trend in the last decade to decrease pixel size the problem worsens. In the column level approach all the ADCs operate in parallel. A column parallel ADC is widely chosen as the architecture of choice for low and high 51

61 speed mobile imagers and high performance imagers because it shows a good tradeoff between frame rates, fill factor, silicon area and power consumption. Several types of ADCs have been used in column-parallel ADC architecture s, such as the single slope ADC [69,77], successive approximation (SAR) [78], cyclic ADC [68,79-81], an iterative Divide-by-Two ADC [82] and oversampling ΣΔ ADC[83]. The main advantage of using the single slope ADC is that it can be implemented using very simple column circuitry, which mainly consists of a per column comparator and chip level ramp generator. As a result a single-slope ADC will typically require much less chip area and lower power consumption then other architectures. Moreover, the simple column circuitry also makes it relatively easy to ensure uniformity between columns and this minimizes the amount of column fixed-pattern noise (FPN). However the disadvantage of a single slope-slope ADC is its relatively slow conversion speed. Each n- bit A/D conversion requires 2 n clock periods, compared with only n clock cycles for both successive approximation and cyclic ADC. While SAR and cyclic ADCs are much faster, these all require increased chip area and complexity. A trade-off between resolution and speed can limit the use of the single slope ADC in many application where high resolution conversion (>10 bit) is desired. There have been many proposed methods on increasing the conversion speed of a single slope ADC, in which the main concept is to implement multiple slopes or a changing slope [84,85]. Another approach is having a two-step phase where you first have a coarse phase to find the region of interest and then you have a slower slope in the area of interest to increase the resolution [70,71,86,87]. In this chapter a proposed expanding analog to digital converter (EADC) in which we relax the sensitivity requirements of the 52

62 comparator and number of steps required for high resolution conversion. In the EADC method, which will be discussed more in detail in the next section, first uses a coarse phase to find the area of interest and then in the expanding phase it amplifies the area of interest back to the full voltage swing using a differential difference amplifier (DDA). The DDA which will be discussed more in detail in section 4.3. The DDA is designed in an instrumentation amplifier configuration to get high precision and accurate gain throughout the whole input common range. A semi constant-g m input stage for the DDA defines a fairly constant Gain Bandwidth Product (GBW) so that a fairly constant unity gain frequency is determined throughout the whole input common range. The last phase of the conversion is another coarse phase, similar to the first phase, but on the expanded area of interest. The main advantage of the proposed EADC method is that it still maintains the simple architecture of the single slope technique but higher resolution is achieved in a fraction of the clock cycles. Using the EADC conversion method, the conversion time is /2 2*2 N clocks cycles instead of 2 N in the case of the classic single slope. As an example for a 16 bit conversion (N=16), using the proposed EADC method would require 512 clocks and in a classical single slope 65,536 clocks would be required, i.e. in 0.78% of the time. An additional advantage is that two coarse comparisons are made and therefore sensitivity requirements of the comparator can be drastically relaxed, so simple and / or high speed comparators can be used. As an example in a CMOS 0.18um process the full voltage swing is 1.8V, so to achieve a 16 bit conversion with classical single slope architecture the comparator would need to be able to differentiate 27uV increments (a difficult task especially as this can be well into the noise floor in many circuits). In the 53

63 EADC method the comparator would only require a sensitivity of 7mV, a fairly simple task and therefore high speed comparators can be implemented. Due to the relaxed sensitivity requirements in the EADC method very fast frame rates can be used in CMOS image sensors while achieving high resolution conversion. The remainder of this chapter is organized as follows. Section 4.2 the DDA design is presented. In section 4.3 the EADC method in discussed in detail. The results are presented in Section 4.4 and the conclusion in Section DDA Design The DDA is a basic CMOS analog building block yielding simple analog VLSI circuits with low component count [88,89]. The DDA is an extension to the op-amp, the main difference is that instead of two single-ended inputs, as the case in op-amps, it has two differential input ports (V pp -V pn ) and (V np -V nn ). The symbol for the DDA is shown in Figure 4.1. The output of a DDA can be expressed as where A is the open loop gain of the DDA. When o introduced, i.e., to Vpn or/and expression is obtained (15): V o A o[(vpp - V pn ) - (Vnp - V nn)] (14) Ao very large and negative feedback is Vnp which appear in (14) with a negative sign, the following Vpp - V pn = Vnp - V nn (15) In contrast to the op-amp we can see that V pp and Vpn or V np and V nn do not have the property of virtual ground but the difference between the two differential input voltages is virtually zero. 54

64 . Figure 4.1 The DDA Symbol DDA based circuits provide high input impedance and simple external circuitry due to its features of differential difference inputs. A precise differential gain throughout the whole input common range is required for the expanding ADC. An instrumentation amplifier is well suited for the task due to its characteristics of very low DC offset, low drift, low noise, very high open-loop gain, very high common-mode rejection ratio (CMRR), and very high input impedances. But in its conventional form it requires three op-amps and many external resistors which have to be tightly matched. Mismatches in the resistors values and mis-match in the common mode gains of the two input op-amps cause undesired common mode gain [90]. An instrumentation amplifier can be realized using one DDA and two gain determining resistors. Figure 4.2 shows a DDA realization of an instrumentation amplifier which is programmable by two external resistors for a gain of (R1 R 2) / R 1. The amplifier in instrumentation configuration is characterized by equation (16) referenced from [92] : 55

65 R R R R 1 V (1 )( V V V V ) (16) o 2 1 cm off R1 CMRRd 2CMRR n Ad R1 CMRR p wherecmrr and CMRR are the common mode rejection ratios for the two input ports p and n respectively. p n CMRR d which is not known from the regular op-amp as the CMRR of a two input op-amp, measures the effect of equal floating voltages at the two input ports. A d is the differential gain of 2 V1 V while Vcm is the common mode voltage of the differential pair ( V 2 V 1 ) and Voff is the offset voltage. It can be seen from (16) that with high differential gain and high common mode rejection ratios, accurate differential gain can be accomplished over a wide common mode input voltage range. It should be noted that the offset voltage can be reduced using an autozero technique used in op-amps [91]. Alternatively the offset can be cancelled by adding a third low-sensitivity differential pair [92]. Figure 4.2 A DDA based instrumentation amplifier which is programmable by two external resistors for a gain of (R1+R2)/R1. 56

66 The proposed transistor design for the DDA is shown in Figure 4.3. The DDA consists of an input stage to control the tail currents of the input pairs. A semi constant- G m is achieved by ensuring the sum of the tail currents remains constant, thereby achieving a fairly constant GBW for the whole input common range. A constant GBW for the whole input common range is important for the expanding ADC as it will determine the maximum clock speed of the conversion. The design of the input stage will be discussed later in this section. The DDA is implemented as a two stage folded-cascode amplifier. The DDA has three input pairs, a complementary PMOS and NMOS input pair (M1-M4) for Vpp and Vpn as to cover the rail-to-rail operation and an additional PMOS input pair M5-M6 Vnn and Vnp for the feedback. The first stage consists of the folded-cascode branch (M7- M14) utilizing two gain boosters A1 and A2 controlling the gate voltages of M9-M10 and M11-M12 respectively. M13-M14 and M7-M8 are biased with a constant voltage Vb1 and Vb2 respectively. The second stage consists of a transimpedance amplifier A3 to convert the output current from the first stage to a voltage Vout. The gain of the transimpedance stage is controlled through the feedback resistor Rf and lastly R2 and R1 in series define the differential gain of the full DDA instrumentation amplifier configuration. The DDA in this configuration can be simplified and redefined as. R R R R V ( V V ) V (17) out pp pn diff R1 R1 The voltage differential Vdiff generated on (M1-M4) generates a current diff ( Vpp Vpn ) I defined in: 57

67 I I I (18) diff ( Vpp Vpn ) PMOS NMOS Where and I NMOS are the tail currents of the PMOS and NMOS input pair IPMOS respectively. The DDA achieves the desired gain of (R1+R2)/R1 when (19) is satisfied in steady state. I I (19) diff ( Vnn Vnp ) diff ( Vpp Vpn ) Where Idiff ( Vnn Vnp ) is the tail current of M5-M6 feedback pair. Equations (17) (19) are only valid if the sum of the tail currents of the PMOS and NMOS input pair is a constant for the rail-to-rail common mode input ( V cm ) range and the tail current of the feedback pair M5-M6 is also equal to the same constant, i.e. for (20) has to be satisfied so that (17) (19) are valid: I I I Constant p n ref V V V Gnd V Vdd cm pp _ common _ mod e pn _ common _ mod e cm (20) V, V is the common mode voltage of Vpp and Vpn. The Where pp _ common _ mod e pn _ common _ mod e input stage of the DDA shown in Figure 4.4 takes care of the functionality defined in (20). 58

68 Figure 4.3 DDA Transistor Design The input consists of two constant current sources each providing a constant current of Iref. When the common mode input voltage Vcm is at gnd, M3-M4 are off, no current flows through the NMOS input pair (In=0) and therefore M16 is also off because Iref has to flow through M15. The current flowing through M15 is mirrored into the PMOS input pair and Ip = Iref in this case. As Vcm is increased M3 and M4 start turning on and the tail current (In) flows through the bottom current source. In order to satisfy Kirchhoff's circuit laws the same current (In) has to flow through M16 and therefore In=Iref-Ip and Ip is mirrored into the PMOS input pairs. When Vcm reaches Vdd, Ip = 0 and all the current from the top current source flows through M16. It has been shown that the input stage takes care of (20) and that a semi constant-g m input stage is achieved. It is 59

69 worth noting that for a fully-constant-g m input stage the sum of the square root of the tail currents needs to be constant rather than the sum of the tail currents. With the semiconstant-g m a 4% variation in the G m is achieved which is sufficient for the frame rates required in CMOS imager applications in which the DDA is incorporated in a column parallel configuration. The DDA and ADC results will be discussed in section 4.4. Figure 4.4 DDA Input Stage 4.3 Expanding ADC Technique The proposed EADC technique is suitable for high resolution analog to digital conversion in CMOS imagers while still maintaining high frame rates. The technique utilizes the simplicity of single slope architecture while overcoming the limitation of a large amount 60

70 of clock cycles required for high resolution conversion by incorporating an expanding phase. In addition high resolution conversion would require very small voltage increments when the ramp is being generated and also the comparator requires high sensitivity. To overcome these problems a DDA configured in instrumentation amplifier mode is incorporated to expand the area of interest. The EADC technique consists of first a coarse phase to derive the most significant bits (MSB), then an expanding phase with the DDA to expand the area of interest back to the full voltage swing and lastly an additional coarse phase to derive the least significant bits (LSB). An illustration of the proposed method is shown in Figure 4.5. First a coarse ramp voltage is incremented in steps equal to [VDD/2]^(N/2) in contrast to [VDD/2]^N when using a classic single slope architecture. The ramp in Phase 1 is incremented until it crosses the unknown analog voltage requiring conversion (Vin). The voltage (V_Ramp1_Stop) at the first incremented point after it crosses is stored and passed on to the DDA in Phase 2. The DDA in phase 2 expands the difference between the V_Ramp1_Stop and Vin by a factor of 2^(N/2) and passes a new input voltage for the second coarse conversion. In Phase 3 a coarse ramp incremented in steps of [VDD/2]^(N/2) is again used again to derive the LSB, this time with the new differential amplified signal as the input voltage to be converted. 61

71 Figure 4.5 The proposed EADC Technique The full ADC architecture utilizing the DDA is shown in Figure 4.6. The input voltage Vin to be converted is fed into Vpn of the DDA and to V+ of the comparator. The single slope ramp is incremented and the Ramp1 output voltage is fed into Vpp of the DDA and to V- of the comparator. Due to the ramp incrementing in coarse steps of Vdd/2^(N/2) rather than steps of the Vdd/2^N as in a classic single slope, the comparator sensitivity requirements can be drastically reduced. When the Ramp1 output voltage crosses the input voltage (Vin) the comparator signals the Counter1 to stop counting and for the Ramp1 to stop incrementing. Counter1 now holds the N/2 MSB of the conversion. The output of the DDA now holds the expanded voltage equal to the difference between the Ramp1 stop voltage (V_Ramp1_Stop) and input voltage (Vin) times the gain factor of the DDA (R1+R2)/R1 which in the case of the ADC is equal to 2^(N/2). The expanded voltage is now fed into the V+ of the second comparator and Ramp2 output voltage is fed into the V- of the comparator. Ramp2 is also incremented in coarse steps of Vdd/2^(N/2) and when the Ramp2 output voltage crosses the expanded voltage the comparator signals 62

72 Counter2 to stop. Counter2 now holds the N/2 LSB bits of the input voltage (Vin) conversion. Figure 4.6 ADC Architecture The advantage of the proposed EADC technique and ADC architecture is that no switches are required for the high resolution conversion, in contrast to many other schemes, therefore problems such as charge injection don t limit the performance. The main advantage is that the simplicity of the single slope technique is maintained while a high resolution is achieved in a fraction of the time. In the test chip fabricated in a CMOS 0.18um process, an N=16 Bit ADC was designed. Using the EADC method only 2^8 + 2^8 clocks = 512 clocks are required for conversion in comparison to 2^16 clocks = 65,536 clocks if a classic single slope architecture was used. As for the sensitivity of the 63

73 comparator and coarse ramps, in the EADC method the steps are ~7mV in comparison to 27uV as in a classical single slope architecture. 4.4 EADC ADC Results A test chip was fabricated in a CMOS 0.18um process with supply voltage Vdd=1.8V. R1 and R2 where fabricated so that a gain of 2^(N/2)=256 is achieved when the DDA in configured in instrumentation amplifier configuration. The gain is suited for a 16 bit ADC, i.e. N=16. Figure 4.7 shows the simulated Gain Margin and Phase Margin of the DDA, a Gain Margin of -119dB and Phase Margin of 73.9 degrees is achieved. Figure 4.8 shows the simulated open loop gain of the DDA as a function of the input voltage. A small signal of 1mV was inputted and it can be seen that a high open loop gain ~126dB is achieved throughout the whole input range, i.e. Gnd to Vdd. A variation of ~4% is achieved and therefore a semi-constant-g m is achieved thereby defining a near constant GBW for the whole input common range. The increase in G m is attributed to the fact that both PMOS and NMOS input pairs are on and the sum of the square root of the tail currents is larger than the constant when one of the input pairs is off. 64

74 Figure 4.7 Simulated Gain Margin and Phase Margin of DDA Figure 4.8 Simulated Open Loop Gain of the DDA 65

75 CMRR n and simplified to: Returning to the theoretical DDA equation (16), The simulated results for CMRR p, Ad where 114dB, 101dB and 126dB respectively and therefore (16) can be R R ( ) (21) 1 2 Vo V2 V1 R1 The DDA offset was subtracted when calibrating the test chip and therefore the DDA met the high conversion requirements. The test chip included a switched capacitor based ramp generator on chip which 18 was incremental in 2 steps from Gnd to VDD. The ramp generator was used as the input for the ADC under test and the input signal was also outputted to an 18bit ADC on board. The histogram method was used to derive the expanding ADC differential nonlinearity (DNL) and integral nonlinearity (INL) with 1024 samples taken for each 18 Vdd /2 increment. Non-linearity s of the on chip ramp generator were removed by using data from the on-board 18 bit ADC. DNL and INL measured results of the expanding ADC are shown in Figure 4.9 and Figure 4.10 respectively. 66

76 Figure 4.9 Expanding ADC DNL Figure 4.10 Expanding ADC INL 67