IEEE Transactions on Very Large Scale Integration Systems

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1 A CMOS Image Sensor with on Chip Image Compression based on Predictive Boundary Adaptation and Memoryless QTD Algorithm Journal: Manuscript ID: TVLSI-- Manuscript Type: Regular Paper Date Submitted by the Author: -Feb- Complete List of Authors: Bermak, AE Amine; Hong Kong University of Science and Technology, Electrical and Electronic Engineering Chen, Shoushun; Yale University, EEE Wang, Yan; HKUST, ECE Key Words: CMOS Image Sensor, On-Chip Compression, Predictive Boundary Point Adaptation

2 Page of A CMOS Image Sensor with on Chip Image Compression based on Predictive Boundary Adaptation and Memoryless QTD Algorithm Chen Shoushun, Amine Bermak, Senior Member, IEEE, and Wang Yan Abstract This paper presents the architecture, algorithm and VLSI hardware of image acquisition, storage and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using -bit Static-RAM device embedded at the pixel level. An adaptive quantization scheme based on Fast Boundary Adaptation Rule (FBAR) and Differential Pulse Code Modulation (DPCM) procedure followed by an on-line, least storage Quadrant Tree Decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including x pixels, read-out and control circuitry as well as the compression processor was implemented in.µm CMOS technology with a silicon area of..mm. Simulation results show compression figures corresponding to. Bit-per-Pixel (BPP), while maintaining reasonable PSNR levels. I. INTRODUCTION With the development of network and multimedia technology, real time image acquisition and processing is becoming a challenging task because of higher spatial and coding resolution, which imposes very high bandwidth requirement. New applications in the area of wireless video sensor network and ultra low power biomedical applications have created new design challenges. For example, in a wireless video sensor network, each node takes pictures of its surrounding area, compresses the image and transmits the data to its parent in the network. As usually the sensor is powered by small batteries, an energy efficient image acquisition as well as image compression system is required. This is only possible using custom single chip solutions integrating image sensor and hardwarefriendly image compression algorithms. However, standard image compression techniques such as JPEG and Wavelet Transform remains an expensive hardware [][][] in digital video camera. This would limit the prospect of implementing low power image acquisition and compression on a single chip. In order to alleviate some of these problems, we have reported a single chip vision sensor with a hardware friendly image compression algorithm based on FBAR followed by an on-line QTD processing enabling low power and compact image acquisition and compression []. The image is first acquired using a time domain CMOS digital pixel sensor array followed by FBAR scheme which permits to compress the data to Bit-per-Pixel (BPP). Further compression (.. BPP) is accomplished, while scanning out the pixel values, Chen Shoushun, Wang Yan and Amine Bermak are with HKUST, ECE Department, Clear Water Bay, Kowloon, Hong Kong, bermak@ieee.org. using QTD algorithm. The scanning sequence in this work is based on a Morton(Z) [] scan which features block based scan strategy. However, the transition from one quadrant to the next involves jumping to a non-neighboring pixel resulting in spatial discontinuity. We proposed a smooth boundary point propagation scheme but at the expense of additional two - bit registers for each level of quadrant. In this paper, we propose a second generation of image compression system. Compared to the previous work, the -bit FBAR algorithm is performed on the predictive error rather than the pixel itself using DPCM which results in compressed dynamic range. A new Hilbert scanning technique is used avoiding any spatial discontinuity in the scanning sequence and maintaining block based scanning strategy. This makes it quite suitable to both the FBAR and QTD algorithm. The proposed compression algorithm was validated through extensive Matlab simulation and implemented using Alcatel.µmCM OS technology. The remainder of the paper is organized as follows. Section II introduces design of the TFS-based DPS pixel. Section III introduces the algorithmic considerations for the -bit FBAR algorithm combined with the DPCM technique and the simulation results. Section IV describes the imager architecture. This section also introduces design strategies used for implementing the Hilbert Scan. Section VI concludes this work. II. PIXEL DESIGN AND OPERATION The image array consists of digital pixel sensors. As shown by Fig. (a). The circuit includes main building blocks namely photodetector PD with its its internal capacitance C d, followed by a reset transistor M and a comparator (M- M) and -bit SRAM each of which is implemented by transistors. The comparator s output is buffered by (M-M) then served as a write enable ( SRAM WriteEn ) signal of the SRAM. As explained in Fig. (b), the pixel is operated in two modes, denoted as acquisition mode and storage mode, respectively. In the first mode, the pixel s operation is further divided into two separate stages. The first stage corresponds to the integration phase in which the illumination level is recorded asynchronously within each pixel. The voltage of the sensing node VN is first reset to V dda. After that, the light falling onto the photodiode discharges the capacitance C d associated with the sensing node, resulting in a decreasing voltage across the photodiode node. Once the voltage VN reaches a reference voltage V ref, a pulse is seen at the output

3 Page of Row Sel Rst Photodetector Fig.. VddA M PD VN VddA M M Vbias M M M Comparator Vref VddA M M Vdd M M (a) M M (a)pixel Schematic. (b)pixel operation diagram. Vdd Column Sel SRAM WriteEn On pixel Mem Read_Write (= read, = write) of the comparator. The time to generate the first spike is inversely proportional to the photocurrent [] and can be used to encode the pixel s brightness. Actually, a global offpixel controller operates as a timing unit which is activated at the beginning of the integration process and provides timing information to all of the pixels through Data Bus. The pixel s SRAM WriteEn signal is always valid until the pixel fires. Therefore, the SRAM will first follow the changes on the the Data Bus and the last data stored is the pixel s timing information. Once the integration stage is over, the pixel array turns to Read-out stage. The pixel array can be interpreted as a distributed static memory and can be easily readout using Row and Column addressing techniques. At this stage, the global timer is removed from the driving the Data Bus. Column address decoder will select one column of pixels and their data will be put onto the Data Bus. Therefore, there is only one set of data bus in the array which is served as input bus in the integration stage and then served as output bus in the Read-out stage. In the second operation mode, storage mode, the pixel is served as an -bit memory unit. This is realized by turning on both transistor M and M. Actually, the external global control signal Read W rite differs in the acquisition mode and storage mode. In the latter mode, it turns from to. With both the row and column select signals, the SRAM WriteEn signal is re-enabled such that the pixel picks up the data on the Data Bus into its built-in memory. Compared to the pixel reported in [], this new pixel reduces the number of transistors from to by removing the self-reset logic for the photodiode and the reset transistor for each bit of the on-pixel SRAM. At the same time, only two stages of inverter is needed between the comparator and the memory because the SRAM Write Enable signal is no longer pulse width sensitive. Further more, the pixel is built with new feature. The pixel can be used as general purpose storage element for image processing algorithms which will be explained by future sections. B B B Data Bus Pixel Operation Stage Rst VN Row DataBus SRAM WriteEn SRAM Content Vref Integration Read Out X X (b) III. IMAGE COMPRESSION ALGORITHMIC CONSIDERATIONS The image compression procedure can be achieved in three different phases. In the first phase, the image data is scanned out of the array in the order of Hilbert scanning then compared to a predictive value from a backward predictor. Based on the comparison result, a codeword ( or ) is generated and feedback to adjust the predictor s parameters. In the second phase, the / codeword stream is considered as an binary image which is further compressed by a QTD processor. The compression information is encoded into a tree structure. Finally, the tree data together with non-compressed codewords are scanned out during the third read-out phase. A. Predictive Boundary Adaptation The proposed compression scheme can be specified by an ordered set of boundary points (BP ) y < y < < y i < y i < < y N < y N delimiting N disjoint quantization intervals R,, R i,, R N, with R i = [y i, y i ]. The quantization process is a mapping from a scalar-valued signal x into one of reconstruction intervals, i.e., if x R j, then Q(x) = y j. This Quantization process thus inevitably introduces quantization error when the number of quantization intervals is less than the number of bits needed to represent any element in a whole set of data. The most commonly used distortion measure is the r th power law distortion: d (x, Q (x)) D r N x y i r p(x)dx () i= It has been shown that using Fast Boundary Adaptation Rule[] can minimize the r-th power law distortion, e.g. the mean absolute error when r = or the mean square error when r =. At convergence, all the N quantization intervals R i will have the same distortion D r (i) = D r /N. This property guarantees an optimal high resolution quantization. For a - bit quantizer, there will be just one adaptive boundary point y delimiting two quantization intervals, with R = [, y] and R = [y, ]. At each time step, the input pixel intensity will

4 Page of fall into either R or R. BP is shifted to the direction of the active interval by a quantity η. After that, the BP itself is taken as the reconstructed value. x(n) + Fig.. BP P (n) Predictor BP(n) D D D Reg Reg Reg -bit Adaptive Q combined with DPCM. / u(n) + + η Adaptation In our system, before a new pixel (x(n)) comes, its value is first estimated by BP P (n) through a backward predictor as shown in Fig.. Three registers, denoted as Reg, Reg, Reg are used to store the history values of the reconstructed pixels. BP is estimated by the equation: BP P = Reg. Reg. + Reg. () Compared to the scheme reported in [], BP P is now a function of several neighbor pixels instead of just one neighbor pixel. The estimated pixel value is then used to be compared with the real incoming value. The comparison result, or, is taken as a codeword u(n) which is further used to update the boundary point: if(u(n) == ), BP = BP P + η; else, BP = BP P η () At the end of this clock cycle, the newly obtained BP is feedback to update Reg and to predict the next pixel s value. The codeword u(n) is also used to adjust another very important parameter η. As stated in [], the adaptation step size parameter η is found to affect the quantizer s performance. On one hand, a large η is needed so as to track rapid fluctuations in consecutive pixel values. On the other hand, a small η is needed so as to avoid large amplitude oscillations at convergence. To circumvent this problem, we propose to make η adaptive using the following heuristic rule: if the active quantization interval does not change between two consecutive pixel readings, we consider that the current quantizing parameters are far from the optimum and η is then multiplied by Λ >. If the active quantization interval changes between two consecutive pixel readings, we consider that the current quantizing parameters are near the optimum and thus η is reset to its initial value. This rule can be done by simply looking at the condition of u(n) == u(n ). When this condition is true, we consider that BP is now consecutively adapted to the same direction and η must be increased. Otherwise, i.e, this condition is false, we consider BP is now changing the adaptation direction which means the convergence is probably achieved. B. Hilbert scanning The adaptive quantizer explained earlier permits to build a binary image on which quadrant tree decomposition (QTD) can be further employed to achieve higher compression ratio. The QTD compression algorithm is performed by building a multiple hierarchical layers of a tree which corresponds to a quadrant in the array. To scan the image data out of the pixels array, many approaches can be employed, the most straightforward way, raster row and column scan, for example. However, as will be explained in the next section, different scanning sequence highly affects the QTD compression performance. Generally speaking, block based scan can result in higher PSNR and compression ratio because it favors both the adaptive quantizer and QTD processor by providing larger spatial correlation. In the previous work [], we built the tree by scanning the array using the Morton (Z) [] scan strategy as shown by Fig..(a). It is clear to note that the transition from one quadrant to the next involves jumping to a nonneighboring pixel which will result in spatial discontinuity which gets larger and larger when scanning the array due to the inherent hierarchical partition of the QTD algorithm. As a consequence, we will lose the benefit of similarity at the edge of large quadrants. To address this problem, we proposed a smooth boundary point propagation scheme at the expense of two additional -bit registers for each level of quadrant. As shown in Fig..(a), two registers (A, B) are needed to store the boundary point for the quadrant level and two other registers (A, B) are needed to store those related to the quadrant level. B B B B A A A A A B A B A A (a.) A A A (b.) Fig.. (a.)smooth boundary point propagation scheme using Morton (Z) scan. (b.)hilbert scan patterns at each hierarchy for a array. Hilbert scanning provides another interesting solution without using the additional storage. As shown in Fig..(b), the scanning is also performed within multi-layers of quadrants but always keeping spatial continuity when jumping from one quadrant to another. It ensures minimal storage requirement for the adaptive quantizer as the neighboring pixel s value is the one just scanned. The implementation of Hilbert scanning can be quite straightforward by using hierarchical address mapping logic which will be explained in the next section. C. Simulation Results We have compared the performance of our proposed algorithm, adaptive η with DPCM using Hilbert scan (η- Hilbert+DPCM), with other operation modes, namely fixed η raster scan (η -R), adaptive η raster scan (η-r), adaptive η Morton (Z) scan (η-mz), adaptive η smooth boundary Morton (Z) scan (η-smoothmz), adaptive η Hilbert scan (η-hilbert) over a set of test images. These test images were randomly selected from popular scientific image database. As stated

5 Page of PSNR (db) Compression Quality vs. Eta, image size : x (MaxPSNR=.dB)@(Eta=.). Eta (a) BPP. Bit per Pixel PSNR (db) Compression Quality vs. Eta, image size : x (MaxPSNR=.dB)@(Eta=.). Eta Fig.. Simulation results about the choice of η which strongly affects the compression quality in terms of PSNR and BPP. (a) image size = (a) image size =. Size of test images Operation modes PSNR BPP M η PSNR BPP M η PSNR BPP M η PSNR BPP M η η -R η-r η-mz η-smoothmz η-hilbert η-hilbert+dpcm TABLE I AVERAGE PERFORMANCE OF TEST IMAGES UNDER DIFFERENT OPERATING MODES, NAMELY FIXED η RASTER SCAN (η -R), ADAPTIVE η RASTER SCAN (η-r), ADAPTIVE η MORTON (Z) SCAN (η-mz), ADAPTIVE η SMOOTH BOUNDARY MORTON (Z) SCAN (η-smoothmz), ADAPTIVE η HILBERT SCAN (η-hilbert) AND ADAPTIVE η WITH DPCM USING HILBERT SCAN (η-hilbert+dpcm). M = P SNR [db/bp P ]. THE TABLE SHOWS THAT BP P EACH MODE CAN ACHIEVE TO ITS MAXIMUM PSNR USING A SPECIFIC VALUE OF η. THE η-hilbert+dpcm MODE PRESENTS THE BEST PSNR AND in [] the performance of quantizer is highly dependent on the choice of η. There even exists an optimal η value for a particular image under each operation modes. However, it isn t practical to try all of the choices when the user wants to capture an optimal image. Therefore, for each operation modes reported in Table I, we sweep the value of η from to and calculate the average PSNR and BPP to find the optimal one. Fig. shows the results when sweeping η for the operation modes of DPCM using Hilbert scan (η- Hilbert+DPCM). Both PSNR and BPP are highly dependant upon the value of η. Using a large value for η will permit to reach oscillation faster and hence improved compression ratios are obtained when using QTD. However η cannot be increased indefinitely as it will result in a rapidly degraded PSNR performance. For image set sizing of and, the optimum η was found to be around and, respectively. From Table I, we can note the benefit of adaptive η by comparing the figures in the first and second row. Both the two operation modes are based on conventional row and column raster scan. With adaptive η, PSNR can be increased about.db for the sake of faster convergence speed. The BPP FIGURES WHEN η =. (b) third row reports that using Morton (Z) scan can achieve better performance than raster scan because it is block based strategy and more correlation can be explored. However, in Morton (Z) scan, the transition from one quadrant to the next involves jumping to a non-neighboring pixel resulting in spatial discontinuity. We have proposed a smooth boundary point propagation scheme and its performance is reported in the fourth row. Bad pixels are removed which results in a PSNR improvement of about.db ( ). Hilbert scan provides another interesting block based scan strategy featuring smooth transition. One can note from the fifth row that, it can easily achieve even better performance than smooth boundary Morton (Z) scan. Finally, the best figures of PSNR and BPP are achieved when applying our proposed algorithm, combining DPCM with Hilbert scan. From Table I, we can also note that significant performance improvements are obtained when using large size images. For our proposed algorithm (the last row), using format instead of enables a % and a % improvements in terms of PSNR and BPP, respectively. This represents a significant improvement and points out to an important finding suggesting that the proposed algorithm is much more effective BPP... Bit per Pixel

6 Page of for large size images. A. Imager Architecture IV. VLSI IMPLEMENTATION Fig..(a) shows the block diagram of a single chip CMOS image sensor with the adaptive DPCM quantizer and the QTD processor. The image array consists of digital pixel sensors. The pixel array is operated in two separate phases. The first phase corresponds to the integration phase in which the illumination level is recorded and each pixel sets its own integration time which is inversely proportional to the photocurrent. A timing circuit is added in our imager in order to compensate for this non-linearity by adjusting the quantization levels of a sampling counter circuit. In our prototype, a bit word memory is used in order to apply more compensation modes than the straightforward linear relationship, logarithmic relationship, for instance. In the integration phase, the row buffers drive the timing information in gray code format to the array. After the longest permitted integration time, the imager turns into the read-out mode. The row buffers are disabled and the image processor starts to work. First, the QTD processor will generate linear quadrant address which is then translated into Hilbert scan address by the Hilbert Scanner block. The address is decoded into Row Select Signal (RSx) and Column Select Signal (CSx). The selected pixel will drive the data bus and its value will be first quantized by the DPCM Adaptive Quantizer then the binary quantization result will be compressed by the QTD processor. B. Hilbert Scanner Hilbert scanning is actually composed by multiple levels of four basic scanning patterns as shown in Fig.. Fig.. RR RR CC CC Basic scanning patterns found in Hilbert scan. They are denoted as RR, RR, CC, and CC respectively. RR represents a basic scanning pattern featuring a relationship between its linear scanning sequence and physical scanning address as following: RR linearaddress : ( b) ( b) ( b) ( b) hilbertaddress : ( b) ( b) ( b) ( b) CC represents another basic scanning pattern with the following address mapping relationship: CC linearaddress : ( b) ( b) ( b) ( b) hilbertaddress : ( b) ( b) ( b) ( b) CC RR RR CC RR RR RR CC CC RR CC CC CC RR RR CC CC CC RR RR Fig.. Hilbert scanning patterns between hierarchies of quadrants. If the parent scanning pattern is RR, its four children quadrants pattern are CC RR RR CC, respectively. For an array of m m pixels, the whole Hilbert scan can be represented by m levels of scanning patterns. For an intermediate level, its scanning pattern is determined by its parent quadrant s pattern. At the same time, its scanning pattern can also determine its children quadrants patterns. This is shown by Fig.. If one quadrant is in the format of RR, then its four children quadrants must be in the format of CC RR RR CC. Based on this nice feature, we can implement Hilbert scanning in a top-down approach. Firstly, we use a linear address to segment the whole array into levels of quadrants. Each level of quadrant is addressed by -bit of address. Then we need to know which kind of scanning pattern for each quadrant level. For the very top quadrant level, the scanning sequence is predefined, either RR or CC. If we assume that we now using RR, then the scanning types of the four quadrants are CC RR RR CC, respectively. By looking at the first -bit of the MSB address, we can tell which of the four largest quadrants we are scanning now. If the first -bit MSB is now b, i.e, we are now in the fourth quadrant, then its scanning pattern must be in the format of CC. Consequently, its four sub-quadrants must be in the format of RR CC CC RR. Further more, we can determine which one of them we are within now by looking at the second -bit MSB of the linear address. Applying the same procedure on the rest levels, we can map all of the linear address into Hilbert scan address. The above mapping only involves some bitwise manipulation and therefore, no sequential logic is needed which results in very compact VLSI design. C. QTD Algorithm with Pixel Storage Reuse For our array, the tree information is to be stored in registers with a total number of =. In the previous work, the QTD tree is built out of the pixel array which occupies significant silicon area. A possible solution to save area is based on the following observation: After the -bit FBAR algorithm, the original -bit pixel array is compressed into another array which has an effective storage of only bit/pixel. QTD tree can be stored inside the array by reusing the storage of the DPS pixels. To understand our approach, we first express the QTD algorithm in this way: if one quadrant can be compressed, only its first pixel s value and its root are necessary information. All the other pixels in the quadrant and the intermediate level nodes on the tree can be compressed. Outside of the pixel array, at each quadrant level (except the root and second largest quadrant level), we maintain a -bit shift register which temporarily stores the nodes on that tree level. For the

7 Page of Integration/ Read out Controller W/R W/R CS CS CS P, P, Row Decoder Hilbert Scanner Column Decoder CS P, RS RS RS On Pixel SRAM P, Row Buffer/Decoder Obuff Ibuff P, P, P, P, Obuff Ibuff P, P, P, P, Ibuff Pd Comparator x Pixel Array Obuff Pixel Vdd Rst Cd Variable Clock Gray De Counter + Pd W SRAM R Vn DPCM Adaptive Q QTD Processor Vref r Fo Fig.. Timing LUT RAM Image Processor (a) (b) (a)imager architecture (b)imager layout implemented in Alcatel. µm CMOS technology with main blocks highlighted. pixel level, a -bit shift register (SRP ix) is maintained to store the first pixel of each quadrant. If the level quadrant can compressed, the last bits of SRP ix will be shifted off and if the level quadrant can be compressed, the last bits of SP P ix will be shifted off, etc. If it is full, the oldest bits will be written back into the array at the address of b xx ss, where ss is b, b or b. ew vi B B B B new_node_x SR Block Re << Mux B B S >> D. Physical Implementation Fig.. Block diagram of the shift register at the (SR) and (SR) block level. At each level, the -bit LSB will be shifted off if its higher level s lowest bit is. ly B B B B new_node_x SR Block The single chip image sensor and compression processor was implemented using.µm AMI CMOS digital process (-poly metal layers). Fig..(b) shows the chip s layout with a total silicon area of..mm. The pixel array was implemented using a full-custom approach. Each pixel occupies an area of µm with a fill factor of %. The digital processing parts was synthesized from HDL and implemented using automatic placement and routing tools. The digital processor occupies an area of..mm. In Table II, we compared the number of flip-flops used in this processor compared to that reported in []. On << Mux B B S >> Function Block Adaptive η DPCM SmoothMZ QTD HilbertScan Total This work That of [] sake of clarity, let s look at the operation principle of one intermediate level as shown in Fig.. Each valid bit of the shift register SR represents the compression information of a block. During scanning, after each block is scanned, the shift register SR will shift in a new value (new node ). TABLE II However, after each of its higher level, block, is scanned N O. OF FLIP - FLOPS USED IN THIS WORK AND []. A S THE NUMBER OF and if that block can be compressed, the last bits of COMBINATIONAL LOGICS ARE DETERMINED BY MANY IMPLEMENTATION SR will be shifted off. When the SR register is full ( bits), PARAMETERS, FOR EXAMPLE, SYNTHESIS TIMING CONSTRAINTS, the oldest bits are the nodes that can t be compressed and PLACEMENT AND ROUTING PARAMETERS AND CLOCK TREE will be written back to a special location of the array, which SPECIFICATION, WE ONLY COMPARE THE NUMBER OF FLIP - FLOPS USED. is at the lower right corner of the corresponding quadrant. For The pixel layout is shown in Fig..(b), with the main example, the SR register can only be stored at the binary addresses of bxx ss, where ss can be b, b or building blocks labeled. The photosensitive elements are n+ p b and xx can be b to b. While at the lowest photodiodes chosen for their high quantum efficiency. Except

8 Page of for the photodiode, the entire in-pixel circuitry (Fig. (a)) is shielded from incoming photons to minimize the impact of light-induced current resulting in parasitic light contribution to the signal. Guard rings are used extensively to limit substrate coupling and as a means to shield the pixels from the outer array digital circuitry. Power and ground buses are routed using top layer metal. V. EXPERIMENTS AND DISCUSSION In order to characterize the prototype, a FPGA based testing platform has been developed shown in Fig.. The FPGA is configured to provide input control signals and temporarily store the output signals from the prototype. The SRAM of the timing unit is first configured followed by a global pixel reset signal which starts the integration process. The timing unit de-counts from until, in gray code format. When it reaches to the value of, i.e, the darkest gray level value, the integration process is considered to be finished and the image processor is enabled. The FPGA temporarily stores the captured data into an on-board SRAM and then sends it to a host computer though low speed UART connection when all of the data is received. As described earlier, the imager will send the trimmed tree data followed by the compressed binary image data (quantization codewords), which is actually the first pixel within each compressed quadrant. As a result, on the host computer, the same tree is first rebuilt and the whole array can be filled guided by the tree and the first pixel value of each quadrant. FPGA Board data Host PC control data Chip mounted on PCB Fig.. FPGA based testing platform which is composed by a host computer, FPGA board (Memec Virtex- MB) and the chip under test. Fig. shows some sample images with their BPP figures acquired from the prototype. One can note that, the proposed imager works much better for images with more uniform background. For the th sample in Fig., a BPP figure as low as. is achieved. While for a complicated object, the th one, due to the overhead information stored in the QTD tree, the compression ratio is even worse than without doing the QTD processing (which will be BPP). VI. CONCLUSION In this paper, a single chip CMOS image sensor with a hybrid -bit FBAR quantizer combining DPCM algorithm BPP= BPP=..... BPP= BPP=..... Fig.. Captured images from the prototype chip. The first and third rows show the sample images captured without compression while the second and fourth rows represent the reconstructed compressed images using the proposed image compression processor. and QTD compression processor is presented. Hilbert scan is employed to provide both spatial continuity and quadrant based scan. The whole processor is implemented with small hardware expense but achieves. BPP compression ratio and. db image (for resolution) quality. ACKNOWLEDGMENT This work was supported by a University grant and a grant from the RGC of Hong Kong ( and HIA/.EG). REFERENCES [] A. Olyaei and R. Genov, Mixed-Signal Haar Wavelet Compression Image Architecture, MWSCAS,Cincinnati, Ohio,. [] Kawahito, et al., CMOS Image Sensor with Analog -D DCT-Based Compression Circuits, JSSC, Vol., No., pp.-, Dec.. [] L. G. Chen, et al., A lowpower direct D-DCT chip design, in J. VLSI Signal Process., Vol., pp.-,. [] S. Chen, et al., Adaptive-Quantization Digital Image Sensor for Low- Power Image Compression, TCASI, Vol., Issue, pp.-, Jan.. [] E. Artyomov, et al., Morton (Z) Scan Based Real-Time Variable Resolution CMOS Image Sensor, IEEE Trans. On Circuits and Systems For Video Technology, Vol., pp.-, Jul.. [] Biswas, S., Hilbert scan and image compression, th International Conference on Pattern Recognition, Vol., pp.-,. [] A. Kitchen, et al., A DPS Array With Programmable Dynamic Range,, IEEE TED, Vol., pp.-, Dec.. [] D. Martinez, et al., Generalized Boundary Adaptation Rule for Minimizing rth Power Law Distortion in High Resolution Quantization, Neural Networks, Vol., No., pp. -,.