Development of CMOS Pixel Sensors for the Inner Tracking System Upgrade of the ALICE Experiment

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1 1 Development of CMOS Pixel Sensors for the Inner Tracking System Upgrade of the ALICE Experiment Ph.D. thesis defense Tianyang WANG Directeur de thèse : Yann HU, Professeur, UdS Rapporteur externe : Marlon BARBERO, Professeur, AMU Rapporteur externe : Patrick GARDA, Professeur, UPMC Examinateur : Marc WINTER, Directeur de recherche, IPHC 25 th September, 2015

2 Outline ALICE- ITS upgrade and its design goals CMOS pixel sensors and a design strategy towards ALICE- ITS upgrade Prototype design and measurement Conclusions 2

Part 1 : ALICE-ITS upgrade and its design goals The ALICE experiment ALICE (A Large Ion Collider Experiment) at LHC

Inner tracking system (ITS) Installed at the heart of ALICE Main funckons reconstruckon of the primary and secondary

display of a Pb-Pb collision in ALICE, with the layers of the ITS highlighted.

3 Part 1 : ALICE-ITS upgrade and its design goals The ALICE experiment ALICE (A Large Ion Collider Experiment) at LHC OpKmized to study in parkcular the QGP (quark-gluon plasma) Reconstruct thousands of parkcles created by the collision Inner tracking system (ITS) Installed at the heart of ALICE Main funckons reconstruckon of the primary and secondary verkces parkcle idenkficakon and tracking of parkcles with low p T Improvement of momentum resolukon at high p T An event display of a Pb-Pb collision in ALICE, with the layers of the ITS highlighted. The ALICE detector Inner Tracking System Current ITS 3 different tech. 2 layers of silicon pixel 2 layers of silicon driw 2 layers of silicon strips * Rate limitakon: around 1kHz 3

Part 1 : ALICE-ITS upgrade and its design goals The ALICE-ITS upgrade Successful operation, but detailed and quantitative characterizakon of QGP requires High stakskcs increased luminosity (50 khz

4 Part 1 : ALICE-ITS upgrade and its design goals The ALICE-ITS upgrade Successful operation, but detailed and quantitative characterizakon of QGP requires High stakskcs increased luminosity (50 khz Pb- Pb rate) Precision measurements detector upgrade A new ITS will play an important role Significantly improved tracking and vertexing capabilikes at low p T First layer closer to IP: 39 mm => 23 mm LongShutdown2 in 2018/ layers => 7 layers silicon driw & strip => silicon pixel Material budget: from ~ 1.14% X 0 => 0.3% X 0 (inner layers) ~ 12.5 G pixel (~10 m 2 ) Pixel size: from 50 μm x 425 μm => O(30μm x 30μm) Read out Pb- Pb interackons at 50kHz Currently limited to ~ 1 khz for overall ITS Call for high performance and cheap sensor chip Very high granularity Fast readout RadiaKon tolerant Very thin Low power Cost (large area to cover) 3 Inner Barrel layers 4 Outer Barrel layers CMOS pixel sensor 4

5 Part II ALICE- ITS upgrade and its design goals CMOS Pixel Sensors (CPS) and a design strategy towards ALICE- ITS upgrade CMOS pixel sensors: basic principle and main features State- of- the- art and new challenges Design strategy of a CMOS pixel sensor adapted to the ALICE- ITS upgrade Prototype design and measurement Conclusions 5

Part 2 : CPS and a design strategy towards ALICE-ITS upgrade CMOS pixel sensor Basic principle Using a commercial CMOS process Epitaxial layer as the sensikve volume Very thin: 15-40 μm 80 e - /µm

6 Part 2 : CPS and a design strategy towards ALICE-ITS upgrade CMOS pixel sensor Basic principle Using a commercial CMOS process Epitaxial layer as the sensikve volume Very thin: μm 80 e - /µm for MIP Charge sensing: N- well/p- epi junckon Signal processing μ- circuits integrated on sensor substrate monolithic sensor Cross sec(on view of a CPS cell Main features High granularity: pixels μm 2 Low material budget: total thickness 50 µm by post- processing Industrial mass produckon: cost, reliability, fast turn- over, etc. SKll not as radiakon tolerant and fast as hybrid pixel detectors But less stringent in ALICE The potenkal of CPS is skll not fully exploited will be progressively revealed by tech. evolukon, more R&D efforts 6

Part 2 : CPS and a design strategy towards ALICE-ITS upgrade State-of-the-art and new challenges State- of- the- art CPS design: MIMOSA- 28 for STAR- PXL 0.35 μm process with high- resiskvity epi.

7 Part 2 : CPS and a design strategy towards ALICE-ITS upgrade State-of-the-art and new challenges State- of- the- art CPS design: MIMOSA- 28 for STAR- PXL 0.35 μm process with high- resiskvity epi. layer > 400 Ω cm (~ 10 Ω cm in standard) Column // readout In- pixel amplificakon & CDS Column level discriminator On- chip zero- suppression AcKve area: ~ 3.8 cm pixels & Pixel pitch = 20.7µm t r.o. ~ 200 µs 200 ns/row 150 mw/cm 2 power consumpkon JTAG programmable * MIMOSA: Minimum Ionizing particle MOS Active pixel sensor 7

Part 2 : CPS and a design strategy towards ALICE-ITS upgrade State-of-the-art and new challenges MIMOSA- 28 fully evaluated/validated: (50 μm thin) All specificakons of STAR- PXL were met 2 detectors

8 Part 2 : CPS and a design strategy towards ALICE-ITS upgrade State-of-the-art and new challenges MIMOSA- 28 fully evaluated/validated: (50 μm thin) All specificakons of STAR- PXL were met 2 detectors of 40 ladders constructed 1st vertex detector equipped with CPS at a collider exp. 1st physics data taking in early 2014 preliminary results as expected ALICE- ITS upgrade calls for some improvements System σ sp (µm) t r.o. (µs) TID (krad) Fluency (n eq /cm 2 ) Power (mw/ cm 2 ) Main limitakon of MIMOSA- 28: radiakon tolerance & read- out speed T op ( C) STAR-PXL < 4 < ITS-in < A new process with smaller feature size & a possible new sensor architecture 8

Part 2 : CPS and a design strategy towards ALICE-ITS upgrade CPS in a 0.18 µm quadruple-well process Main features High- resiskvity epitaxial layer > 1 kω cm ( 400 Ω cm in 0.

9 Part 2 : CPS and a design strategy towards ALICE-ITS upgrade CPS in a 0.18 µm quadruple-well process Main features High- resiskvity epitaxial layer > 1 kω cm ( 400 Ω cm in 0.35 µm) CCE & non- ionizing radiakon Smaller feature size & 6ML (4ML in 0.35 µm) Thinner gate oxide ionizing radiakon tolerance High- density & low power μ- circuit Deep P- well full CMOS circuitry in pixel more pixel- level intelligence possibility of new sensor architectures for fast & low power operakon Adequate radiakon tolerance for ALICE- ITS upgrade observed MIMOSA- 32, etc. 9

10 Part 2 : CPS and a design strategy towards ALICE-ITS upgrade Accelerating strategy t r.o. < 30 μs Using elongated pixel with staggered diodes reduce row number & maintain σ sp t r.o. = (read-out time per row) (row number) More parallelized readout MulKple rows read out at the same Kme At the expense of increasing proporkonally the power consumpkon In- pixel discriminakon alleviakng the dilemma between power & speed Analogue signal processing is localized within one pixel The power consuming in- pixel source follower is not required AROM concept (Accelerated Read- Out Mimosa) Only small parasikc along the analogue signal processing chain headroom for fast & power efficient design Several pf Fast & power efficient 10

11 Part 2 : CPS and a design strategy towards ALICE-ITS upgrade Our proposal: ASTRAL ASTRAL (Arom Sensor for the inner TRacker of Alice) 3 abuzed FSBB sensors mulkplexed at their output nodes AcKve area: ~ 1 3 cm 2 t r.o. ~ 20 μs ~ 400 rows 100 ns/2rows No insensikve area between 2 FSBBs Sequencer circuit at the array bozom Alongside the array for MIMOSA28 Introduce difficulty in pixel array layout cross- like control signal distribukon 11

12 Part 2 : CPS and a design strategy towards ALICE-ITS upgrade Our proposal: ASTRAL ASTRAL (Arom Sensor for the inner TRacker of Alice) Upstream Opt. of charge sensing and pre- amplifying The integrakon of signal discriminakon in pixel Downstream: digital processing data compression data transfer chip steering. The thesis contributes to the upstream development of ASTRAL via the AROM prototyping 12

13 Part III ALICE- ITS upgrade and its design goals CMOS pixel sensors and a design strategy towards ALICE- ITS upgrade Prototype design and measurement Feasibility study of CPS with in- pixel discriminator: AROM- 0 Prototype design and measurement Pixel performance opkmizakon: AROM- 1 Pixel design and prototype measurement Conclusions 13

Design challenges of the AROM prototype SpecificaKons driven by ASTRAL row control signals Pixel floor plan Area: 22 μm 33 μm (as the baseline for AROM) σ sp ~ 5 μm no complex circuitry allowed

14 Design challenges of the AROM prototype SpecificaKons driven by ASTRAL row control signals Pixel floor plan Area: 22 μm 33 μm (as the baseline for AROM) σ sp ~ 5 μm no complex circuitry allowed Staggered diode placement & cross- like control signal distribukon layout difficulkes High precision < 1 mv set by its upstream noise floor (charge sensing and pre- amplifying) Fast operakon A- D conversion Kme < 100 ns MulK- dimensional tradeoffs for the discriminator design diode 14

15 The proposed discriminator structure Speed considerakon mulkple stages => fast for a given total amplifying gain G 1- stage n- stage Precision considerakon common noise rejeckon differenkal architecture latch offset: O(10 mv) => to be validated sufficient gain before latch (> 30) amplifier offsets: O(5 mv) offset cancellakon techniques impact on circuit complexity In prackce, 2 n 4 & 4 A

16 Pixel design: V1 16

17 Pixel V1: sensing system e- e - * by A. IPHC risk for RTS (Random Telegraph Signal) Sensing system: sensing diode + pre- amplifier Established in a previous prototype with pure analog pixels Expected performance CVF: μv/e - noise: 1 mv ~ 20 e - set the noise constraint on the discriminator 17

18 Pixel V1: discriminator principle Q Threshold injeckon 2 amps + latch + dig. buffer Offset compensated calib: offset memorizakon read: signal tracking Signal extracted by CDS V Q,read (N+1) V Q,calib (N) Threshold = V ref2 V ref1 latch reset decision making V Q,calib (N) = V ref1 V Q,read (N+1) = V ref1 + V sig. 18

19 #

20 Pixel V1: latch design Dynamic configurakon Fast & no stakc current σ offset : 2.2 mv (simulakon) mainly from M1 & M2 negligible when referred to the discriminator input Latch offset distribukon 20

21 Pixel design: V2 21

22 Pixel V2 A more compact design 2 amp. directedly cascaded Offset memorized at inputs 2 MIM cap. (using 4 th 6 th ML) 1 cap. less than V1 Less area required read calib More room for metal roukng Same operakon Kming as V1 Same amplifier and latch as V1 2- order loop during calib stability issue OscillaKon during calib may degrade the noise performance Sezling verified by simulakon OscillaKon negligible awer 10 ns 22

signals shared by 2 neighboring rows introduce layout difficulkes

23 Pixel V2 2 2 pixels 66 µm 44 µm 2 different layouts realized Single- row readout Double- row readout Transverse control signals shared by 2 neighboring rows introduce layout difficulkes due to staggered diode placement more cross coupling 66 µm 2 2 pixels 44 µm 23

24 Prototype design: AROM-0 6 pixel arrays 3 different discri. circuit (V1, V2 & V3) implemented in separate arrays offset cancellakon techniques vs. circuit complexity 1 double- row read- out array with pixel V2 explore the readout accelerakon 2 pixel arrays to validate the latch performance digital output pixels sensing + pre- amplifying + discriminakon 32 4 modified pixels Sensing + pre- amplifying + ana. Buffering Discriminator implemented, but not used 24

AROM-0: laboratory measurement 1. Sensing system: sensing diode + pre- amplifier Employing the 4 analogue columns CVF (charge to voltage conversion factor) CCE (charge colleckon efficiency) 2.

25 AROM-0: laboratory measurement 1. Sensing system: sensing diode + pre- amplifier Employing the 4 analogue columns CVF (charge to voltage conversion factor) CCE (charge colleckon efficiency) 2. Full in- pixel circuitry Sensing system + discriminator FuncKon and noise performance of pixel 3. Noise contribukon from in- pixel discriminator 4. Noise contribukon from latch Offset dispersion agree with simulakon? 25

26 AROM-0: laboratory measurement 1. Sensing diode + pre- amplifier 55 Fe radioackve source: 5.9 kev X- rays ~1640 e - CalibraKon peak the full colleckon of 1640 e CVF V1: 52 μv/e - V2: 57 μv/e - CCE: ~ 75 % for 3 3 pixel cluster MPV signal from 3 3 cluster MPV signal from 3 3 cluster Pixel V1 Pixel V2 26

27 AROM-0: laboratory measurement 2. Full in- pixel circuitry Nominal read- out speed: 100 ns/row (or 100 ns/2rows) S curves of full in- pixel circuitry of V1 Threshold distribu6on (Fixed PaDern Nnoise) Array ID Avg. TN (mv) FPN (mv) Total noise (mv) ENC (e ) V V V2(2-row) * * ENC value eskmated based on the CVF of single- row read- out V2 Temporal noise (TN) distribu6on RTS from pre- amp 27

curves strongly distorted at nominal speed caused by cross coupling: pixel_out

28 AROM-0: laboratory measurement 3. In- pixel discriminator Sensing system replaced by a reference voltage S curves strongly distorted at nominal speed caused by cross coupling: pixel_out Vref could be avoided with more careful layout design Noise evaluated at lower speeds V1 100 ns/row V1 200 ns/row V1 400 ns/row 28

29 AROM-0: laboratory measurement 3. In- pixel discriminator Array ID V1 V2 V2 (2-row) Speed Avg. TN (mv) FPN (mv) Total noise (mv) 200 ns/row ns/row ns/row ns/row ns/row ns/row ns/2rows ns/2rows ns/2rows

30 AROM-0: laboratory measurement 3. In- pixel discriminator Array ID V1 V2 V2 (2-row) Speed Avg. TN (mv) FPN (mv) Total noise (mv) 200 ns/row ns/row ns/row ns/row ns/row ns/row ns/2rows ns/2rows ns/2rows Discriminator noise contribukon ~ 1mV should be improved 30

31 AROM-0: laboratory measurement 3. In- pixel discriminator Array ID V1 V2 V2 (2-row) Speed Avg. TN (mv) FPN (mv) Total noise (mv) 200 ns/row ns/row ns/row ns/row ns/row ns/row ns/2rows ns/2rows ns/2rows FPN decreases with speed unkl 400 ns/row The low- speed results may imply the discriminator FPN potenkal 31

32 AROM-0: laboratory measurement 3. In- pixel discriminator Array ID V1 V2 V2 (2-row) Speed Avg. TN (mv) FPN (mv) Total noise (mv) 200 ns/row ns/row ns/row ns/row ns/row ns/row ns/2rows ns/2rows ns/2rows V1 has the potenkal for very low FPN, assuming a more careful layout 32

33 AROM-0: laboratory measurement 4. Latch circuit evaluakon Illustra6on of a pixel used for latch evalua6on (pixel V2) Noise values of the latch circuit for a array Common input (V) Avg. TN (mv) FPN (mv) Total noise (mv) FPN well predicted by simulakon (2.2 mv) Noise increases with common input, but total noise remains < 3 mv The latch is not a major noise source 33

34 Short summary for AROM-0 FuncKon of small pixels with in- pixel discriminator validated Fast operakon validated 100 ns/row (or 100 ns/2rows) Row processing twice as fast as MIMOSA- 28 (200 ns/row) Noise performance evaluated Encouraging (~ 30 e- ) Improvement needed (Random Telegraph Signal, discriminator noise, etc.) 34

35 Pixel performance optimization - The AROM-1 pixel development 1. To opkmize the pixel designs based on the experience of AROM To verify the pixel performance in a larger array with 2- row readout The AROM- 1 prototypes 35

Part 3 : prototype design and measurement AROM-1 description Pixel array of 64 64 56 col. of pure digital pixels 8 col.

36 Part 3 : prototype design and measurement AROM-1 description Pixel array of col. of pure digital pixels 8 col. of pixels with analogue output capability Double- row rolling shuzer readout DACs (reference & biasing), sequence generator, slow control via JTAG registers. approaching the ASTRAL sensor Five pixel (chip) versions AROM- 1 A/B/C: derived from AROM- 0 V2 MiKgated RTS noise from pre- amp Study consists in layout design AROM- 1 E/F: derived from AROM- 0 V1 * Chips designed in collaboration with H. Pham, A. Dorokhov, I. Valin, A. Himmi, F. IPHC A: 22x33 µm² (similar layout as AROM- 0) B: 22x33 µm² (opkmized layout) C: 24x33 µm² (impact of pixel pitch) MiKgated RTS noise from pre- amp Explore the potenkal for low noise & low power E: 22x33 µm² F: 27x27 µm² 36

37 Design improvements in AROM-1 E/F 37

38 TN optimization Biasing improved by removing the NMOS source followers Vref1 & Vref2: ~1.2 V => ~ 0.75 sub- threshold => linear region Before modificalon (AROM- 0 V1) 1.8 V / 0V Main TN source 1.2 V 0.7 V less thermal noise ~ 70 % TN reduckon for discriminator Simulated noise dispersion ARer modificalon 0.75V 38

39 Power optimization (1/2) A modified operakon sequence allows to trade BW for low power Before modificalon (AROM- 0 V1) ARer modificalon 39

40 Power optimization (2/2) A modified operakon sequence allows to trade BW for low power Before modificalon (AROM- 0 V1) ARer modificalon Comparison of amplifiers used in different chips (simula6on) Chip Amplifier Current Gain BW AROM-0 1 st and 2 nd stages 15 µa ~ ff AROM-1 E 1 st and 2 nd stages 7 µa ~ ff AROM-1 F 1 st stage 7 µa ~ ff 2 nd stage 3 µa ~ ff 40

41 AROM-1: Laboratory measurement 41

42 Part 3 : prototype design and measurement AROM-1: Laboratory measurement Sensing diode + pre- ampliﬁer: 55Fe X- ray source CVF 44 μv/e- for both AROM- 1 E/F CCE: Seed pixel: ~ 40 % 4 pixels with the highest signal: ~ 90 % Calibration peak AROM- 1 E AROM- 1 F 42

43 AROM-1: Laboratory measurement Full in- pixel circuitry Maximum speed: 160 ns/2rows (100 MHz clock) due to DAQ limitakon Chip Avg. TN FPN Total noise ENC ID (mv) (mv) (mv) (e ) AROM-1 E AROM-1 F ENC values improved (~ 30 e - for AROM- 0) Excellent FPN performance Improved discriminator design RTS mikgakon Pre- amplifier modificakon TN distribu6on 43

44 AROM-1: Laboratory measurement In- pixel discriminator Chip ID Avg. TN (mv) FPN (mv) Total noise (mv) AROM-1 E AROM-1 F Noise opkmizakon validated contribute marginally to the total noise baseline design for the future 44

45 Part 4 : conclusions Conclusions This thesis contributes to the upstream development of the ASTRAL sensor 1. The AROM concept validated feasible to have high performance discriminator in a small pixel 2. Fast operakon validated Fast signal processing 100 ns/row or 100 ns/2rows AROM- 0: measured AROM- 1: 160 ns/2rows achieved, full speed to be validated Double- row read- out 3. Low noise and very low power achieved Noise comparable (or even bezer) w.r.t. the more complex col. level discriminator StaKc current consumpkon down to the A- D stage almost an order of magnitude lower Chip ID Proc. (µm) Current (µa/discri.) Avg. TN (mv) FPN (mv) note MIMOSA ~ 70 * row col. dis. & complex E ~ row in- pixel dis. & AROM F ~ simple * 50 µa of addikonal current is needed for analog buffering 45

46 Part 4 : conclusions Conclusions This work follows one of several approaches to push forward the CPS potenkal Proc. Read-out architecture This work MIMOSA like MIMADC ALPIDE Pixel- level discriminator 2- row Rolling shuzer Column- level discriminator 0.18 µm CMOS 1- row rolling shuzer Pixel- level 3- bit ADC Data driven Pixel- level discriminator Speed 100 ns/2rows* 200 ns/2rows 180 ns/row Sig. durakon ~ 4 μs Power/pixel 30 μw ~ 200 μw ~ 200 μw ~ 40 nw conkn. ackve σ sp ~ 5 μm ~ 5 μm ~ 4 μm ~ 5 μm Noise of A-D stage ~ 0.3 mv ~ 0.3 mv ~ 0.8 mv Sensor ENC ~ 20 e- 20 e ~ 20 e- * to be validated 46

47 Publications and Communications T. Wang, H. Pham, A. Dorokhov, M. Goffe, I. Valin, A. Himmi, F. Morel, C. Hu- Guo and Y. Hu, CMOS Digital Pixels: Design Study for Low- Noise and Power Efficiency, Poster at Ecole IN2P3 de Microélectronique, 2015 T. Wang, H. Pham, G. Claus, A. Dorokhov, M. Goffe, I. Valin, A. Himmi, F. Morel, C. Hu- Guo, Y. Hu and M. Winter, Development of CMOS Pixel Sensors Featuring Pixel- Level DiscriminaKon for the ALICE- ITS Upgrade, Oral presentalon at The Technology and InstrumentaKon in ParKcle Physics, 2014, published in Proceedings of Science T. Wang, W. Zhao, H. Pham, C. Hu- Guo, A. Dorokhov and Y. Hu, Development of CMOS Pixel Sensors with digital pixel dedicated to future parkcle physics experiments, Poster at Topical Workshop on Electronics for ParKcle Physics, 2013, published in Journal of InstrumentaKon T. Wang, H. Pham, A. Dorokhov, C. Hu- Guo and Y. Hu, A CMOS Pixel Sensor with In- Pixel DiscriminaKon for ALICE- ITS Upgrade, Poster at Ecole IN2P3 de Microélectronique, 2013 C. Hu- Guo, J. Baudot, G. Bertolone, A. Besson, G. Claus, C. Colledani, A. Dorokhov, G. Dozière, W. Dulinski, X. Fang, M. Goffe, A. Himmi, K. Jaaskelainen, F. Morel, S. Senyukov, M. Specht, M. Szelezniak, H. Pham, I. Valin, T. Wang and M. Winter, Development of the MISTRAL & ASTRAL sensors for the upgrade of the Inner Tracking System of the ALICE experiment at LHC, Oral presentakon at IEEE Nuclear Science Symposium and Medical Imaging Conference, 2013, published in the conference proceedings F. Morel, C. Hu- Guo, G. Bertolone, G. Claus, C. Colledani, A. Dorokhov, G. Doziere, W. Dulinski, X. Fang, M. Goffe, A. Himmi, K. Jaaskelainen, S. Senyukov, M. Specht, M. Szelezniak, H. Pham, I. Valin, T. Wang and M. Winter, MISTRAL & ASTRAL: two CMOS Pixel Sensor architectures suited to the Inner Tracking System of the ALICE experiment, Oral presentakon at Topical Workshop on Electronics for ParKcle Physics, published in Journal of InstrumentaKon 47

48 Thank you for your attention 48

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

PICSEL group Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments Serhiy Senyukov (IPHC-CNRS Strasbourg) on behalf of the PICSEL group 7th October 2013 IPRD13,