CMOS Pixel Sensors for Charged Particle Tracking : Achieved Performances and Perspectives

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Jeffrey York
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1 Copenhagen, 6 August 009 CMOS Pixel Sensors for Charged Particle Tracking : Achieved Performances and Perspectives Marc Winter (IPHC/Strasbourg) on behalf of IPHC/Strasbourg IRFU/Saclay collaboration More information on IPHC Web site: Motivation of the talk : 11 years since the 1st CMOS sensor was proposed for vertexing (at the ILC) numerous other applications of CMOS sensors have emerged since then HEP groups in the US & Europe are presently active in CMOS sensor R&D Scope of the talk : R&D motivations performances achieved with CMOS pixel sensors current applications perspectives with D and D sensors CMOS pixel sensors, 1

.5.5 115 0 5 0 5 40 45 - What is the ILC Project?

energy up to 1 TeV ; 1 km long site; it will deepen discoveries made at LHC and extend the experimental sensitivity to new phenomena underlying

2 What is the ILC Project? ILC next large scale accelerator after LHC Physics 00 it is an electron - positron linear collider : c.m. energy up to 1 TeV ; 1 km long site; it will deepen discoveries made at LHC and extend the experimental sensitivity to new phenomena underlying the history of Universe (laws of Nature) and its present mysteries (Dark Matter, Dark Energy) ILC design expected to be technically ready for construction 01 (... R&D started 10 years ago...) Detector concept should mature synchronously (time scale less tight as LHC) CMOS pixel sensors,

.5.5 115 0 5 0 5 40 45 - The Quest for Highly Precise & Sensitive Detectors ILC is a high precision machine : electron - positron collisions are relatively (compared to LHC) background free physics

3 The Quest for Highly Precise & Sensitive Detectors ILC is a high precision machine : electron - positron collisions are relatively (compared to LHC) background free physics conditions of elementary interactions are particularly well defined and tunable Very high precision/sensitivity studies accessible if detectors are extremely sensitive Vertex Detector with unprecedented performances Major requirements : Resolution on vertex position O(10) µm Ionising radiation : O(100) krad / yr O(10 ) hit pixels /cm /10 µs (inner layer) Non-ionising radiation O(10 11 )n eq /cm /yr from e ± BS and O(10 10 )n eq /cm /yr from neutron gas CMOS pixel sensors,

.5.5 115 0 5 0 5 40 45 - Granularity and Transparency How to achieve high spatial resolution : small pixels (pitch) and reduced material ( weight) Figure of merit : σ ip = a b/p t b governs

4 Granularity and Transparency How to achieve high spatial resolution : small pixels (pitch) and reduced material ( weight) Figure of merit : σ ip = a b/p t b governs low momentum ( 0 % particles < 1 GeV/c) a governs high momentum Accelerator a (µm) b (µm GeV ) LEP 5 70 SLD 8 LHC 1 70 RHIC-II 1 19 ILC < 5 < 10 b dominated ւ a dominated CMOS pixel sensors, 4

5 Granularity and Transparency How to achieve high spatial resolution : small pixels (pitch) and reduced material ( weight) Figure of merit : σ ip = a b/p t b governs low momentum ( 0 % particles < 1 GeV/c) a governs high momentum Accelerator a (µm) b (µm GeV ) LEP 5 70 SLD 8 LHC 1 70 RHIC-II 1 19 ILC < 5 < 10 b dominated ւ a dominated Existing pixel technologies cannot do the job : CCDs are too slow and radiation soft Hybrid Pixel Sensors are not granular and thin enough CMOS pixel sensors, 4-a

.5.5 115 0 5 0 5 40 45 - Main Features and Advantages of CMOS Sensors P-type low-resistivity Si hosting n-type charge collectors signal created in epitaxial layer (low doping): Q 80 e-h / µm signal

6 Main Features and Advantages of CMOS Sensors P-type low-resistivity Si hosting n-type charge collectors signal created in epitaxial layer (low doping): Q 80 e-h / µm signal 1000 e charge sensing through n-well/p-epi junction excess carriers propagate (thermally) to diode with help of reflection on boundaries with p-well and substrate (high doping) Prominent advantages of CMOS sensors: granularity: pixels of µm high spatial resolution low mat. budget: sensitive volume µm total thickness 50 µm Signal processing µcircuits integrated in the sensors compacity, high data throughput, flexibility, etc. other attractive aspects: cost, multi-project run frequency, T room operation, etc. Attractive balance between granularity, mat. budget, rad. tolerance, r.o. speed and power dissipation Limitations Very thin sensitive volume impact on signal magnitude (mv!) vey low noise FEE Sensitive volume almost undepleted impact on radiation tolerance & speed Commercial fabrication fab. param. (doping profile, etc.) not optimal for charged part. detection etc. CMOS pixel sensors, 5

7 Achieved Performances with Analog Output Sensors CMOS pixel sensors, 6

.5.5 115 0 5 0 5 40 45 - M.I.P. Detection with CMOS Sensors 100 chips (M1, M, M4, M5, M8, M9, M11, M14, M15, M16, M17, M18) tested on H.E.

8 M.I.P. Detection with CMOS Sensors 100 chips (M1, M, M4, M5, M8, M9, M11, M14, M15, M16, M17, M18) tested on H.E. beams since 001 at CERN & DESY, mounted on Si-strip telescope (calibrated with 55 Fe) well established perfo. (analog output): Example of well performing technology: AMS 0.5 µm OPTO 14 & 0 µm epitaxy thickness N 10 e ENC S/N 0 0 (MPV) at room Temperature Technology without epitaxy also performing well : very high S/N but large clusters (hit separation ց) Macroscopic sensors : MIMOSA-5 ( 1.7x1.7 cm ; 1 Mpix) ; MIMOSA-0 (1x cm ; 00 kpix) ; MIMOSA-17 (0.76x0.76 cm ; 65 kpix) ; MIMOSA-18 (0.55x0.55 cm ; 56 kpix) CMOS pixel sensors, 7

9 Detection Efficiency & Spatial Resolution Detection efficiency: Ex: MIMOSA-9 data (0, 0 & 40 µm pitch) ǫ det % repeatedly observed at room temperature (fake rate 10 5 ) T oper. 40 C Efficency % Efficency vs Temperature Small Diode pitch 0 small diode chip 1 pitch 0 small diode chip 1 pitch 40 small diode chip 1 pitch 0 small diode chip pitch 0 small diode chip pitch 40 small diode chip Single point resolution versus pixel pitch: Mimosa resolution vs pitch o Temp ( C) clusters reconstructed with eta-function, exploiting charge sharing between pixels (1-bit ADC) σ sp 1 µm (10 µm pitch) µm (40 µm pitch) bit ADC simul. σ sp µm (0 µm pitch) measured binary output resolution (MIMOSA-16, -): σ sp.5 & 4.5 µm (18.4 & 5 µm pitch) pitch (microns) CMOS pixel sensors, 8

10 Radiation Tolerance: Condensed Summary Ionising radiation tolerance (chips irradiated with 10 kev X-Rays) : Pixels modified against hole accumulations (thick oxide) and leakage current increase (guard ring) MIMOSA-15 tested with 5 GeV e at DESY after 10 kgy exposure : Preliminary results T = - 0 C, t r.o. 180 µs t r.o. << 1ms crucial at T room Integ. Dose Noise S/N (MPV) Detection Efficiency ± ± % 1 MRad 10.7 ± ± ± 0.04 % Non-ionising radiation tolerance (chips irradiated with O(1 MeV) neutrons): MIMOSA-15 (0 µm pitch) tested on DESY e beams : Preliminary results T = - 0 C, t r.o. 700 µs Fluence (10 1 n eq /cm ) (5/) 5.8 (4/) n eq /cm values with standard & soft cuts S/N (MPV) 7.8 ± ± ± ±. 7.5 ±. Det. Efficiency (%) ± ± ± 84. ±. MIMOSA-18 (10 µm pitch) tested at CERN-SPS (10 GeV π beam) : Preliminary results T = - 0 C, t r.o. ms Fluence (n eq /cm ) Conclusion : parasitic 1 kgy γ gas N ր Q clust (e ) S/N (MPV) 8.5 ± ± ± 0. Det. Efficiency (%) 99.9 ± ± ± 0.1 obs. tolerance: O(10 kgy) & 10 1 n eq /cm (0 µm pitch) > n eq /cm (10 µm pitch) further studies needed : tolerance vs diode size, r.o. speed, digital output,..., annealing?? CMOS pixel sensors, 9

.5.5 115 0 5 0 5 40 45 - System Integration

with MIMOSA chips (coll. with LBL): STAR ( 0.

11 System Integration Industrial thinning (via STAR coll. at LBNL) MIMOSA-18 ( mm thinned to 50 µm) Devt of ladder equipped with MIMOSA chips (coll. with LBL): STAR ( 0. % X 0 ) ILC (< 0. % X 0 ) Perspectives? accessibility of industrial thinning + post-processing of high-res substrate stitching alleviates material budget of flex cable CMOS pixel sensors, 10

.5.5 115 0 5 0 5 40 45 - Applications of Sensors with Analog Output Beam telescope of the FP6 project EUDET arms of planes (plus 1 high resolution plane) σ extrapol.

(see later) Several other applications : MIMOSA sensor R&D : Pixel telescope of Strasbourg (TAPI) STAR (RHIC) : telescope ( MIMOSA-14) inside apparatus (007) background meast, no

12 Applications of Sensors with Analog Output Beam telescope of the FP6 project EUDET arms of planes (plus 1 high resolution plane) σ extrapol. 1 µm EVEN with e ( GeV, DESY) frame read-out frequency O(10 ) Hz running since 07 CERN-SPS & DESY (numerous users) evolution towards 10 4 frames/s in 009, using binary output sensors (see later) Several other applications : MIMOSA sensor R&D : Pixel telescope of Strasbourg (TAPI) STAR (RHIC) : telescope ( MIMOSA-14) inside apparatus (007) background meast, no pick-up! CBM (FAIR) : MVD demonstrator (double-sided layers) to be used for high precision tracking in HADES (GSI) 010 Spin-offs : beta imaging, hybrid photo-detector, dosimetre,... CMOS pixel sensors, 11

13 Improving the Read-Out Speed with Digital Output Sensors CMOS pixel sensors, 1

.5.5 115 0 5 0 5 40 45 - Development Strategy of Fast CMOS Sensors Target value : read-out time 0 - - - - 00 µs sensors organised in pixel columns read out in

µcircuit in each pixel 1 discriminator ending each column MIMOSA-8 (004), MIMOSA-16 (006), MIMOSA- (007/08) Ø µcircuits & output memories : SUZE-01 (007) 4 5

14 Development Strategy of Fast CMOS Sensors Target value : read-out time µs sensors organised in pixel columns read out in // R&D organisation : simultaneous R&D lines types of µcircuits MIMOSA- architecture of pixel arrays organised in columns read out in // CDS and pre-amp µcircuit in each pixel 1 discriminator ending each column MIMOSA-8 (004), MIMOSA-16 (006), MIMOSA- (007/08) Ø µcircuits & output memories : SUZE-01 (007) 4 5 bits ADCs (1000 ADC featuring µm per sensor! ) potentialy replacing each discriminator σ sp < µm (4 bits) µm (5 bits) for 0 µm pitch CMOS pixel sensors, 1

.5.5 115 0 5 0 5 40 45 - Performances of a Large Prototype with Digitised Output MIMOSA- : fabricated in 007/08 (coll. with IRFU/Saclay) 16 col. of 576 pixels (18.4 µm pitch, integrated CDS ) 18 col.

15 Performances of a Large Prototype with Digitised Output MIMOSA- : fabricated in 007/08 (coll. with IRFU/Saclay) 16 col. of 576 pixels (18.4 µm pitch, integrated CDS ) 18 col. ended with an integrated discriminator integrated JTAG controller Tests at CERN-SPS ( 10 GeV π ) in 008 results of different sub-arrays M digital S6. Efficiency, Fake rate and Resolution S6 M, S5 Mbis & S Mbis digital Efficiency Mbis digital fake hit rate Efficiency (%) Resolution (um) Average fake hit rate/pixel/event Efficiency (%) S6 MIMOSA S5 MIMOSAbis S MIMOSAbis Average fake hit rate/pixel/event S6 MIMOSA S5 MIMOSAbis S MIMOSAbis Discri. Threshold (mv) S/N S/N Architectures of pixel (integrated CDS ) and of full chain made of columns ended with integrated discri. validated at real scale CMOS pixel sensors, 14

.5.5 115 0 5 0 5 40 45 - Zero Suppression Micro-Circuit : SUZE-01 Test Results 1st chip (SUZE-01) with integrated Ø and output memories (no pixels) : step, raw by raw, logic : step-1 (inside blocks

16 Zero Suppression Micro-Circuit : SUZE-01 Test Results 1st chip (SUZE-01) with integrated Ø and output memories (no pixels) : step, raw by raw, logic : step-1 (inside blocks of 64 columns) : identify up to 6 series of 4 neighbour pixels per raw delivering signal > discriminator threshold step- : read-out outcome of step-1 in all blocks and keep up to 9 series of 4 neighbour pixels 4 output memories (51x16 bits) taken from AMS I.P. lib. adapted to 64 columns surface.9.6 mm Test results summary : designed & fabricated in 07 (lab) tests completed by Spring 08 design performances reproduced up to 1.15 design read-out frequency (T room ) : noise values as predicted, no pattern encoding error, can handle > 100 hits/frame at rate > 10 4 frames/s Still to do : improve radiation tolerance (SEU, latch-up ) of ouput memories CMOS pixel sensors, 15

.5.5 115 0 5 0 5 40 45 - MIMOSA-6 : 1st Sensor with Integrated Ø MIMOSA-6 final sensor for EUDET telescope MIMOSA- (binary outputs) complemented with Ø (SUZE-01) Active surface : 115 columns of 576

17 MIMOSA-6 : 1st Sensor with Integrated Ø MIMOSA-6 final sensor for EUDET telescope MIMOSA- (binary outputs) complemented with Ø (SUZE-01) Active surface : 115 columns of 576 pixels (1. x 10.6 mm ) Pitch : 18.4 µm 0.7 million of pixels σ sp.5 µm Integration time 110 µs 10 4 frames / second suited to > 10 6 particles/cm /s Ø in 18 groups of 64 col. allowing 9 pixel strings / raw Sensor full dimensions : 1 x 1 mm Data throughput: 1 output at 80 Mbits/s or outputs at 40 Mbits/s Fabricated in AMS-0.5 technology: Sensor currently being tested preliminary test results satisfactory (see next slide) Sensor foreseen to equip several beam telescopes (including ATLAS) Architecture is baseline for STAR, CBM and ILC vertex detectors CMOS pixel sensors, 16

.5.5 115 0 5 0 5 40 45 - MIMOSA-6 : Preliminary Lab Test Results MIMOSA-6 final sensor for EUDET telescope 9 sensors mounted on interface board and tested with/without 55 Fe source Noise performance

18 MIMOSA-6 : Preliminary Lab Test Results MIMOSA-6 final sensor for EUDET telescope 9 sensors mounted on interface board and tested with/without 55 Fe source Noise performance assessment performed separately for each of the 4 groups of 88 columns, at nominal r.o. speed Typical value of pixel (i.e. temporal noise) mv Typical value of FPN (discriminator) noise mv Results are identical to MIMOSA- values Ø logic seems to work as foreseen sensors mounted as DUT on EUDET beam telescope Sensor is operational at nominal speed Next steps : Commission final version of EUDET beam telescope at CERN-SPS (Septembre 09) Cross-check radiation tolerance Yield investigate stitching? Extend design to various vertex detectors (STAR, CBM, ILC, etc.) CMOS pixel sensors, 17

.5.5 115 0 5 0 5 40 45 - Extensions of MIMOSA- & MIMOSA-6 to STAR 1st generation sensor for the HFT-PIXEL of STAR (PHASE-1): full scale extension of MIMOSA- (no Ø)

mm integration time : 640 µs designed and fabricated in 008 currently under test at LBNL + 9 ladders to equip with 10 sensors thinned to 50 µm (1/4 of PIXEL) 1st

19 Extensions of MIMOSA- & MIMOSA-6 to STAR 1st generation sensor for the HFT-PIXEL of STAR (PHASE-1): full scale extension of MIMOSA- (no Ø) 640x640 pixels (0 µm pitch) active surface : 19. x 19. mm integration time : 640 µs designed and fabricated in 008 currently under test at LBNL + 9 ladders to equip with 10 sensors thinned to 50 µm (1/4 of PIXEL) 1st physics data expected in 011 Final HFT-PIXEL sensor : MIMOSA-6 with active surface 1.8 & improved rad. tolerance 115 col. of 104 pixels (1. x 18.8 mm ) Pitch : 18.4 µm 1.1 million pixels Integration time 00 µs Design in 009 fab. early 010 1st physics data expected in 01 CMOS pixel sensors, 18

20 ILC Vertex Detector R&D Goals Sensor requirements defined w.r.t. ILD VTX geometries alternative geometries : 5 single-sided layers double-sided layers (mini-vectors) pixel array read-out perpendicular to beam lines Prominent specifications : read-out time target values (continuous read-out version) : SL1/SL /SL /SL4 /SL5 DL1 / DL / DL single-sided : 5 / 50 / 100 / 100 / 100 µs double-sided : 5 5 / / µs σ sp < µm (partly with binary outputs) full ladder material budget in sensitive area ( 50 µm thin sensors) : single-sided : < 0. % X 0 double-sided : 0. % X 0 P diss W/cm 1/50 duty cycle (5 Hz, 1 ms long, bunch train frequency) CMOS pixel sensors, 19

.5.5 115 0 5 0 5 40 45 - From MIMOSA-6 to the ILC Design Move from AMS-0.5 µm to feature size 0.

Outer layers (t int 100 µs) : Inner layers (t int 5-50 µs) : pitch 5 µm (need phys. studies ) dou

21 From MIMOSA-6 to the ILC Design Move from AMS-0.5 µm to feature size 0.18 µm improved clock frequency, more metal layers, more compact peripheral circuitry, etc. Outer layers (t int 100 µs) : Inner layers (t int 5-50 µs) : pitch 5 µm (need phys. studies ) double-sided r.o. twice shorter (= faster) columns 4-bit ADC σ sp µm pitch 15 µm 576 col. of 576 pixels x cm binary r.o. σ sp µm 1600 columns of 0 pixels 4x0.95 mm CMOS pixel sensors, 0

.5.5 115 0 5 0 5 40 45 - System Integration : PLUME Project PLUME project Pixelised Ladder using Ultra-light Material Embedding Objectives : achieve a double-sided ladder prototype by 01 evaluate

22 System Integration : PLUME Project PLUME project Pixelised Ladder using Ultra-light Material Embedding Objectives : achieve a double-sided ladder prototype by 01 evaluate benefits of -sided concept (mini-vectors) : σ sp, alignment, shallow angle pointing Collaboration: Bristol - DESY - Oxford - Strasbourg Synergy with Vertex Detector of CBM/FAIR Perspective: to be integrated in FP-7 project called DEVDET (proposal in preparation) interest for (s)lhc experiments? CMOS pixel sensors, 1

.5.5 115 0 5 0 5 40 45 - System Integration : PLUME Project 1st step (009) : pairs of MIMOSA-0 sensors (4x1 cm, 50 µm thin) mounted on flex cable, assembled on SiC (8 %) support total material budget

23 System Integration : PLUME Project 1st step (009) : pairs of MIMOSA-0 sensors (4x1 cm, 50 µm thin) mounted on flex cable, assembled on SiC (8 %) support total material budget 0.5 % X 0 SiC foam sensors glue flex 0.18 % 0.11 % 0.0 % 0.9 % beam tests at CERN-SPS in Novembre nd step (009 01) : sets of 6 MIMOSA-6 sensors (x1 cm, 50 µm thin) mounted on flex cable, assembled on SiC support total material budget 0. % X 0 (stitching???) prototype for innermost layer CMOS pixel sensors,

24 Evolution of CMOS Sensors CMOS pixel sensors,

.5.5 115 0 5 0 5 40 45 - High Resistivity Sensitive Volume Advantages : faster charge collection (< 10 ns ) faster frame read-out frequency shorter minority charge carrier path length improved

25 High Resistivity Sensitive Volume Advantages : faster charge collection (< 10 ns ) faster frame read-out frequency shorter minority charge carrier path length improved tolerance to non-ionising radiation Exploration of 0.6 µm techno: 15 µm thick epitaxy ; V dd 5 V ; ρ O(10 )Ω cm MIMOSA-5 : fabricated in 008 & tested with 106 Ru (β) source before/after O(1 MeV) neutron irradiation 0 µm pitch, + 0 C, 160 µs r.o. time fluence 0. / 1. / 10 1 n eq /cm tolerance improved by > 1 order of mag. need to confirm ǫ det (uniformity!) with beam tests (CERN-SPS in July 09) Exploration of a new VDSM technology with depleted substrate : project LePIX project driven by CERN for SLHC trackers (also attractive for CBM, ILC and CLIC Vx Det.) 1st prototypes by the end of 009 thinning and post-processing of substrate? CMOS pixel sensors, 4

.5.5 115 0 5 0 5 40 45 - Using DIT to Improve CMOS Sensor Performances D Integration Techno.

processes alleviate constraints on transistor type inside pixel Split signal collection and processing functionnalities : Tier-1: charge collection system Tier-: analog signal processing Tier-: mixed

26 Using DIT to Improve CMOS Sensor Performances D Integration Techno. allow integrating high density signal processing µcircuits inside small pixels DIT are expected to be particularly beneficial for CMOS sensors : combine different fab. processes alleviate constraints on transistor type inside pixel Split signal collection and processing functionnalities : Tier-1: charge collection system Tier-: analog signal processing Tier-: mixed and digital signal processing Tier-4: data formatting (electro-optical conversion?) Use best suited technology for each Tier : Tier-1: epitaxy (depleted or not), deep N-well? Tier- & -4 : digital process (nb of metal layers), feature size fast laser (VOCSEL) driver, etc. Tier-: analog, low I leak, process (nb of metal layers) CMOS pixel sensors, 5

.5.5 115 0 5 0 5 40 45 - Ex: Delayed R.O. Architecture for the ILC Vertex Detector Run in Chartered - Tezzaron technology Tier-1 -Tier run with high-res substrate (allows m.i.p.

27 Ex: Delayed R.O. Architecture for the ILC Vertex Detector Run in Chartered - Tezzaron technology Tier-1 -Tier run with high-res substrate (allows m.i.p. detection) -Tier architecture compactified in -Tier chip feature size = 10 nm design foreseen for smaller feature size Try D architecture based on small pixel pitch, motivated by : Tier- < µm single point resolution with binary output probability of > 1 hit per train << 10 % 1 µm pitch : σ sp.5 µm & 5 % proba. of > 1 hit/train Split signal collection and processing functionnalities : Tier-1A: sensing diode & amplifier Tier-1B: shaper & discriminator Tier-: time stamp (5 bits) + overflow bit & read-out delayed r.o. Architecture prepares for -Tier perspectives : Tier-1: CMOS process adapted to charge collection Tier-: CMOS process adapted to analog & mixed signal processing Tier-: digital process (<< 100 nm????) Tier- CMOS pixel sensors, 6

28 Ex: Low Power Design & Mixed CMOS Technologies Other ex. of chips designed in Chartered - Tezzaron technology for ILC FAST architecture aiming to minimise power consumption (IRFU/Saclay) : subdivide sensitive area in small matrices running INDIVIDUALLY in rolling shutter mode adapt the number of raws to required frame r.o. time few µs r.o. time may be reached (???) Combine -Tier read-out chip with Tier hosting sensitive volume : Tier-1: XFAB-0.6 (depleted epitaxy) signal sensing volume Tier- /- : Chartered signal processing micro-circuits adapted to fast (few µs), low occupancy, particle detection (small sub-arrays in projective geometry) Memory tolerant to SEU & SEL (CMP/Grenoble) Chips submitted to foundry back by end of 009 CMOS pixel sensors, 7

29 CONCLUSIONS SUMMARY D CMOS sensors have reached necessary prototyping maturity for real scale applications : beam telescopes (EUDET/FP6, etc.) σ sp few µm & 10 6 part./s/cm (even few GeV e ±!!!) vertex detectors requiring high resolution & very low material budget (STAR-HFT, etc.) -sided ladder with 0. % X 0 (PLUME project) wide spectrum of spin-offs (bio-medical imaging, synchro. rad., dosimetry, hadrontherapy,...) The emergence of fabrication processes with depleted epitaxy / substrate opens the door to : substantial improvements in read-out speed and non-ionising radiation tolerance large pitch applications trackers (e.g. Super LHC ) Translation to D integration processes : resorbs most limitations specific to CMOS sensors : T type & density, peripheral insensitive zone, combination of different CMOS processes offers improved read-out speed : O(µs )! many obstacles to explore & overcome (e.g. power consumption) R&D is progressing 009 important step for process validation CMOS pixel sensors, 8

30 D-MAPS Consortium R.Yarema/IUC/Nov.08 CMOS pixel sensors, 9

Towards a 10 μs, thin high resolution pixelated CMOS sensor system for future vertex detectors

Towards a 10 μs, thin high resolution pixelated CMOS sensor system for future vertex detectors Rita De Masi IPHC-Strasbourg On behalf of the IPHC-IRFU collaboration Physics motivations. Principle of operation