presents High-Speed High-Accuracy 3D VLSI Extraction
|
|
- Douglas Harvey
- 5 years ago
- Views:
Transcription
1 presents High-Speed High-Accuracy 3D VLSI Extraction ICCAD99 1
2 Motivation Interconnects Now Dominate VLSI " Timing " Signal Integrity Gate Interconnect Delay [%] µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm Process Technology Existing Interconnect Extractors Fail " Poor Accuracy & High Speed " Medium Accuracy & Very Low Speed Need High-Speed High-Accuracy Extractor ICCAD99 2
3 Overview Company Technology " High-speed High-accuracy BEM 3D Field Solver " Efficient Net-by-Net RC Extraction Products " Extraction of Critical Cells, Blocks, Nets " Distributed RC Models " IR drop " Substrate Coupling Differentiation " 2D / 2.5D / 3D Tools Summary ICCAD99 3
4 Coyote Systems History " Privately held, located in San Francisco CA " Founded in July 1996 by 3D Field Solver & MEMS experts " DARPA contract to develop extremely fast & easy-to-use 3D CAD for MEMS Products " First MEMS product AutoMEMS announced July 1998 " First VLSI product AutoIC announced June 1999 " New Tools - AutoIC v2, AutoIC-SMP, AutoNet, AutoSubstrate, AutoIRdrop, AutoMEMS v2 Customers " End-users include Siemens, Monterey, Analog Devices, Motorola, Texas Instruments, Hewlett-Packard, Sandia, MIT, Berkeley, CMU " OEM licenses include Monterey Design ICCAD99 4
5 Company Mission VLSI Provide premium high-speed high-accuracy solutions for extraction, timing, and signal integrity problems for modern VLSI designs. MEMS Provide premium high-speed high-accuracy analysis of large, realistic MEMS devices. ICCAD99 5
6 Coyote Products Technology " AutoBEM Fastest BEM field solver " AutoBEM-SMP Exploit fine-grained parallelism on SMP computers VLSI " AutoIC Capacitance extraction of interconnects " AutoIC-SMP SMP support " AutoNet Distributed RC models from layout " AutoSubstrate Resistive coupling in substrate " AutoIRdrop Potential drop in powergrid MEMS " AutoMEMS Coupled electro/mechanical simulator " AutoMEMS-SMP SMP support ICCAD99 6
7 VLSI Geometries Interconnects dominate performance Deep submicron is 3D " Huge layouts " Intricate topologies " IBM " AMD ICCAD99 7
8 VLSI Extraction RC Interconnect Extraction Tools " High-Speed " High-Throughput " High-Capacity " High-Accuracy Possible Alternatives " 3D Field Solvers " Statistical Methods " Pattern Matchers - Coyote Systems - QuickCap - Simplex - Raphael - Frequency - FastCap - Mentor - Ultima Identify Advantages/Disadvantages ICCAD99 8
9 Pattern Matchers Why they are used " Mature technology, Very Fast " Requires 3D field solver to develop pattern library 2D/2.5D tools do not capture 3D DSM effects " Fast (<100,000 nets/hour) after lengthy precharacterization ( hours) " Increasing difficulties with modern processes - Many Layers, small feature sizes - Arbitrary angles & non-manhattan geometries - PCB-style variable wire width - Increasing number of patterns needed " Optimistic error cancellation - no bounded errors " Large errors (>20%) ICCAD99 9
10 Accuracy Problem! " Some pattern matching vendors claim <<10% errors " Simple counterexample D Field Solver Pattern Matching " 3D simulation reveals 20% errors using superpositioning! " Geometric non-linearities prevent accurate solutions ICCAD99 10
11 Statistical Methods Why are they sometimes used " Alternative to FEM, FDM " Reasonably good for Self-Cap & Small Problems Why will they not solve the problem " No Distributed R s & C s " Very long run times with increasing number of nets " Inaccurate Coupling Capacitance - Cij " Only supports Manhattan Geometries " Expensive support for multiple dielectrics " Solves only part of the problem - Cii ICCAD99 11
12 Alternative Solvers Proposed Technologies " FEM " FDM " Traditional BEM Why will they not solve the problem " Not fast enough " Limited to very small problems " Huge memory and CPU time requirements Computationally not feasible ICCAD99 12
13 VLSI Extraction Coyote combines advantages of all approaches! " Field solver accuracy " Pattern matcher speed & capacity Accuracy Coyote Field solver Pattern matcher 0 Capacity Speed ICCAD99 13
14 VLSI Geometries Interconnects dominate performance Deep submicron is 3D " High aspect ratios " Extreme Density " Round Corners " Cylindrical Vias " Variable width wires " Nonideal Cross- Sections " IBM " AMD " Coyote can verify the effect of all these features! - Simplex, Frequency, Avanti, Mentor, QuickCap cannot 3D problems require 3D solutions! ICCAD99 14
15 3D Field Solvers Arbitrary Geometries " PCB-style, manhattan & non-manhattan Arbitrary Materials " Planar & conformal dielectrics Arbitrary Boundary Conditions " Neumann, Dirichlet, mixed, floating Only Coyote s AutoIC solves everything! " AutoIC is faster, more accurate, and easier to use! ICCAD99 15
16 3D Field Solvers If field solver, then pick best field solver " Simplest, smallest model " Most accurate (states & gradients) " Fastest runtime " Lowest memory requirements BEM FEM Direct Iterative Multipole Direct Iterative Nr. nodes N^2 N^2 N^2 N^3 N^3 Memory N^4 N^4 (NlogN)^2 N^6 N^4.5 CPUtime N^6 N^4 (NlogN)^2 N^9 N^4.5 " Coyote uses Multipole Accelerated BEM " Computational Scaling N^2 NlogN ICCAD99 16
17 AutoIC Field Solver VLSI Interconnect Extraction " Accelerated Boundary Element Method " Automatic meshed 3D model from 2D layout " Adaptive mesh refinement " Robust automation " Scriptable batch-mode or interactive GUI-mode operation " Superset of Sematech extraction API " Cluster & symmetric multiprocessing (SMP) support ICCAD99 17
18 AutoIC Speed AutoIC 3D Field Solver " 2,000,000 BEM elements/hour per cpu " 1,500 nets/hour per cpu (user selected <2% error) AutoIC vs. Field Solvers " 10-50x faster than QuickCap " x faster than Raphael AutoIC vs. Library-based "Pattern Matchers" " Similar speed to Frequency Accuracy +2.93% to -4.93% with no outliers Performance Full accuracy / GDS mode : 500 nets /hour: Full accuracy / LEF- DEF mode : 2500 nets/hour -fast option (+/- 15% accuracy) : 6500 nets/hour 5 5/26/99 Copyright 1999 by Frequency Technology, Inc. All rights reserved. ICCAD99 18
19 AutoIC Best Performance " Faster than FastCap, QuickCap, Raphael, Space, etc. " As fast as pattern matchers! " Solves many more problems " Large savings replacing multiple licenses " Large engineering time savings ICCAD99 19
20 Customer Tests Motorola SRAM Evaluation " Self-cap Extraction " Cross-cap Extraction " Convergence " Time & Memory " Model Generation " Ease-of-Use Motorola Compared " AutoIC " QuickCap " Raphael ICCAD99 20
21 Motorola SRAM Cell Convergence of bit-line self-capacitance " Require better than ±5% accuracy 2.50E E-15 AutoIC " x faster! " Best convergence! " Tight error bounds! Capacitance [F] 1.50E E E-16 AutoIC-constant AutoIC-linear Raphael QC 0.01u QC 0.005u 105% 95% 0.00E cputime [sec] (AutoIC on 500MHz PentiumIII, others on 333MHz UltraII) ICCAD99 21
22 Siemens Block Extract Critical Nets " 500 nets " 1x1mm die " 0.35um process " 3 metal layers " Multiple dielectrics 60 AutoIC results " <2% Errors " Excellent scaling " 8mm/min extraction Extraction Time [sec] " All nets extracted in 20 min using 1 cpu = 1,500 nets/hour " All nets extracted in 1 min using 20 cpus = 30k nets/hour um/min Critical Net Length [um] ICCAD99 22
23 Design Flow Industry Std Layout " GDSII, annotated GDSII, CIF, Sematech API 3D Model Generator " Flexible process descriptor " API-mode or Batch-mode or GUI-mode 3D RC Extraction " Lumped, distributed " API-mode or Batch-mode or GUI-mode Industry Std Output " Spice, Sematech API " 3D visualization ICCAD99 23
24 Model Generation Input " Layout " Process Description - Arbitrary layers - Interlayer dielectrics - Conformal dielectrics Output " Meshed 3D Model ICCAD99 24
25 Applications Critical Cells " Coefficient generation " Cell optimization Critical Blocks " IP characterization " Routing Critical Nets " Clock trees, control lines " User-selected nets Substrate Coupling IR drop " Power grid effects delays ICCAD99 25
26 Critical Cells AutoIC simulates 10,000 cells in 2 hours " 1 AutoIC license replaces Raphael licenses " Adaptive meshing on SRAM bit-line shown ICCAD99 26
27 Cell Optimization AutoIC identifies where interactions occur Modify layout to optimize performance " Magnitude of electrostatic flux on SRAM bit-line shown ICCAD99 27
28 Critical Nets Handles largest global nets " Automatic tunneling around aggressor net " 3D visualization indicates crosstalk areas " Designer can modify layout to eliminate problem " 1 AutoIC license replaces QuickCap licenses ICCAD99 28
29 Critical Blocks PCB-style layout (Cypress) " Non-manhattan Geometries " Varying Linewidths " AutoIC 500x faster than QuickCap! " Aggressor net, 3D tunnel & 3D mesh shown ICCAD99 29
30 Non-Ideal Fabrication AutoIC simulates Process Variations " Any geometry " Any material AutoIC correctly solves floating filler metal " Note that filler adds 20% to self-cap! " Non-zero potential on floating filler shown ICCAD99 30
31 AutoIC-SMP Scaling Symmetric multiprocessing support " Excellent scaling with every added CPU " Accelerates both large and small nets SMP Scaling for Critical Net Extraction 4 Relative Scaling 3 2 Large Monterey benchmark global net (control90!reset) small net (control90!n6969) Number CPUs (Sun Ultra Enterprise 450) ICCAD99 31
32 "The Layout is the Design" Timing Delay " Self-capacitances dominate Signal Integrity " Noise or Crosstalk " Cross-capacitances dominate AutoIC generates lumped RC models " Extracts high-accuracy 3D self-caps and cross-caps from the interconnect layout " 3D visualization identifies areas for correction AutoNet generates distributed RC models " Important differences between lumped and distributed simulations ICCAD99 32
33 AutoNet Go from Layout to Distributed Spice Variable model size Segment1 " Lumped net = 1 segment A T1 V1 T3 B " Distributed net = multiple segments Segments a T4 V3 V2 C T2 T5 D b " Spice star-model for each segment " Created from layout " Cross-caps between segments A Segment1 T1 V3 V1 Segment3 T3 B a T4 Segment4 " Compact Spice model size " No model reduction needed C T2 Segment2 D V2 T5 Segment5 b ICCAD99 33
34 AutoNet Automatic segmentation " 5 segments on Net1 " 4 segments on Net2 Net1 Net2 Distributed RC spice model " Each segment has self-capacitance " Each segment has cross-capacitances to segments on other nets B A A B C D E a b c d C D E a b c d ICCAD99 34
35 AutoNet Parallel bus lines " Generated distributed model (8 segments per net) " Generated lumped T-model (1 segment per net) volts Unit step response Vin 8 segments T-model time [ps] Crosstalk volts Vin 8 segments T-model 0.2 " Step Response - Distributed and T model responses similar " Coupling - Distributed and lumped responses similar time [ps] ICCAD99 35
36 AutoNet Non-uniform bus lines " Generated distributed model (4-5 segments per net) " Generated lumped T-model (1 segment per net) volts Unit step responses Vin 4/5 segments T-model Victim B time [ps] Victim A Crosstalk Vin Victim A, 4/5 segments Victim B, 4/5 segments Victim A, T-model Victim B, T-model volts Aggressor " Step Response - Distributed and T model responses similar " Coupling - 2x more noise on distributed model time [ps] ICCAD99 36
37 AutoNet Parallel lines with varying cross-section " Net1 switches Unit step response and coupling effects Net Net1 0.8 volts [V] Vin response, 4/5 segments response, T-model response, self capacitance coupling, 4/5 segments coupling, T-model 0.2 " Step Response - Distributed and T models similar - Commonly used self-cap model is inaccurate " Coupling - 30% larger noise with distributed model time [ps] ICCAD99 37
38 AutoNet Non-uniform parallel lines " Nets switch in opposite directions Net High/low switch response Non-monotonic Net1 0.8 volts [V] Vin 1 Vin 2 Vout 1, 4/5 segments Vout, T-model 1 Vout 2, 4/5 segments Vout, T-model " Step Response - Distributed and T models similar " Coupling time [ps] - Distributed model shows non-monotonic behavior ICCAD99 38
39 AutoNet Clock Tree Skew " Hierarchical H-shaped layout " 256 terminals Clock skew volts [V] Vin Vout 1 Vout 2 Vout sample segments time [ps] " RC model with 70 segments " Non-constant clock skew due to cross capacitances " 20% clock skew at 3 random clock terminals! ICCAD99 39
40 AutoNet Compare Floating Filler & Grounded Filler " 3x3 crossing bus " Net1 switches Unit step response, filler floating / grounded Net1 Net2 Net3 volts [V] Vin Vout 1, floating filler Vout 1, grounded filler Vout 2, floating filler Vout 2, grounded filler Vout 3, floating filler Vout 3, grounded filler time [ps] Significant filler problem " 25% difference in risetime " 9x increase in noise level ICCAD99 40
41 AutoIRdrop AutoIC solves 3D field outside interconnects AutoIRdrop solves 2D/3D field inside interconnects " Varying angles, width, cross-section " Vias " Aluminum, copper " Current sink/source 4 2D/3D Field Solver " Solves potential drop - Resistance " Solves current density through wire - Enables electromigration analysis ICCAD99 41
42 AutoIRdrop "Naive" Resistance Network " N-ports require N simulations, resulting in N 2 resistances 1 2 "Smart" Resistance Network " N-ports require N simulations, resulting in N resistances Field Simulation " 2D resistance is very accurate, much faster than 3D " 2D suitable for resistance, 3D suitable for capacitance 2 3 ICCAD99 42
43 AutoSubstrate Solves 3D field inside substrates " Contacts " Multiple materials 3D Field Solver 10 " Solves potential distribution " Solves electrostatic flux distribution " Solves current density through contacts ICCAD99 43
44 AutoSubstrate Resistance Network " Resistance calculated from calculated current densities " Resistor for every portport interaction " Automatic spice model Ohm x Port Port ICCAD99 44
45 Shipping Now Fastest, Most accurate, Easiest to use " Replace multiple tools " Large engineering time savings Licenses " End-user licenses " OEM, Embedded licenses Available Now " Sun, Linux, HP platforms " Uniprocessor & SMP configurations ICCAD99 45
46 For More Information Contact " Dr. Per Ljung 2740 Van Ness Ave. #210 San Francisco, CA (415) x12 ICCAD99 47
DATASHEET CADENCE QRC EXTRACTION
DATASHEET Cadence QRC Etraction, the industry s premier 3D fullchip parasitic etractor that is independent of design style or flow, is a fast and accurate RLCK etraction solution used during design implementation
More informationPROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS
PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high
More informationModeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting
Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting C. Guardiani, C. Forzan, B. Franzini, D. Pandini Adanced Research, Central R&D, DAIS,
More informationFigure 1. Inductance
Tools for On-Chip Interconnect Inductance Extraction Jerry Tallinger OEA International Inc. 155 East Main Ave., Ste. 110 Morgan Hill, CA 95037 jerry@oea.com Haris Basit OEA International Inc. 155 East
More informationInductance 101: Analysis and Design Issues
Inductance 101: Analysis and Design Issues Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao Motorola Inc., Austin TX 78729 kaushik.gala@motorola.com Abstract With operating frequencies
More informationImpact of Low-Impedance Substrate on Power Supply Integrity
Impact of Low-Impedance Substrate on Power Supply Integrity Rajendran Panda and Savithri Sundareswaran Motorola, Austin David Blaauw University of Michigan, Ann Arbor Editor s note: Although it is tempting
More informationIntroduction to Digital VLSI Design מבוא לתכנון VLSI ספרתי
Design מבוא לתכנון VLSI ספרתי Extraction Lecturer: Gil Rahav Semester B, EE Dept. BGU. Freescale Semiconductors Israel Slide 1 Extraction Extraction is a process of creating electrical representation (R&C)
More informationWhen Should You Apply 3D Planar EM Simulation?
When Should You Apply 3D Planar EM Simulation? Agilent EEsof EDA IMS 2010 MicroApps Andy Howard Agilent Technologies 1 3D planar EM is now much more of a design tool Solves bigger problems and runs faster
More informationUsing Sonnet EM Analysis with Cadence Virtuoso in RFIC Design. Sonnet Application Note: SAN-201B July 2011
Using Sonnet EM Analysis with Cadence Virtuoso in RFIC Design Sonnet Application Note: SAN-201B July 2011 Description of Sonnet Suites Professional Sonnet Suites Professional is an industry leading full-wave
More informationUNIT-III POWER ESTIMATION AND ANALYSIS
UNIT-III POWER ESTIMATION AND ANALYSIS In VLSI design implementation simulation software operating at various levels of design abstraction. In general simulation at a lower-level design abstraction offers
More informationBASICS: TECHNOLOGIES. EEC 116, B. Baas
BASICS: TECHNOLOGIES EEC 116, B. Baas 97 Minimum Feature Size Fabrication technologies (often called just technologies) are named after their minimum feature size which is generally the minimum gate length
More informationFDTD SPICE Analysis of High-Speed Cells in Silicon Integrated Circuits
FDTD Analysis of High-Speed Cells in Silicon Integrated Circuits Neven Orhanovic and Norio Matsui Applied Simulation Technology Gateway Place, Suite 8 San Jose, CA 9 {neven, matsui}@apsimtech.com Abstract
More informationSignal Integrity for Gigascale SOC Design. Professor Lei He ECE Department University of Wisconsin, Madison
Signal Integrity for Gigascale SOC Design Professor Lei He ECE Department University of Wisconsin, Madison he@ece.wisc.edu http://eda.ece.wisc.edu Outline Capacitive noise Technology trends Capacitance
More informationLecture #2 Solving the Interconnect Problems in VLSI
Lecture #2 Solving the Interconnect Problems in VLSI C.P. Ravikumar IIT Madras - C.P. Ravikumar 1 Interconnect Problems Interconnect delay has become more important than gate delays after 130nm technology
More informationOn-Chip Inductance Modeling
On-Chip Inductance Modeling David Blaauw Kaushik Gala ladimir Zolotov Rajendran Panda Junfeng Wang Motorola Inc., Austin TX 78729 ABSTRACT With operating frequencies approaching the gigahertz range, inductance
More information2.5D & 3D Package Signal Integrity A Paradigm Shift
2.5D & 3D Package Signal Integrity A Paradigm Shift Nozad Karim Technology & Platform Development November, 2011 Enabling a Microelectronic World Content Traditional package signal integrity vs. 2.5D/3D
More informationTrends and Challenges in VLSI Technology Scaling Towards 100nm
Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends
More informationLeading at the edge TECHNOLOGY AND MANUFACTURING DAY
Leading at the edge 22FFL technology MARK BOHR Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration Disclosures Intel Technology and Manufacturing Day
More informationOn-Chip Inductance Modeling and Analysis
On-Chip Inductance Modeling and Analysis Kaushik Gala, ladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw Motorola Inc., Austin TX 78729 kaushik.gala@motorola.com Abstract With operating
More informationStatic Timing Analysis Taking Crosstalk into Account 1
Static Timing Analysis Taking Crosstalk into Account 1 Matthias Ringe IBM Deutschland Entwicklung GmbH, Schönaicher Str. 220 71032 Böblingen; Germany ringe@de.ibm.com Thomas Lindenkreuz Robert Bosch GmbH,
More informationInterconnect-Power Dissipation in a Microprocessor
4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition
More informationInterconnect Modeling in Deep-Submicron Design
IEICE TRANS. ELECTRON., VOL.E83 C, NO.8 AUGUST 2000 1311 INVITED PAPER Special Issue on SISPAD 99 Interconnect Modeling in Deep-Submicron Design Won-Young JUNG a), Soo-Young OH, Jeong-Taek KONG, and Keun-Ho
More informationLecture 13: Interconnects in CMOS Technology
Lecture 13: Interconnects in CMOS Technology Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 10/18/18 VLSI-1 Class Notes Introduction Chips are mostly made of wires
More informationUser2User The 2007 Mentor Graphics International User Conference
7/2/2007 1 Designing High Speed Printed Circuit Boards Using DxDesigner and Expedition Robert Navarro Jet Propulsion Laboratory, California Institute of Technology. User2User The 2007 Mentor Graphics International
More informationSemiconductor Technology Academic Research Center An RTL-to-GDS2 Design Methodology for Advanced System LSI
Semiconductor Technology Academic Research Center An RTL-to-GDS2 Design Methodology for Advanced System LSI Jan. 28. 2011 Nobuyuki Nishiguchi Semiconductor Technology Advanced Research Center (STARC) ASP-DAC
More informationHow to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model
How to anticipate Signal Integrity Issues: Improve my Channel Simulation by using Electromagnetic based model HSD Strategic Intent Provide the industry s premier HSD EDA software. Integration of premier
More informationAppendix. RF Transient Simulator. Page 1
Appendix RF Transient Simulator Page 1 RF Transient/Convolution Simulation This simulator can be used to solve problems associated with circuit simulation, when the signal and waveforms involved are modulated
More informationIntel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells
Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration Intel 1 What are We Announcing? Intel has fabricated fully-functional
More informationGeorgia Tech. Greetings from. Machine Learning and its Application to Integrated Systems
Greetings from Georgia Tech Machine Learning and its Application to Integrated Systems Madhavan Swaminathan John Pippin Chair in Microsystems Packaging & Electromagnetics School of Electrical and Computer
More informationBrief Overview of EM Computational Modeling Techniques for Real-World Engineering Problems
Brief Overview of EM Computational Modeling Techniques for Real-World Engineering Problems Bruce Archambeault, Ph.D. IEEE Fellow, IBM Distinguished Engineer Emeritus Bruce@brucearch.com Archambeault EMI/EMC
More informationEE141- Spring 2004 Digital Integrated Circuits
EE141- Spring 2004 Digital Integrated Circuits Lecture 27 Power distribution Resistive interconnect 1 Administrative Stuff Make-up lecture on Monday 4-5:30pm Special office hours of Prof. Rabaey today
More informationAndrew Clinton, Matt Liberty, Ian Kuon
Andrew Clinton, Matt Liberty, Ian Kuon FPGA Routing (Interconnect) FPGA routing consists of a network of wires and programmable switches Wire is modeled with a reduced RC network Drivers are modeled as
More informationFixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
Fixing Antenna Problem by Dynamic Dropping and Jumper Insertion Peter H. Chen and Sunil Malkani Chun-Mou Peng James Lin TeraLogic, Inc. International Tech. Univ. National Semi. Corp. 1240 Villa Street
More informationDesignCon On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces
DesignCon 2010 On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces Ralf Schmitt, Rambus Inc. [Email: rschmitt@rambus.com] Hai Lan, Rambus Inc. Ling Yang, Rambus Inc. Abstract
More informationElectromagnetic Interference Reduction Study using a Self-Structuring Antenna
Electromagnetic Interference Reduction Study using a Self-Structuring Antenna A. M. Patel (1), E. J. Rothwell* (1), L.C. Kempel (1), and J. E. Ross (2) (1) Department of Electrical and Computer Engineering
More informationChapter 4. Problems. 1 Chapter 4 Problem Set
1 Chapter 4 Problem Set Chapter 4 Problems 1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock network (between the nodes) is 5 mm long, 3 µm wide, and is implemented
More informationLow Transistor Variability The Key to Energy Efficient ICs
Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc.
More informationSynthesis of Optimal On-Chip Baluns
Synthesis of Optimal On-Chip Baluns Sharad Kapur, David E. Long and Robert C. Frye Integrand Software, Inc. Berkeley Heights, New Jersey Yu-Chia Chen, Ming-Hsiang Cho, Huai-Wen Chang, Jun-Hong Ou and Bigchoug
More informationSticks Diagram & Layout. Part II
Sticks Diagram & Layout Part II Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped
More informationClocktree RLC Extraction with Efficient Inductance Modeling
Clocktree RLC Extraction with Efficient Inductance Modeling Norman Chang, Shen Lin, Lei He*, O. Sam Nakagawa, and Weize Xie Hewlett-Packard Laboratories, Palo Alto, CA, USA *University of Wisconsin, Madison,
More informationAnalysis and Reduction of On-Chip Inductance Effects in Power Supply Grids
Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids Woo Hyung Lee Sanjay Pant David Blaauw Department of Electrical Engineering and Computer Science {leewh, spant, blaauw}@umich.edu
More informationStudy on Bluetooth Antenna Integration into Metal Environment Julnar Musmar, Dr. Ing Denis Sievers, Ralf Kakerow Continental, Paderborn University
Bitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture. (24,4 x 7,6 cm) Study on Bluetooth Antenna Integration into Metal Environment Julnar Musmar, Dr.
More informationChapter 3 Novel Digital-to-Analog Converter with Gamma Correction for On-Panel Data Driver
Chapter 3 Novel Digital-to-Analog Converter with Gamma Correction for On-Panel Data Driver 3.1 INTRODUCTION As last chapter description, we know that there is a nonlinearity relationship between luminance
More informationEE141-Spring 2007 Digital Integrated Circuits
EE141-Spring 2007 Digital Integrated Circuits Lecture 22 I/O, Power Distribution dders 1 nnouncements Homework 9 has been posted Due Tu. pr. 24, 5pm Project Phase 4 (Final) Report due Mo. pr. 30, noon
More informationTechnology Timeline. Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs. FPGAs. The Design Warrior s Guide to.
FPGAs 1 CMPE 415 Technology Timeline 1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000 Transistors ICs (General) SRAMs & DRAMs Microprocessors SPLDs CPLDs ASICs FPGAs The Design Warrior s Guide
More informationDesign and Matching of a 60-GHz Printed Antenna
Application Example Design and Matching of a 60-GHz Printed Antenna Using NI AWR Software and AWR Connected for Optenni Figure 1: Patch antenna performance. Impedance matching of high-frequency components
More informationI DDQ Current Testing
I DDQ Current Testing Motivation Early 99 s Fabrication Line had 5 to defects per million (dpm) chips IBM wanted to get 3.4 defects per million (dpm) chips Conventional way to reduce defects: Increasing
More information! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
More informationA passive circuit based RF optimization methodology for wireless sensor network nodes. Article (peer-reviewed)
Title Author(s) Editor(s) A passive circuit based RF optimization methodology for wireless sensor network nodes Zheng, Liqiang; Mathewson, Alan; O'Flynn, Brendan; Hayes, Michael; Ó Mathúna, S. Cian Wu,
More informationEMI Reduction on an Automotive Microcontroller
EMI Reduction on an Automotive Microcontroller Design Automation Conference, July 26 th -31 st, 2009 Patrice JOUBERT DORIOL 1, Yamarita VILLAVICENCIO 2, Cristiano FORZAN 1, Mario ROTIGNI 1, Giovanni GRAZIOSI
More informationWorst Case RLC Noise with Timing Window Constraints
Worst Case RLC Noise with Timing Window Constraints Jun Chen Electrical Engineering Department University of California, Los Angeles jchen@ee.ucla.edu Lei He Electrical Engineering Department University
More informationDeep Submicron Interconnect. 0.18um vs. 013um Interconnect
Deep Submicron Interconnect R. Dept. of ECE University of British Columbia res@ece.ubc.ca 0.18um vs. 013um Interconnect 0.18µm 5-layer Al Metal Process 0.13µm 8-layer Cu Metal Process 1 Interconnect Scaling
More informationAdvanced Meshing Techniques
Advanced Meshing Techniques Ansoft High Frequency Structure Simulator v10 Training Seminar P-1 Overview Initial Mesh True Surface Approximation Surface Approximation Operations Lambda Refinement Seeding
More informationResearch in Support of the Die / Package Interface
Research in Support of the Die / Package Interface Introduction As the microelectronics industry continues to scale down CMOS in accordance with Moore s Law and the ITRS roadmap, the minimum feature size
More informationMicrocircuit Electrical Issues
Microcircuit Electrical Issues Distortion The frequency at which transmitted power has dropped to 50 percent of the injected power is called the "3 db" point and is used to define the bandwidth of the
More informationCS 6135 VLSI Physical Design Automation Fall 2003
CS 6135 VLSI Physical Design Automation Fall 2003 1 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) 5742963 tcwang@cs.nthu.edu.tw Office hours: M56R5
More informationSignal integrity means clean
CHIPS & CIRCUITS As you move into the deep sub-micron realm, you need new tools and techniques that will detect and remedy signal interference. Dr. Lynne Green, HyperLynx Division, Pads Software Inc The
More informationSwitching (AC) Characteristics of MOS Inverters. Prof. MacDonald
Switching (AC) Characteristics of MOS Inverters Prof. MacDonald 1 MOS Inverters l Performance is inversely proportional to delay l Delay is time to raise (lower) voltage at nodes node voltage is changed
More informationRamon Canal NCD Master MIRI. NCD Master MIRI 1
Wattch, Hotspot, Hotleakage, McPAT http://www.eecs.harvard.edu/~dbrooks/wattch-form.html http://lava.cs.virginia.edu/hotspot http://lava.cs.virginia.edu/hotleakage http://www.hpl.hp.com/research/mcpat/
More informationLecture 11: Clocking
High Speed CMOS VLSI Design Lecture 11: Clocking (c) 1997 David Harris 1.0 Introduction We have seen that generating and distributing clocks with little skew is essential to high speed circuit design.
More informationRelationship Between Signal Integrity and EMC
Relationship Between Signal Integrity and EMC Presented by Hasnain Syed Solectron USA, Inc. RTP, North Carolina Email: HasnainSyed@solectron.com 06/05/2007 Hasnain Syed 1 What is Signal Integrity (SI)?
More informationExperiences and Benefits of 16nm and 10nm FinFET Development
Experiences and Benefits of 16nm and 10nm FinFET Development Jeff Galloway, Paweł Banachowicz, Michael Kroger, Brian Eplett, Andrew Cole, Randy Caplan Silicon Creations Process Experience Silicon Creations
More informationPower Distribution Paths in 3-D ICs
Power Distribution Paths in 3-D ICs Vasilis F. Pavlidis Giovanni De Micheli LSI-EPFL 1015-Lausanne, Switzerland {vasileios.pavlidis, giovanni.demicheli}@epfl.ch ABSTRACT Distributing power and ground to
More information3 GHz Wide Frequency Model of Surface Mount Technology (SMT) Ferrite Bead for Power/Ground and I/O Line Noise Simulation of High-speed PCB
3 GHz Wide Frequency Model of Surface Mount Technology (SMT) Ferrite Bead for Power/Ground and I/O Line Noise Simulation of High-speed PCB Tae Hong Kim, Hyungsoo Kim, Jun So Pak, and Joungho Kim Terahertz
More informationManaging Cross-talk Noise
Managing Cross-talk Noise Rajendran Panda Motorola Inc., Austin, TX Advanced Tools Organization Central in-house CAD tool development and support organization catering to the needs of all design teams
More informationDesign and Analysis of Power Distribution Networks in PowerPC Microprocessors
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan Advanced Tools Group, Advanced System Technologies
More informationDesignCon Full Chip Signal and Power Integrity with Silicon Substrate Effect. Norio Matsui Dileep Divekar Neven Orhanovic
DesignCon 2004 Chip-Level Physical Design Full Chip Signal and Power Integrity with Silicon Substrate Effect Norio Matsui Dileep Divekar Neven Orhanovic Applied Simulation Technology, Inc. 408-436-9070
More informationAccurate In Situ Measurement of Peak Noise and Delay Change Induced by Interconnect Coupling
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 10, OCTOBER 2001 1587 Accurate In Situ Measurement of Peak Noise and Delay Change Induced by Interconnect Coupling Takashi Sato, Member, IEEE, Dennis
More informationLecture 1: Digital Systems and VLSI
VLSI Design Lecture 1: Digital Systems and VLSI Shaahinhi Hessabi Department of Computer Engineering Sharif University of Technology Adapted with modifications from lecture notes prepared by the book author
More informationArea and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses Srinivasa R. Sridhara, Arshad Ahmed, and Naresh R. Shanbhag Coordinated Science Laboratory/ECE Department University of Illinois at
More informationCapturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis
Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis Masanori Hashimoto Dept. Communications & Computer Engineering Kyoto University hasimoto@i.kyoto-u.ac.jp Yuji Yamada Dept. Communications
More informationRF Board Design for Next Generation Wireless Systems
RF Board Design for Next Generation Wireless Systems Page 1 Introduction Purpose: Provide basic background on emerging WiMax standard Introduce a new tool for Genesys that will aide in the design and verification
More informationFast Placement Optimization of Power Supply Pads
Fast Placement Optimization of Power Supply Pads Yu Zhong Martin D. F. Wong Dept. of Electrical and Computer Engineering Dept. of Electrical and Computer Engineering Univ. of Illinois at Urbana-Champaign
More informationEE 434 ASIC and Digital Systems. Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University.
EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries VLSI Design System Specification Functional Design RTL
More informationSignal Integrity Design of TSV-Based 3D IC
Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues
More information8 th Order Dielectric Resonator Filter with Three Asymmetric
Application Article CST AG 215 8 th Order Dielectric Resonator Filter with Three Asymmetric Transmission Zeroes The dielectric resonator filter (Figure 1) is a high-performance filter design which is well-suited
More informationSignal Integrity Modeling and Measurement of TSV in 3D IC
Signal Integrity Modeling and Measurement of TSV in 3D IC Joungho Kim KAIST joungho@ee.kaist.ac.kr 1 Contents 1) Introduction 2) 2.5D/3D Architectures with TSV and Interposer 3) Signal integrity, Channel
More informationMeasurement Results for a High Throughput MCM
Measurement Results for a High Throughput MCM Funding: Paul Franzon Toby Schaffer, Alan Glaser, Steve Lipa North Carolina State University paulf@ncsu.edu www.ece.ncsu.edu/erl Outline > Heterogeneous System
More informationDC-DC Converter Design Phase Acceleration with Virtuoso UltraSim Simulator
DC-DC Converter Design Phase Acceleration with Virtuoso UltraSim Simulator Mohamed Bouhamame, Didier Depreeuw NXP Semiconductors Caen France Outline Motivations DC-DC converter topology Implementation
More informationLecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design)
Lecture 07 Modeling and Optimization of VLSI Interconnects (ECG 415/615 Introduction to VLSI System Design) Dr. Yingtao Jiang Department of Electrical and Computer Engineering University of Nevada Las
More informationEMDS for ADS Momentum
EMDS for ADS Momentum ADS User Group Meeting 2009, Böblingen, Germany Prof. Dr.-Ing. Frank Gustrau Gustrau, Dortmund User Group Meeting 2009-1 Univ. of Applied Sciences and Arts (FH Dortmund) Presentation
More informationStandardization of Interconnects: Towards an Interconnect Library in VLSI Design
Standardization of Interconnects: Towards an Interconnect Library in VLSI Design Submitted in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY by P. Vani Prasad 00407006 Supervisor:
More information3-2-1 Contact: An Experimental Approach to the Analysis of Contacts in 45 nm and Below. Rasit Onur Topaloglu, Ph.D.
3-2-1 Contact: An Experimental Approach to the Analysis of Contacts in 45 nm and Below Rasit Onur Topaloglu, Ph.D. Outline Introduction and Motivation Impact of Contact Resistance Test Structures for Contact
More informationNarrowband Combline Filter Design with ANSYS HFSS
Narrowband Combline Filter Design with ANSYS HFSS Daniel G. Swanson, Jr. DGS Associates, LLC Boulder, CO dan@dgsboulder.com www.dgsboulder.com Introduction N = 6 Inline, Cover Loaded, Combline Filter Single
More informationLeakage Power Minimization in Deep-Submicron CMOS circuits
Outline Leakage Power Minimization in Deep-Submicron circuits Politecnico di Torino Dip. di Automatica e Informatica 1019 Torino, Italy enrico.macii@polito.it Introduction. Design for low leakage: Basics.
More informationIntroduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.
More informationHomework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!
EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback
More information! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture
More informationCROSS-COUPLING capacitance and inductance have. Performance Optimization of Critical Nets Through Active Shielding
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 51, NO. 12, DECEMBER 2004 2417 Performance Optimization of Critical Nets Through Active Shielding Himanshu Kaul, Student Member, IEEE,
More informationOn Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI
ELEN 689 606 Techniques for Layout Synthesis and Simulation in EDA Project Report On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital
More informationCell size and box size in Sonnet RFIC inductor analysis
Cell size and box size in Sonnet RFIC inductor analysis Purpose of this document: This document describes the effect of some analysis settings in Sonnet: Influence of the cell size Influence of thick metal
More informationA CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design
A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design Hai Lan, Zhiping Yu, and Robert W. Dutton Center for Integrated Systems, Stanford
More informationCMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience
CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY
More informationNanoFabrics: : Spatial Computing Using Molecular Electronics
NanoFabrics: : Spatial Computing Using Molecular Electronics Seth Copen Goldstein and Mihai Budiu Computer Architecture, 2001. Proceedings. 28th Annual International Symposium on 30 June-4 4 July 2001
More informationThe wireless industry
From May 2007 High Frequency Electronics Copyright Summit Technical Media, LLC RF SiP Design Verification Flow with Quadruple LO Down Converter SiP By HeeSoo Lee and Dean Nicholson Agilent Technologies
More information12-bit 140 MSPS IQ DAC
SPECIFICATION 1 FEATURES TSMC CMOS 65 nm Resolution 12 bit Current-sinking DAC Different power supplies for digital (1.2 V) and analog parts (2.5 V) Sampling rate up to 140 MSPS Optional internal differential
More informationCharacterization Methodology for High Density Microwave Fixtures. Dr. Brock J. LaMeres, Montana State University
DesignCon 2008 Characterization Methodology for High Density Microwave Fixtures Dr. Brock J. LaMeres, Montana State University lameres@ece.montana.edu Brent Holcombe, Probing Technology, Inc brent.holcombe@probingtechnology.com
More informationDavinci. Semiconductor Device Simulaion in 3D SYSTEMS PRODUCTS LOGICAL PRODUCTS PHYSICAL IMPLEMENTATION SIMULATION AND ANALYSIS LIBRARIES TCAD
SYSTEMS PRODUCTS LOGICAL PRODUCTS PHYSICAL IMPLEMENTATION SIMULATION AND ANALYSIS LIBRARIES TCAD Aurora DFM WorkBench Davinci Medici Raphael Raphael-NES Silicon Early Access TSUPREM-4 Taurus-Device Taurus-Lithography
More informationEMC cases study. Antonio Ciccomancini Scogna, CST of America CST COMPUTER SIMULATION TECHNOLOGY
EMC cases study Antonio Ciccomancini Scogna, CST of America antonio.ciccomancini@cst.com Introduction Legal Compliance with EMC Standards without compliance products can not be released to the market Failure
More information