ANALOG IC DESIGN HIGH SPEED SERIAL LINKS (HSSL)

Transcription

1 ANALOG IC DESIGN HIGH SPEED SERIAL LINKS (HSSL)

2 Team members Transmitter Receiver Timing Nasr Mahana Mohamed Alaa Issa Mostafa Naeem Ahmed El-Said Mostafa Ayesh Mohamed Issa El- Dacher Hisham Moubarak Ahmed El-Said Shehata Mohamed Megahed Mabrouk Mohamed Mansour El- Rayany

3 Introduction Why HSSL? 10GBaseKR Standard System overview Channel Transmitter Receiver Timing system

4 Why HSSL? Many core system processors Bandwidth increased to Tpbs Limited number of pins HSSL

5 10GBaseKR Standard Transmitter Receiver Speed Gbps Speed Gbps Max. output diff. peak-peak 1.2V Max. input diff. peak-peak 1.2V Max. jitter 0.28 UI Max Jitter 0.13 UI Programmable Equalization (3-tap FIR) AC coupling CM voltage limit 0-1.9

6 System overview

7 Channel Limited channel bandwidth High frequency attenuation and dispersion Inter symbol interference (ISI)

8 Tx & Rx Transmitter Serializer 3-Tap FIR Receiver AFE ADC 3-Tap DFE & 2-tap FFE

9 Timing System Phase locked loop (PLL) at Tx side PLL at Rx side with CDR

10 TRANSMITTER

11 Transmitter system overview Serializer. Three tap FIR equalizer.

12 Conceptual I/O Transmitter Goals High bit rate Low power consumption Low noise, free of unnecessary time-domain spikes. Low coupling to other links

13 System Overview

14 Multiplexer

15 Multiplexer Introduction. Different architectures. Topologies. Results. Power budget. Corner results.

16 Introduction High-speed links can be limited by both the channel and the circuits. Multiplexing circuitry also limits maximum data rate.

17 Different Architectures Full rate architecture. Advantages: Relaxes duty cycle of the clock. Disadvantages: Need to generate and distribute high speed clock. Need to design high speed flip-flop.

18 Half Rate Architecture Half-rate architecture uses 2 clock phases separated by 180 to mux data. Advantages: eliminates high-speed clock and flip-flop. Disadvantages: Output eye is sensitive to clock duty cycle..

19 Half Rate Architecture Tree architecture 16:1 MUX with 4 stages based on 2_to_1 MUX

20 1/4-rate architecture 4-phase clock distribution spaced at phase spacing and duty cycle critical for uniform output eye. Advantages: Reduce the frequency of the clock. Disadvantages: Increase multiplexing factor to allow for lower frequency clock distribution.

21 Tree Architecture

22 First Stage Input data rate 625Mb/s. Output data rate 1.25Gb/s. The clock is 625MHZ. All circuit implemented in CMOS.

23 Second Stage Input data rate 1.25Gb/s. output data rate 2.5Gb/s. The clock is 1.25MHZ. All circuit implemented in CMOS.

24 Third Stage Input data rate 2.5Gb/s. output data rate 5Gb/s. The clock is 2.5MHZ. All circuit implemented in CMOS.

25 Fourth Stage Input data rate 5Gb/s. output data rate 10Gb/s. The clock is 5MHZ. Flip-Flop and Latch are implemented by TSPC. 2_1_mux is CML MUX.

26 Flip Flop Built from master and slave D latches A negative level-sensitive latch A positive level-sensitive latch

27 2:1 MUX No restoring mux uses two transmission gates. Only 4 transistors More efficient. Low area. Low power. High speed than other CMOS.

28 CML MUX

29 TSPC

30 First Stage Result Flip Flop

31 First Stage Result D latch

32 First Stage Result 2:1 MUX

33 First Stage Result Eye diagram

34 Second Stage Result Eye diagram

35 Third Stage Result Eye diagram

36 Fourth Stage Result TSPC Flip Flop

37 Fourth Stage Result TSPC latch

38 Fourth Stage Result CML MUX

39 Fourth Stage Result Eye diagram

40 Power budget Stage 1-First stage power u watt 2-Second stage u watt 3-Third stage m watt. 4-Fourth stage m watt. 5-Total power m watt.

41 Corner Results Ss corner,ff_res, high_temp MUX across this corner which is the worst corner and generate output swing 0.67 mv pp.

42 Agenda 3 Tap Equalizer with programmable cofficient Digital To analog Converter Drivers Predrivers Flipflop TransmitterOutput

43 3Tap Equalizer With programmable Cofficient Vpre=[c(-1)-c(0)-c(1) ]V Vpst=[c(-1)+c(0)-c(1)]V Vss=[c(-1)+c(0)+c(1)]V C-1 has 8 settings from 0 to with step size of at least C1 has 8 settings from 0 to with step size of at least 0.05.

44 Frequency-Domain Representation W(z)=-c(-1)+ c(0) -c(1) z=exp(j*2*pi*f*ts)=cos(2*pi*f*ts)+sin(2*pi*f*ts) At low frequency(f=0) Z= cos(0)+jsin(0) W(f=0)= c(-1)+ c(0)- c(1) At Nyquist frequency response (f=1/2ts) Z= cos(pi)+jsin(pi)=-1 W(f=1/2Ts)= -1

45 Frequency-Domain Representation C(-1) C(0) C(1) LF NF db db db db db db db 0 The Equalizer has -26db of frequency peaking Attenutes DC at -26.6db and passes Nyquist frequency

46 Coefficient Range and Equivalent current C(-1) Pre-tap current C(0) Main-tap current C(1) Post-tap current 0 0mA 1 20mA 0 0mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

47 Digital to analog converter Segmented current arrays All current sources are equal and controlled by thermometer code so that when digital input increases by 1 LSB, one additional current is switched to output.

48 current segmented arrays Advantages Guarantee monotonicity: the transfer characteristics of such arrays is monotonic function of input. Cancel the glitches that lead to large DNL,since it s controlled by thermometer coding.

49 Matching Analyze performance of mismatch on circuit :- Systematic Mismatch VDS Random Mismatch Id= Id = / / Larger device area less mismatch effect Larger gate-overdrive less threshold mismatch

50 Cascode current mirror

51 Monte Carlo simulation

52 Drivers

53 CML pre drivers. Capacitance driving

54 CML Latch Operation At the beginning of regeneration phase : Vout(0)=GM1 RD vin Gm3Vout= +CL Vout(t)=Gm1RD Vin exp exp

55 Setting & hold time

56 Flip flop output

57 Transmitter Output Eye diagram without any Equalization

58 Transmitter Output Minimum output swing without any equalization Outpu

59 Transmitter Output Eye diagram after passing 16 inch channel with - 12db loss without Equalization

60 Transmitter Output Eye diagram at Tx with Equalization

61 Transmitter Output Eye diagram at Tx with Equalization after passing 16 inch channel with -12db loss

62 Transmitter Output Eye diagram after passing 22 inch channel with - 20db loss without Equalization

63 Transmitter output Eye diagram after passing 22inch channel with - 20db loss with Equalization

64 Corners Simulation System passes all corners specially FF corner for Transistor, SS corner for resistor with high temp and supply=0.9v SS corner for Transistor,ff corner for resistor with low temp and supply=1.1v

65 Rise &Fall time Rise time is equal 29.5 ps. Fall time is equal 35.9 ps. at SS corner for transistor FF for resistor, temperature 0ºC and supply 0.9 V

66 Rise &Fall time 2 Rise time is equal 44.2 ps. Fall time is equal 44.3 ps. at FF corner for transistor SS for resistor, temperature 85ºC and supply 1.1 V

67 Power budget Type Power consumption MUX Pre-driver Flip-flop Driver Total power 11.73mW 4.5mW 2mW 20mW 38.23mW

68 Drivers layout

69 Future Work Bandgap reference circuit Layout and post layout simulation

70 RECEIVER SYSTEM LEVEL OVERVIEW

71 RX system level conventional Architecture

72 RX system level Recent years & future trend

73 Our Rx System level

74 ANALOG FRONT END (AFE)

75 Contents Introduction Continuous Time Linear Equalizer (CTLE) Design Simulation Results Variable Gain Amplifier (VGA) Design Simulation Results

76 Introduction Received signals suffers from frequency dependent attenuation and dispersion causing inter symbol interference (ISI) Dispersion due to skin effect and dielectric losses

77 Continuous Time Linear Equalizer (CTLE) Equalizer acts as a high-pass filter to compensate for channel high frequency losses Passive linear Vs. Active linear equalizer First order Vs. Second order CTLE

78 CTLE Channel Equalizer Equalized channel

79 Concept of operation

80 Design

81 Pros & Cons Pros Low power and area Cancel both precursor and long tail ISI Cons Noise and cross talk are amplified Very sensitive to PVT

82 Simulation results AC-Response Peaking variation : 0 db 10dB

83 Peaking adaptation values Rdeg (Ω) Boosting (db) K 10.5

84 Simulation results AC-Response (1) Typical back plane channel with S 21 = -5.3 db -3dB BW =

85 Simulation results Eye diagram (1) Typical back plane channel with S 21 = -5.3 db

86 Simulation results AC-Response (3) Typical back plane channel with S 21 = -9.5 db

87 Simulation results Eye diagram (2) Typical back plane channel with S 21 = -9.5 db

88 Simulation results AC-Response (3) Typical back plane channel with S 21 = db

89 Simulation results Eye diagram (3) Typical back plane channel with S 21 = db

90 Characteristics Power Consumption Range Data Rate Supply Voltage Technology 7.84 mw 0-10 db 10 Gbps 1V 65nm

91 Variable Gain Amplifier (VGA) Channel attenuates signal + CTLE boost high freq. Received signal must be amplified for operating the ADC Varying gain by varying the degeneration resistance to adjust the output swing at constant value = 1.2V p- p

92 Design Large Bandwidth Reject CM noise Sets CM for following stage A =

93 Simulation results (1)

94 Simulation results (2)

95 Different gain adaptations

96 Characteristics Power Consumption Output voltage swing Data Rate Supply Voltage Technology 3.2mW 1.2V p-p 10 Gbps 1V 65nm

97 Conclusion & Further work Conclusion AFE of the Rx flatten the frequency response of the signal after being the channel effect, and amplifies the signal going to the ADC Further Work Passing corners Layout

98 Questions?

99 LOW POWER, HIGH SPEED FLASH ADC

100 Overview ADC in Digital RX Architecture System level design Models Expected Specs Circuits Schematics Specs Simulation Results Waveforms Integration with system Waveforms

101 ADC Architecture Most proper candidates: Type Resolution Speed Pipeline High Medium Flash Low High Folding Medium High

102 ADC Architecture: Time Interleaving Pros: Lower sampling frequency Relax design of ADC components Cons: Gain mismatch Offset mismatch Timing mismatch

103 ADC Architecture: Flash ADC Pros: Highest conversion speed. Cons: Efficient only Up to 6 bits Large area High power

104 ADC System-Level Design

105 1 st model Sub-ADC model

106 Dynamic performance: Output spectrum SFDR = 39dB for 1.25GHz 2.5GS/s

107 2 nd model AMS-Library Modified Model

108 Dynamic performance for sub-adc: Output spectrum SFDR = 34.5dB for 1.25 GHz 2.5GS/s

109 Static performance:

110 10 GS/s Interleaved ADC Model

111 Output spectrum for 5GHz input SFDR = 33.4dB for 5GHz 10GS/s

112 Expected Specs ADC is expected to have the following specs at 5GHz input (Nyquist frequency): Spec SNR_nominal SINAD SNR THD SDR SFDR ENOB Value db db db db db 33.4 db 3.32 bits

113 Circuits

114 Track and Hold Amplifier (THA) Track and hold Circuit: Sampling Switch Buffer TYPE Pros Open Loop High speed (90MHz - 10GHz)* Unconditionally stable Closed Loop More accurate linearity on average 50dB 78dB * Reduce charge injection Cons Pedestal error Less accurate - Poor linearity (28dB - 63dB)* Less Speed ( 240MHz)* Stability issue must be considered * Pieter Harpe, Concepts for Smart AD and DA Converters, chap.7, pp.82

115 Open Loop Track and Hold Bootstrapped Sampling switch Pros: Higher linearity Small switch size Less charge/clock injection expense: Caps are large µw power consumption Andrew Masami Abo, Design for Reliability of Low-voltage, Switched-capacitor Circuits

116 Open Loop Track and Hold Buffer Topologies

117 SF or DP? Topology Source Follower Differential Pair Gain Linearity Determined by second order effects Body effect channel length mod. Determined by first order effects Mismatch sensitivity Low High Controllability Design freedom * Pieter Harpe, Concepts for Smart AD and DA Converters, chap.7, pp.82

118 Designed THA

119 Reference Ladder To generate reference levels Stack of resistors in series voltage divider rule Alternatives: Band-gap references Adjustable references* * Ken Yang, Ramy Yousry, Tamer Ali, Hung Chen, 10Gb/s Serial I/O Receiver Based on V i bl R f ADC

120 Differential Reference ladder

121 Comparator Design Comparator consists of: Pre-Amplifier Regenerative latch

122 Pre-Amplifier Design

123 Regenerative Latch Strong-Arm Latch CML latch

124 Designed Comparator

125 Circuit results (1): THA measured specs: Process Power supply Signal range v in,pp Input common mode voltage 65 nm 1 V 1.2 V 0.6 V Output common mode voltage 0.3V 1.25 GHz input Supported Load Topology FOM_SFDR Sampling frequency ( fs ) Power consumption 31 db 300f F Source follower fj 2.5 GHz 2.44 mw

126 Circuit results (2): Reference ladder specs: Power Single resistance value Resistance Stack systematic error in reference value Comparator Specs: Power Maximum systematic offset Delay mw 4 ohm ohm ±3.6 mv 2 mw 13 mv 88.4 psec

127 Sub-ADC

128 Full Flash,Time Interleaved ADC

129 Simulation Results(1) THA output for Random input stream

130 Simulation Results(2) Reference levels for Comparators

131 Simulation Results(3) Single reference level, showing the effect of kickback noise and input feed-through

132 Simulation Results(4) static performance Analog output corresponding to output codes from the ADC

133 Simulation Results(5) DNL -using histogram Method-

134 Simulation Results(6) INL INL = +0.25/ No mis-codes

135 Power consumption distribution Total consumed power per single ADC (2.5 GSps)= 49.6 mw

136 Thermometer to binary Decoder

137 Final results Total Power FSR (DR) SNDR ENOB 158 mw 1 Vp-p db 3.1 bits INL / FOM 5GHz 1.58 pj/conversion step 28 db

138 Comparison with literature ADC Performance Survey (ISSCC & VLSI Symposium)

139 All System: TX with CTLE and VGA

140 All System: Adding ADC

141 Future work Variable reference levels digitally controlled by the equalizer Offset cancellation circuit Digital calibration for the ADC

142 Questions?

143 DIGITAL EQUALIZATION

144 Overview Digital Encoder Digital Equalization Methods Chosen Approach Adaptive Coefficients

145 Digital Encoder Why? Types Rom-based, Fat tree, BEC Chosen Approach Simulation

146 ROM-Based

147 ROM-Based

148 Fat-tree Based

149 MUX-Based

150 Bubble Error

151 Chosen Approach

152 Simulation

153 Digital Equalization Types FFE or FIR DFE

154 Feedback Forward Equalizer Serial FIR

155 Feedback Forward Equalizer Drawback

156 Feedback Forward Equalizer Parallel Processing

157 Feedback Forward Equalizer Equations :

158 Simulation

159 Decision Feedback Equalizer Type used :

160 Simulation

161 Chosen Approach Mixed Architecture

162 Simulation

163 Simulation

164 Adaptive Cofficients Two Modes for operation : 1- Training Mode 2- Decision Directed Mode

165 Adaptive Cofficients Least Mean Square : The basic premise of the LMS algorithm is the use of the instantaneous estimates of the gradient in the steepest descent algorithm

166 LMS Algorithm Implementation

167 Adaptive Coefficients LMS Types : 1- Variable Step Size Normalized LMS

168 Adaptive Coefficients 2- sign LMS (sign-sign, sign- data, sign- error) where w(n + 1) = w(n) + μu(n) sgn(e(n))

169 Questions and Discussion

170 PLL SYSTEM

171 Overview What is PLL? Block Diagram of PLL Targets and Specifications Simulations and results

172 What is PLL?

173 Block Diagram of PLL

174 Targets & Specs Targets: Eliminating Frequency & Phase errors Specifications Jitter Phase Margin K vco Icp 1ps 60 degrees 700MHz/V 150 ua

175 Block Diagram The transfer function of the system is given by: where,, and 1

176 Noise Performance in PLL

177 Simulations and Results PLL Parameters Parameter Value Reference Frequency MHz N 66 K vco BW Phase margin Peaking 700MHz/V 7MHz 60 degrees <2 db

178 Simulations and Results R =29.78KΩ

179 Simulations and Results C1 =0.22pF

180 Simulations and Results C2 =2.85pF

181 Simulations and Results Closed Loop Transfer Function

182 Simulations and Results Open Loop Transfer Function

183 Simulations and Results Closed Loop Transfer Function

184 Simulations and Results Open Loop Transfer Function

185 Simulations and Results Property C1 C2 R Value 0.22pF 2.85pF 29.78KΩ Icp 150µA Estimated rms Jitter* 47fs

186 Questions?

187 Phase and Frequency Detector (PFD)

188 Overview Introduction Design Issues Non-Idealities of PFD Dead Zone Continuous Time Approximation Different Implemented Topologies Conclusion

189 Overview Introduction Design Issues Non-Idealities of PFD Dead Zone Continuous Time Approximation Different Implemented Topologies Conclusion

190 Introduction

191 Overview Introduction Design Issues Non-Idealities of PFD Dead Zone Continuous Time Approximation Different Implemented Topologies Conclusion

192 Design Issues Function of PFD

193 Design Issues Function of PFD

194 Design Issues Function of PFD

195 Design Issues Function of PFD

196 Overview Introduction Design Issues Non-Idealities of PFD Dead Zone Continuous Time Approximation Different Implemented Topologies Conclusion

197 Non-Idealities of PFD Dead Zone

198 Non-Idealities of PFD Continuous Time Approximation PFD puts out a pulse width modulated signal and not a continuous current. Good approximation Minor errors in the calculation

199 Overview Introduction Design Issues Non-Idealities of PFD Dead Zone Continuous Time Approximation Different Implemented Topologies Conclusion

200 Different Implemented Topologies Topology 1

201 Different Implemented Topologies Topology 1

202 Different Implemented Topologies Topology 1

203 Different Implemented Topologies Topology 1

204 Different Implemented Topologies Topology 2

205 Different Implemented Topologies Topology 2

206 Different Implemented Topologies Topology 2

207 Different Implemented Topologies Topology 3

208 Different Implemented Topologies Topology 3

209 Different Implemented Topologies Topology 3

210 Different Implemented Topologies Topology 4

211 Different Implemented Topologies Topology 4

212 Different Implemented Topologies Topology 4

213 Overview Introduction Design Issues Non-Idealities of PFD Dead Zone Continuous Time Approximation Different Implemented Topologies Conclusion

214 Conclusion Comparison between topologies Topology Criteria Number of transistors Power Consumed Detection Range Topology I Topology II Topology III μ w 38 2π DR 2π Topology IV μ w 44 2π DR 2π

215 Conclusion Comparison between topologies Topology Criteria Number of transistors Power Consumed Detection Range Topology I Topology II Topology III Topology IV μw 44 2π DR 2π

216 Questions?

217 Charge Pump

218 Overview Introduction Design Issues Different Topologies Phase Noise Corners Analysis

219 Introduction UP & DOWN currents

220 Introduction

221 Design Issues Current Mismatch V DS,SAT Channel Length (L)

222 Design Issues Charge Injection

223 Design Issues Charge Sharing

224 Design Issues Reference feed through The reference feed through causes an AC signal on the control voltage at reference frequency. Causes spurs in the output spectrum.

225 Topology 1

226 Topology 1 Compliance Curve 0.13v & 0.86v

227 Topology 1 IDS Vs VDS

228 Topology 1 Transient Analysis (UP)

229 Topology 1 Transient Analysis (DOWN)

230 Topology 2

231 Topology 2 Compliance Curve 0.12v & 0.85v

232 Topology 2 IDS Vs VDS

233 Topology 2 Transient Analysis (UP)

234 Topology 2 Transient Analysis (DOWN)

235 Topology 3

236 Topology 3 Unity Gain Buffer

237 Topology 3 Unity Gain Buffer

238 Topology 3 Transient Analysis (UP)

239 Topology 3 Transient Analysis (DOWN)

240 Topology Chosen Topology 2 was used because of: Reduced charge sharing Reduced charge injection Least power ( uw)

241 Phase Noise

242 Corners Analysis Compliance curve 0.2v & 0.75v Phase Noise (at 10M) -111dBc/Hz & -125 dbc/hz

243 Questions?

244 VOLTAGE Controlled oscillator (VCO)

245 Overview VCO basics Different Topologies LC VCO Why LC? -GM vs Colpitts -GM oscillator CMOS vs NMOS and PMOS Simulation and results

246 VCO Basics VCO is a feedback system. Positive feedback Barkhausen criterion

247 Different topologies LC VCO Ring VCO

248 Different topologies Passive Devices Ring Oscillator No Passive devices so it s easier to implement LC Oscillator Spiral inductors and varactors Area Smaller area Larger area Tuning Range Large tuning range Smaller tuning range Frequency High frequency Much higher frequencies Phase noise Poor phase noise performance Better phase noise performance Power Consumption Higher power consumption Lower power consumption

249 LC VCO Why LC? Since the required output jitter from the PLL is 1ps rms, we have chosen to work with the LC VCO in order to achieve the lowest possible phase noise from the oscillator.

250 -GM oscillator vs Colpitts -GM VCO Colpitts VCO

251 -GM oscillator

252 CMOS vs NMOS & PMOS NMOS PMOS

253 Current tail problem Noise report indicated 20% of noise is from current source. On removing current source Phase noise is improved significantly.

254 Performance with current source

255 Performance with current source

256 Without current source

257 Without current source

258 Comparison Without Current tail With Current tail Power 3.7mW 3.09mW consumption Kvco 800MHz/V 550MHz/V Phase noise at -112dBc/Hz dBc/Hz 1MHz Figure Of Merit 186.3dBc/Hz 180.3dBc/Hz Figure Of Merit =10log{(fo/Δf)²/L{Δf}.P}

259 Corners Results Across different corners, phase noise has not exceeded -110dBc/Hz Locking frequency is within the range of V

260 Layout Area = µm*282.7µm

261 Area and power NMOS 105µm / 360nm PMOS 105µm/300nm Capacitance range 1.23pF 1.5pF Inductance Width = 9µm R = 40µm Turn s = 1 L = pH Q Fact or = 20.6 Area width = 153µm Area length = 147.5µm

262 Questions?

263 Divider

264 Overview Introduction Proposed Divider Divide by 2 Divide by 3 Divide by 11 Simulations and Results

265 Introduction

266 Proposed System Output of the VCO is GHz Output of the divider MHz The division ratio is 66

267 Cont d Proposed Divider

268 Divide by 2

269 Divide by 3

270 Divide by 11

271 Divide by 11

272 Simulations and Results

273 Cont d Simulations and Results Phase noise Simulation

274 Cont d Simulations and Results Power consumption Power consumption Divide by 2 Divide by 6 The whole divider 1.38 mw 3.32 mw 5.7 mw

275 Questions?

276 Clock and data recovery (CDR)

277 Overview Basic CDR CDR architectures: Single loop Dual loop PI based CDR Proposed system: Advantages Challenges

278 Basic CDR Clock recovery Data retiming

279 CDR Architectures Single loop: Disadvantages: Noisy VCO requires large BW. Large BW results in passing input jitter to output. Harmonics Large lock times

280 Dual loop One loop generates the required freq. The other tracks the phase. Advantage: BW of the two loops are independent. Disadvantages: Frequency offset and VCO matching

281 PI based CDR

282 Proposed system

283 Clocking schemes

284 Questions?

285 Digital Block (DB)

286 Overview Introduction Operation of DB Simulation Result

287 Overview Introduction Operation of DB Simulation Result

288 Introduction Fast stream of data can t be implemented directly. Parallelism is used. Power is reduced.

289 Overview Introduction Operation of DB Simulation Result

290 Operation of DB

291 Operation of DB

292 Operation of DB

293 Operation of DB

294 Operation of DB

295 Operation of DB Shift Right Shift Left Action High Low Late state: shift the data stream to the right by decreasing the delay of the delay line. Low High Early state: shift the data stream to the left by increasing the delay of the delay line. High High High impedance state: no action

296 Overview Introduction Operation of DB Simulation Result

297 Simulation Results

298 Questions?

299 Phase interpolator

300 Phase interpolator

301 Block Diagram

302 Divider

303 Divider

304 Divider The divider has two advantages for the next stages: It automatically produces in-phase and quadraturephase. It produces differential clock, so I practically have 4 phases I, Ibar, Q and Qbar.

305 Multiplexers Two 2-1 multiplexers, one for I-phase and one for Q-phase. CML multiplexers are used.

306 Selecting the quadrant Gray coded selecors. Quadrant S1 S0 1 st 00 2 nd 01 3 rd 11 4 th 10

307 Output waveform

308 Core phase Interpolator

309 Degeneration capacitance Degeneration capacitance at the input. Advantages: Eliminate the sharp edges to allow proper interpolation. Decrease the swing to drive the interpolator to a linear region.

310 Interpolation waveform

311 Simulation and results Typical corner

312 Simulation and results Ff-0deg-1.1V

313 Simulation and results Ss-125deg-0.9V

314 CML to CMOS

315 CML to CMOS

316 CML to CMOS

317 Power Consumption Stage Divider Mux Core PI CML to CMOS Total Power consumption 0.93mW 0.75mW 0.18mW 1.60mW 3.46mW

318 Questions?

319 Thank you!!!

320 Backup slides

321 Area and power (MUX) Device/Property Diff pair Select switches Current mirror Resistance Power consumption Value 2.4µm/60nm 1.2µm/60nm 29µm/240nm 1.25kΩ 0.75mW

322 Power and area (DIVIDER) Device/Property M1 M2 Value 800n/60n M3 M4 1u/60n M5 M6 1u/60n M7 M8 600n/60n Power consumption 0.93mW

323 Power (Core PI ) Device/property Diff pair Switch transistors Current sources Power consumption Value 7µm/60nm 200nm/60nm 8 µm/360nm 0.179mW

324 Questions?