A 7 bit 3.52 GHz Current Steering DAC for WiGig Applications

Transcription

1 A 7 bit 3.52 GHz Current Steering DAC for WiGig Applications Trindade, M. Helena Abstract This paper presents a Digital to Analog Converter (DAC) with 7 bit resolution and a sampling rate of 3.52 GHz to be used in communication systems exploring the high frequency spectral band around 60 GHz. The resulting DAC needs an SNDR (Signal to Noise plus Distortion Ratio) of about 35 db and an INL/DNL (Integral Non-Linearity Error / Differential Non-Linearity Error) of about 1 LSB. The DAC is to be implemented in a 28 nm CMOS technology. Index Terms Digital to Analog Converter, Current Steering, WiGig, 28 nm, High Update Rate T I. INTRODUCTION elecommunications systems nowadays require high performance and high speed digital and analog systems integrated on one chip at the lowest possible cost. These new telecommunication devices have evolved towards broadband systems with moderate signal-to-noise ratios using data converters that according to [1] have to operate at ever increasing sampling rates, but requiring less precision. An example of these new requirements is the use of the 60 GHz radio frequency (RF) band extended from the standard Wi-Fi, also known as WiGig (IEEE ad standard), with ultrawide communication bandwidth. Today there is a growing need for energy efficient systems, especially in the communications mass market. Reducing the power consumption of the devices and hence having a more efficient system can be achieved by downscaling the technology. However the scaling of the technology in DACs is very challenging because the reduction of the gate oxide thickness imposes a limit to the maximum voltage that can be applied to the device, forcing in many cases the circuits to be design with two supply voltages. Moreover, the threshold voltage of the transistors cannot be scaled accordingly. So designing DACs becomes more challenging because the freedom of voltage margins are much lower. These new CMOS reduced technologies also feature reduced voltage gain of the transistors, increasing the distortion of the DAC as stated in [2]. Another major challenge on DACs designed for The work presented in this paper was developed with the help of Synopsys in particular of Engineer António Leal with Synopsys and Professor Jorge Fernandes with Instituto Superior Técnico, Lisbon. Trindade, M. Helena, Author is with Instituto Superior Técnico, Lisbon, Portugal. ( helenatrindade92@gmail.com). communication applications, according to [3], is that they require a large SFDR, which is not straightforward to achieve at high signal frequencies. This project will be a contribute to the development of DACs which combine a high update rate and a low power supply through the use of different approaches to the blocks used and by a careful layout of the circuit. By choosing the right configurations for the blocks of the circuit it is assured the correct functioning for a power supply of 0.9 V and through the correct dimensioning it is assured the desired specifications for the DAC at a high update rate of 3.52 GHz. II. DIGITAL TO ANALOG CONVERTER: DEFINITION AND CHARACTERIZATION The DAC is a system that reconstructs an analog waveform according to a digital word input. It acts like a sample and hold circuit throughout the signal reconstruction. During each clock cycle, the output, which is given according to the input word, is steady so the resulting signal is a series of modulated rectangular pulses. In order to achieve the performance specifications required in a DAC, there are a number of important parameters that need to be measured, like the SFDR (Spurious Free Dynamic Range), SNDR, INL/DNL, etc. Depending on the intended use of the DAC some of these parameters matter most for achieving the specifications. The difference to the ideal behavior is characterized by a number of performance metrics that characterize the DAC static and dynamic performance. The architecture used for a DAC depends on the performance parameters in which we have interest. The output value of the DAC can be formed using voltage, current, charge or time. Some DACs enable high resolution but require a large area while others may consume more power but are faster. So there are three main classes of DACs based on the type of output they provide: resistors (voltage), capacitors (charge) and current sources (current). Every one of them generates a certain quantity at the output according to the digital input code. In this project the Current Steering Architecture which provides a current, through the combination of the values of different current sources is used. An example of this architecture is presented in Fig.1. This converter is build with active current sources in which the current cell can not be turned on or off, instead they have to be steered, to the appropriate summing node(s) so the biasing required for these circuits is not disturbed.

2 corresponding current source. A VHDL decoder which allows any switching scheme because it implements the row and column decoder in one single block in VHDL. The Custom made decoder which exploits the optimal solution for the implementation but requires a lot of effort in design. Fig.1. Current Steering Architecture with segmented implementation. III. CURRENT STEERING ARCHITECTURE The Current Steering Architecture was chosen for its simplicity, because it is intrinsically faster and has a more linear behavior than the resistor and capacitor based architectures, although in general it has large power consumption. Since the main constraints in this project are the high update rate and the linearity this architecture proved to be the adequate choice. This architecture presents three possible implementations of the coding of the bits that control the switches of the current sources: the binary implementation, in which the input bits directly control the current sources, the unary implementation, in which the input bits are thermometer decoded before controlling the current sources and the segmented implementation, in which part of the input bits directly control the current sources and the other part of the input bits is thermometer decoded. It is essential to understand the different basic blocks that constitute the DAC with Current Steering architecture since each block has a specific function in the circuit and the design of each component is essential to guarantee the overall performance. Since there are three different types of codification schemes for the input bits that control the switches the basic blocks will vary according to the implementation chosen. A. Basic Blocks The basic blocks of a Current Steering DAC with segmented implementation are the Thermometer Decoder, Latency Equalizer, Latch and Driver, Biasing Circuit, Cascode Current Source and Current Source Array. The basic principle of operation of the Segmented Current Steering is that the N input bit code is split in N LSB least significant bits and N MSB (N=N LSB +N MSB ) most significant bits. The N MSB bits are thermometer decoded and while the decoding occurs the N LSB bits are delayed in the Latency Equalizer. When all the processing of the bits is finished the current sources are commuted according to the bits by complementary switches synchronized by latches and drivers circuits. An example of this type of overall architecture is presented in Fig.2. The Thermometer Decoder receives the input bits of the DAC and translates the input code into a thermometer code at its output. It can be a row and column decoder which uses the input bits to decode the row and column position of the Fig.2. Basic Block Diagram for a Segmented Current Steering DAC. The Latency Equalizer guarantees the same overall delay on all the bits that go to the driver and switches. Since going through the decoder adds a delay to the most significant bits we have to guarantee that the current sources are active at the same time for all the bits, hence the need for a latency equalizer for the least significant bits. The Driver block includes the drivers, the level shifters and latches. The driver provides the signals that control the switches associated with each current cell. It guarantees that both switch transistors of the current cell are never simultaneously off, preventing glitches at the output. The level shifter can be used when there is the need for converting the voltages of digital logic circuits, where the input bits are processed in the DAC, to the voltages of the analog circuits if they present two different power supply voltages. The latches associated with the level shifter assure the synchronization and shape of the signals to improve the dynamic performance of the circuit. The Current Source Array includes all the current sources that are activated by the driver and latch circuit according to the bits of the input code. The topology selected for the configuration of each current cell has to take into account random errors that can be minimized by the area of the transistor operating as current source and the effect of finite output impedance that can be mitigated by recurring to the cascode configuration. The simplest topology consists of two MOS transistors working as switches operating in saturation with complementary gate signals and a single MOS transistor operating in saturation with constant gate-source voltage. To ensure higher output impedance we can use a cascode current cell. These two types of topology of the current cell are presented in Fig.3 a) and Fig.3 b).

3 Fig.3. Topology of a current cell a) single and b) cascode. The correct functioning of the Current Source Circuit is dependent on the Biasing Circuit which defines the gate voltages for the cascode and current source transistors. The Biasing Circuit consists on a set of current mirrors. The design of these current mirrors depends on important aspects like the supply voltage, process and temperature, output resistance and matching. B. Static and Dynamic Analysis The design of a Current Steering DAC for high resolution or high update rates like the one presented in this project requires a thorough understanding of its static and dynamic behavior. The performance of the DAC due to its static behavior is related with the matching of the current source transistors. According to [2] there are two types of errors associated with this matching, the random errors due to process variations but also the systematic error due to various gradients. The dynamic behavior of the DAC has a main constraint due to the fact that for high speed, the second and third harmonic distortion, in the frequency domain, are a limitation for the spurious free output signal bandwidth. It is crucial to understand this constraints and how to reduce their effect on the performance of the DAC so we can achieve better results. The static performance of a DAC is intrinsically related with the mismatch of the current source transistors in this architecture. The mismatch can be defined as the variation in physical quantities of identically designed devices. The matching errors consist of both random and systematic errors which have to be considered. Systematic mismatch: comes from for example gradients in process parameters, like oxide thickness, doping or temperature. They can be overcome by using appropriate switching schemes, calibration or randomization. Random errors: due to random variations during the fabrication process of different DACs, in the same process technology, results different INL performances. The static matching of the current sources sets a lower limit to the INL that is possible to achieve and to the distortion performance of the DAC. According to [4] the current mismatch has four major physical effects: edge effects, implantation and surfacestate charges, oxide effects and mobility effects. Regarding the systematic errors the main contributors according to [5] are: Transistor Mismatch Effect: due to the fact that the mismatch behavior of a transistor is dependent of its surroundings it can have a negative effect on the static performance of the DAC. To overcome this effect it should be used dummy transistors around the current sources to ensure identical surroundings; Voltage Drop in the ground line: results in nonlinearity errors because it will change the output current of different transistors on the same row. This effect on NMOS current sources can be minimized by either using appropriate switching schemes or by using wide power supply lines. Process and Temperature Gradients: Increasing one bit in the resolution of the DAC can double the area occupied by the unity current source and doubles the number of current sources in the current source array. Increasing four times the area of the current source array for every extra bit results in an area so large that gradients have to be considered. These temperature and process gradients cause non-linearity errors that by using special switching schemes can be compensated. IV. DESIGN METHODOLOGY OF THE DAC In this chapter the circuits used for the different blocks of the DAC will be presented taking into consideration the restrictions and specifications of the DAC required in this project. A. Level of Segmentation The first issue to be addressed when designing the DAC is the level of segmentation. To define the level of segmentation, we can apply different approaches but for this specific project we used the Monte Carlo Approach with simulations for different levels of segmentation and analysis of the results. According to those conclusions the level of segmentation for this specific DAC was defined. A high level model of the DAC was developed in Matlab, which consisted in the computation of the INL/DNL for each input code and the computation of the dynamic metrics like SFDR, SNR, SNDR, THD and ENOB. This model considered: the level of segmentation (N LSB - number of bits in binary coding and N MSB number of bits in thermometer coding), the standard deviation of the LSB current source (σ LSB (I)/I), the sampling frequency (F s ), the input frequency (F i ) and the input signal. It was considered a unary implementation (7MSB/0LSB) and a segmented implementation (6MSB/1LSB) for the DAC using this model for a sampling frequency of 3.52 GHz and an input frequency of 1.76 GHz. From this analysis, for which the results are presented in Table I, it was possible to conclude that since an extra bit in unary codification doubles the area occupied by the latches and increases the complexity of the layout and since by comparison of the values of the simulation presented the differences between the dynamic performance of the two segmentations considered are not relevant to consider the unary implementation of the 7 bits, it was chosen the segmented implementation with 6 bits thermometer decoded and 1 bit in binary codification.

4 TABLE I RESULTS OF THE HIGH LEVEL MODEL OF THE DAC Measure 6 MSB/1LSB 7MSB/0LSB INL_yield (99.75%) DNL_yield (99.75%) SFDR SNDR SNR B. Current Source Design The simplest design of the current cell is a single MOS transistor biased with constant gate to source voltage that operates in saturation region. The switching consists in two MOS transistors operating in saturation as switches with complementary gate signals. The design of this current cell requires a minimum area for the transistor of the current source, so the random errors are small and their impact on the relative standard deviation can be neglected. The area of the transistor can be obtained taking into account the formula (1) obtained from the Pelgrom Model. Defining the value required for the yield, we derive the precision for the current cell ( σ i LSB ) i LSB and obtain the minimum area: (WL) min = (A 4A β 2 2 Vt + (V GS V t ) 2) / (σ i LSB ) (1) i LSB i LSB = I FS 2 N = 1 2 μ 0C ox W L (V GS V t ) 2 (2) From these expressions we conclude that the only degree of freedom is the gate overdrive voltage given by: V OV = V GS V t (3) Increasing the gate overdrive voltage results in a decreased of the minimum area required. So in order to define this voltage we can choose it so that the current source minimizes the systematic errors. For large values of area, the mismatch is mainly determined by A β. These systematic errors are mainly caused by the layout and can be optimized by the switching scheme and a careful layout generation but the finite output impedance is a major effect. To minimize this effect we can use a topology with cascode configuration. In general the output impedance of one single transistor is not high enough to meet the required static output impedance requirements and the large area defined by the matching requirements results in a very large parasitic capacitance that deteriorates the high frequency linearity. Using the cascode topology increases the output impedance in both DC and high frequencies. According to [6] in a fully differential architecture only the even harmonics will be suppressed, while the odd harmonics will not be canceled in the output signal. So the main contribution for the limitation on the SFDR of the DAC will be given by the third harmonic. For Z out N Z load the third harmonic distortion (HD 3 ) is given by: HD 3 N2 2 2 A sin Z load 2 (2Z out + NZ load ) 2 N2 2 A sin Z load 2 (4) 16 2 Z out where A sin is the normalized amplitude of the sine wave processed by the DAC, Z load is the load impedance, N is the number of current sources of the DAC, Z out is the output impedance of the unit current source. The third harmonic distortion (HD 3 ) is related with the SFDR by: SFDR 20 log 10 HD 3 (5) In the case of the DAC in this project we have: Z load = 50Ω A sin = 1 N = 2 N bit = 128 SFDR > 35 db which results in an output impedance for the unit current source of: Z out > 12 kω To assure a voltage swing in the output of V swing = 0.45 V the full scale current (I FS ) of the DAC is: I FS = V swing = 0.45 = 9 ma (6) Z load 50 The current of the LSB current source is given by: I FS I outlsb = 2 N 70.87μA (7) bit 1 The current of each MSB current source for a segmentation of 1LSB/6MSB is given by: I outmsb = 2I outlsb μA (8) The transistors of the current source were dimensioned according to equations (1) and (2) so all the transistors were in saturation for all the corners considered. The resulting output current and output impedance are shown in Table II. TABLE II OUTPUT CURRENT AND OUTPUT IMPEDANCE OF THE CURRENT SOURCE I out MSB = 2I out LSB (μa) Worst Corner Typical Best Corner Worst Corner Z out (kω) Typical Best Corner C. Current Source Design The correct design of the Biasing Circuit is essential to the correct functioning of the DAC. This block directly feeds the transistors of the current source. The main concern when dimensioning the current source reference is to guarantee that

5 it is independent of the power supply and of the temperature so the resulting current that is mirrored is as stable as possible. The biasing circuit used in this project is a current mirror as the one presented in Fig.4. This voltage reference generator was chosen since it is very low power, works for low supply voltages from 0.9V to 4V and produces a voltage reference of about 670 mv. The circuit for this voltage reference generator is presented in Fig.6. formed Fig.6. Voltage Reference Generator of the OpAmp. Biasing Circuit Fig.4. Biasing Circuit Current Source The circuit is formed by the cascode current mirror M cs3 and M cas3 that bias the cascode transistor (M cas ) of the current source and M cs2 and M cas2 that bias the current source transistor (M cs ). The reference currents I ref1 and I ref2 are generated by the current reference generator circuit shown in Fig.5. The resulting values for the current references I ref1 and I ref2 which bias the current source and cascode transistors are presented in Table III. TABLE III REFERENCE CURRENTS OF THE BIASING CIRCUIT I Ref1 (μa) Worst Corner Typical Best Corner Worst Corner I Ref2 (μa) Typical Best Corner Fig.5. Current Reference Generator of the Biasing Circuit. This circuit consists on a set of current mirrors that mirror a current established by the resistor R Ref. The Operational Amplifier (OpAmp) bias the gate of the transistor M P1 in order to guarantee that the voltage in R Ref is equal to V Ref which is the voltage reference of the OpAmp. The resistor R Ref is chosen so the current I Ref has the desired value. The use of the transistor M P2 as a cascode makes this current reference much more stable, so in order to bias M P2 (V casc ) the circuit with transistors M P3, M N1, M P4 and M N2 is used. The cascode current mirror with transistors M P5, M P6 and M N3 defines the gate voltage (V gcas ) for the cascode transistors M N4, M N7 and M N9, while the cascode current mirror with transistors M P7, M P8, M N6, M N4 and M N5 defines the gate voltage (V gsrc ) of transistors M N6 and M N9. The branch with transistors M N6 and M N7 defines the current I Ref2, while the one with transistors M N8 and M N9 defines the current I Ref1. The voltage reference V Ref of the OpAmp is generated by a voltage reference generator based on the one presented in [7]. D. Latch and Driver Design The dynamic performance of a current steering DAC is greatly related with the degradation caused by the imperfect synchronization of the control signals at the switches. In order to minimize this effect a careful design of the driver is necessary. The Driver used in this project is similar to the one used in [8] and can be seen in Fig.7, where a PMOS is placed in parallel with each cross-coupled PMOS at the top of the circuit in order to obtain immediate charging of the output nodes with falling inputs. By doing this, the intrinsic delay is removed from the operation of the circuit. The NMOS passtransistors in the input path keep a single phase input clock and deal with low power supply. This results in a rise time much faster than the fall time of the driver circuit, and a high crossing point of the differential output can be achieved directly at the output of the latch. A lower crossing point is achieved by scaling of the gate width of the PMOS or NMOS. The small inverters at the bottom of the circuit assure the stabilization of the synchronized inputs and suppress the clock feed through.

6 Fig.7. Circuit of the Driver. Fig.9. Row and Column Matrix Decoder Since the output of the driver connects directly to the switches there is a need to a perfect synchronism of the output signals of the driver. Since with this configuration the input signals of the driver come directly from the decoder which can have slightly different delays according to the logic gates used to decode the bits and for the high update rate required in this project these delays can be a limitation, a flip flop was used in association with this circuit in order to guarantee that the signals are stable before the edge of the clock. The flip flop circuit used before the driver is presented in Fig.8. Fig.10. Local Decoder of the Row and Column Matrix Decoder The logic circuit of the row and column decoder is the same since we use the bits in sequence, for the row decoder the bits B 1, B 2 and B 3 and for the column decoder the bits B 4, B 5 and B 6, considering B 0 the LSB bit which is not thermometer decoded. The corresponding logic circuit was deducted from its truth table and the resulting logic gates for each output of the row/column are presented in Fig.11. Fig.8. Flip flop circuit used before the driver. E. Decoder Architecture After defining the level of segmentation of the DAC and when using either a segmented codification or a unary codification there is a need for a thermometer decoder. The use of a row and column decoder may result in a larger accumulation of systematic and graded errors but since we only have 7 bits and we need to use 6 bits in the thermometer decoder the row and column decoder seems to be the most adequate solution. A representation of the decoding scheme where each 3 bits of the 6 MSB are used to decode 7 rows or 7 columns of the matrix is represented in Fig.9. There are an additional row and an additional column which are a combination of supply voltage and ground. The matrix has 63 local decoders each associated with a current source with the logic presented in Fig.10. Fig.11. Logic Circuits for the outputs of the row/column decoder. In the dimensioning of the decoder the restriction is to make sure that the logic gates are as fast as possible. To ensure that the data of all the bits is available for the latches at the same time a Latency Equalizer was used for the LSB bit, which consists on an inverters chain with four inverters. The resulting decoding scheme for the DAC is presented in Fig.12. Fig.12. Complete Decoding scheme of the DAC.

7 The topology of the registers used to ensure the synchronization of all the bits is represented in. In this circuit the clock signal has a delay (CLK_late) ensured by the inverters in the clock driver to make sure that all the data is transferred to the output before the new data comes in. The data is stored in the register on the rising edge and it is available at the output on the falling edge of the clock. F. Clock Driver Fig.13. Schematic of the Register. The clock driver is used to drive the large capacitive loads of the on chip and off chip loads. It is used a buffer circuit which consists in a string of inverters that is dimensioned taking into consideration the input load (C in ) and the output load (C load ) that need to be driven. Each of the N inverters of this chain is larger than the previous by a factor of α as presented in Fig. 14. The cascade of inverters was dimensioned using 5 inverters and 2 < α < 4 in each of the stages of the inverter. G. Design Constraints Fig. 14. Clock Driver. The design of the DAC has to take into consideration its main constraints since they affect the behavior of the circuit. They can be crucial when trying to meet the specifications and matching the requirements, so understanding how to reduce their effect or how to take advantage of them becomes essential. According to [9] the potential of the Current Steering DAC to achieve high speed operation is similar to the potential to exhibit non-linear behavior, so the knowledge of the main problems and their causes is crucial to achieve the higher performance possible. High frequency linearity is mostly dependent on the time domain errors like the output impedance modulation, switching behavior and timing inaccuracies Matching: The transistor mismatch in the current source can be a source of nonlinearity for the circuit, since a deviation from the ideal current cell behavior will result in a spectral impurity. In order to reduce its effect, a good matching with an area of the gate wide enough, short distances between transistors and an ensured similar environment through the use of dummies needs to be used. Output Impedance: The output impedance is a limitation due to amplitude losses caused by the modulated output impedance and the frequency dependency of the impedance. Considering that the output impedance of each individual cell is given by the combination of a resistor in parallel with a capacitor, the total output resistance of the DAC is a function of the input signal and the time constant of the output pulses is modulated by the input signal. As stated in [6] and analyzed before, the output impedance causes the second harmonic distortion to be the main cause of errors, being this effect reduced by the use of a differential output rather than an single ended output. Switching Errors: There are two main problems related with the switching of the MOS transistors. The first problem according to [9] is related with the characteristic of the MOS transistor which presents a switching on and switching off asymmetrical behavior. While one switch transistor turns on it reaches a different operation region in a different time than the one that turns off, resulting that when both transistors are driven by complementary gate signals during a period of time both switches will not be conducting. This causes a choking of the node that connects the switches and the cascode transistor, which discharges abruptly, creating current spikes. As soon as one of the transistors is turned on it is forced to recharge this node instead of delivering the current to the output which prolongs the current spike until the capacitance associated with this node is charged. This spikes affect the common nodes of the circuit and the biasing voltages of the current source and cascode become modulated by the switching which is a source of non-linearity. The second problem is also related with the interaction between the cells via a common node that is shared. While the previous problem is related with the dependency of the interaction that causes the spike to appear at the common node this problem relates to the fact that the switching branch that is turned on cannot shield the common node between the cascode transistor and the switches and the output signal appears at the common node. For a variation in the output a variation in the transient signal at the common node will appear and all switch transistors once again will be affected in the same way by a function of the input signal. The problem does not only result from the interaction on the common node between the cascode transistor and the switches but also due to the fact that the output node (V out ) is shared. Timming Inaccuracies: A timing mismatch of the DAC elements occurs when some of the cells are updated with a slightly different timing compared to others and this difference can be a source of non-linearity as stated in [6]. According to [9] timing inaccuracies in the cells nowadays are related with the clock signal distribution network, clocked units, drivers and switches. It is essential to ensure that the clock signal reaches many locations of the DAC simultaneously and with the correct shape because a difference in the clock arrival between two points or a clock signal with an incorrect pulse shape may cause functional errors in the DAC clocked elements.

8 H. Results and Conclusions After the dimensioning of all the blocks the complete circuit was simulated considering the variations in corners and the SFDR, SNDR, SNR, THD and V out were measured. For an update rate of f clock = 3.52 GHz and an input signal with f i = 1.73 GHz the values obtained for these measures are presented in Table IV. TABLE IV DYNAMIC PERFORMANCE OF THE SCHEMATIC CIRCUIT Corner # SFDR SNDR SNR THD V out máx (V) The V swing of the DAC which corresponds to the V out máx where all the bits are 1 and the current is at full scale varies from 0.49 V through 0.58 V for a R load of 50 Ω the full scale output current of the DAC varies from 9.8 ma through 11.6 ma. The spectrum of the differential output of the DAC for the typical corner (corner 0) is presented in Fig From the results obtained for the schematic circuit we can conclude that the worst SFDR performance happens for the variations of corner 1 which presents a SFDR of 45.7 db and the best performance of 49.8 db occurs with the variations of the corners 2, 3, 8, 9, 10 and 14. Regarding the SNDR the specification is for a SNDR around 35 db which is guaranteed in all corners being the worst value obtained for corner 1 of 40.2 db. The best SNDR performance is of 41.6 db and occurs for corner 4. The ideal SNR of the circuit, being N the number of bits, is given by: SNR = 6.02 N = 43.9 db (12) Through comparison of the results obtained for the SNR we conclude that the maximum difference to the ideal SNR is of 3.7 db for corner 1 which presents a SNR of 40.2 db. The best SNR occurs for corner 4 which presents a SNR of 41.6 db which is still 2.3 db lower than the ideal value. Concerning the THD the best corner which presents a lower harmonic distortion is corner 8 with db while the worst corner which presents the highest harmonic distortion is corner 2 with 65.7 db. Fig.15. Spectrum of the differential output of the DAC for corner 0. The spectrum of the signal gives us information about the spectral impurities and the dominant harmonics of the signal. From Fig.15 we can observe that the highest spur occurs at 1.68 GHZ with 49.0 db which corresponds to the SFDR. In the spectrum shown the 1 st harmonic is at 1.73 GHz which is the fundamental tone with 0 db, the image of the 2 nd harmonic is at 55 MHz, the image of the 3 rd harmonic is at 1.68 GHz. The 3 rd harmonic becomes the main limitation for the SFDR since the 2 nd harmonic is suppressed because the output is differential. In the case of the typical corner the 2 nd harmonic at 55 MHz presents 70.2 db. V. LAYOUT With recent technologies the layout and packaging have become a greater limitation on the circuits performance. While the scaling of the device resulted in an increase of the speed of the transistors, there are also non idealities and interactions in the layout that limit the speed and precision. For each specific technology there are a set of defined rules that need to be applied during the layout of the circuit in order to ensure the proper fabrication of the transistors and interconnects despite the variations that may occur during each step of fabrication. There are layout techniques used to minimize the unwanted known effects like mismatch, noise, etc. A. Layout of the Blocks The design of the layout of the circuit was planned to minimize the area occupied and to assure that the connections

9 between the blocks were also minimized. After the layout of each block the resistances and capacitances of the block were extracted and the block was simulated. The circuit was separated in four different blocks for layout: Clock Driver, Biasing Circuit, Decoder and Current Source. The Decoder block includes the decoder and the registers while the Current Source block includes the latches, cascodes, switches and current source transistors. Clock Driver circuit were in the same conditions dummy transistors were used to surround the circuit. 1) Current Source Block In the layout of the Current Source Block all the connections were designed to be symmetric and to be the smallest possible since the capacitance effects presented to be critical. To reduce the interaction between the different signals in the latch circuit decoupling lines of supply voltage were used between the signal lines. To improve the layout of this block, common centroid technique was used in the matrix of current sources to decrease the effects of the gradients. The final layout of the Current Source Block is presented in Fig.16. Fig.17. Layout of the Biasing Circuit. Fig.18. Layout of the Clock Driver. 4) Decoder Block The Decoder Block considers the Registers, Latency Equalizer and Decoder of the Thermometer Bits. The layout of this block was planned to have the same width has the Bank of Latches since each decoder of the Matrix Decoder connects to an individual latch. To minimize delays between the decoding a tree distribution of the input clock of the registers was used. The layout of the Decoder Block is presented in Fig.19. Fig.16. Layout of the Current Source Block. 2) Biasing Circuit The current source and cascode transistors are biased by a stable biasing circuit. In this layout there was special attention in the OpAmp to ensure that the layout was as much symmetrical as possible so both branches of the differential pair would see the same capacitances and resistances. For the Current Reference Generator there was special attention to divide the transistors in fingers to minimize the occupied area. The final layout of the Biasing is presented in Fig.17. 3) Clock Driver The layout of the Clock Driver was planned according to the rest of the blocks layout. Since the resistance is the main constraint for the propagation of the clock signal throughout the Clock Driver large metal lines were drawn through the propagation path resulting the layout presented in Fig.18. To minimize etch effects and ensure that the transistors in the Fig.19. Layout of the Decoder Block. VI. RESULTS AND CONCLUSIONS After the layout of each individual block was complete all the blocks were extracted and the complete circuit was simulated being the results presented in Table V. The complete layout of the circuit presented in was planned but it is still under improvement since the connections of the biasing

10 circuit presented to be critical for the performance of the circuit. The initial layout of the complete circuit is presented since the final positions and dimension of the circuit will not be changed. Corner # TABLE V DYNAMIC PERFORMANCE OF THE LAYOUT BLOCKS SFDR SNDR SNR THD V out máx (V) From the results presented we conclude that the circuit meets the specification of 35 db of SNDR for all corners for a clock frequency of 3.52 GHz and an input frequency of 1.73 GHz for the digital input code. In most corners there is a degradation from the performance in schematic to the layout, being the most expressive differences in the V out máx and THD of the circuit. Since the circuit was dimensioned to support 0.45 V of full scale output voltage there will be further improvements on the routing in the Current Source Circuit which presented the greater losses in terms of output current. The layout of the circuit presents a length of 170 μm and a width of 170 μm which results in an area of mm 2. VII. REFERENCES VIII. [1] P. Palmers and M. Steyaert, "A 10-Bit 1.6 GS/s 27-mW Current Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS," IEEE Transactions on Circuits and Systems I, pp. Vol.57, Nº11, pp , November [2] P. Palmers, M. Steyaert and X. Wu, "A 130 nm CMOS 6- bit Full Nyquist 3 GS/s DAC," IEEE Asian Solid-State Circuits Conference, pp , December [3] K. Bult and C. Lin, "A 10-b, 500 MSamples/s CMOS DAC in 0.6 mm²," IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp , December [4] A. Duinmaijer, M. Pelgrom and A. Welbers, "Matching Properties of MOS Transistors," IEEE Journal of Solid- State Circuits, vol. 24, no. 5, pp , [5] A. Bosch, W. Sansen and M. Steyaert, Static and Dynamic Performance Limitations for High Speed D/A Converters, Boston: Springer Science+Business Media, LLC, [6] M. Clara, High-Performance D/A-Converters, Berlin: Springer, [7] G. De Vita and G. Iannaccone, "A Sub-1-V, 10ppm/ºC. Nanopower Voltage Reference Generator," IEEE Journal of Solid-State Circuits, vol. 42, no. 7, pp , July [8] A. Bosch, W. Sansen and M. Steyaert, "Solving Static and Dynamic Performance Limitations for High Speed D/A Converters," Analog Circuit Design, pp , [9] R. Geiger, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill Book Company, Fig.20. Initial Layout of the Complete Circuit.