Clockless Circuits. CS150 Adam Megacz 5-May-2009

Transcription

1 lockless ircuits S50 Adam Megacz 5-May-2009

2 Outline lockless ircuits Signal Transition Graphs Muller Elements Foam Rubber Wrapper and Speed Independence Micropipelines KLA Demo 2

3 lockless ircuits ircuits without a clock Not synchronous Often called asynchronous (Warning: highly overloaded term!) 3

4 Are you nuts? 4

5 Are you nuts? Why get rid of clocks? 4

6 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. 4

7 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). 4

8 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. 4

9 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. 4

10 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. They link correctness to performance (ie delay). 4

11 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. They link correctness to performance (ie delay). Design does not meet timing => computes the wrong answer 4

12 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. They link correctness to performance (ie delay). Design does not meet timing => computes the wrong answer Robustness 4

13 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. They link correctness to performance (ie delay). Design does not meet timing => computes the wrong answer Robustness Room temperature changes => computes wrong answer 4

14 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. They link correctness to performance (ie delay). Design does not meet timing => computes the wrong answer Robustness Room temperature changes => computes wrong answer Voltage sags => computes wrong answer 4

15 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. They link correctness to performance (ie delay). Design does not meet timing => computes the wrong answer Robustness Room temperature changes => computes wrong answer Voltage sags => computes wrong answer Mildly defective (slow) transistor => computes wrong answer 4

16 Are you nuts? Why get rid of clocks? locks use power even when no computation is taking place. lock trees consume area (repeaters and wires). Jitter limits maximum frequency of a widely-distributed clock. EMI and power consumption profiles. They link correctness to performance (ie delay). Design does not meet timing => computes the wrong answer Robustness Room temperature changes => computes wrong answer Voltage sags => computes wrong answer Mildly defective (slow) transistor => computes wrong answer Expand your mind... fun to think about! 4

17 A Simple SR Latch set X X reset out 5

18 A Simple SR Latch set= X X reset=0 out 6

19 A Simple SR Latch set= X reset=0 out 7

20 A Simple SR Latch set= 0 reset=0 8

21 A Simple SR Latch set=0 X X reset= out 9

22 A Simple SR Latch set=0 0 X reset= out=0 0

23 A Simple SR Latch set=0 0 reset= out=0

24 A Simple SR Latch set=0 X X reset=0 out 2

25 A Simple SR Latch set=0 X X reset=0 out 3

26 Reasoning About the SR Latch This SR Latch is a clockless circuit How can we analyze it? State machines? FSM diagrams assume a clock Answer: Signal Transition Graphs set X reset X out 4

27 Signal Transition Graph out=0 set X reset X out 5

28 Signal Transition Graph out=0 reset= reset+ out=0 set X reset X out 6

29 Signal Transition Graph out=0 reset= resetreset+ out=0 set X reset X out 7

30 Signal Transition Graph out=0 reset= setout=0 set+ resetreset+ set= set X reset X out 8

31 Signal Transition Graph reset- out=0 reset= reset+ out=0 set+ out=0 set= set+ set= set- set X reset X out 9

32 Signal Transition Graph reset- out=0 reset= reset+ out=0 set+ out=0 set= reset+ set+ reset= set= set- set X reset X out 20

33 Signal Transition Graph reset- out=0 reset= reset+ out=0 set+ out=0 set= outout+ reset+ set+ reset= set= set- 2

34 Signal Transition Graph reset- out=0 reset= reset+ out=0 set+ out=0 set= outout+ reset+ set+ reset= reset- glitch! set- set= 22

35 Signal Transition Graph out=0 reset= set+ resetreset+ out=0 setglitch! out=0 set= outout+ reset+ set+ reset= reset- glitch! set- set= 23

36 Signal Transition Graph illegal! set+ out=0 reset= resetreset+ out=0 set+ out=0 set= reset+ illegal! out- out+ illegal! set+ reset= reset+ set+ set set= reset+ illegal! 24

37 Understanding a lockless ircuit.decide which inputs and outputs your module exposes to the environment (set, reset, out) module set reset out environment 25

38 Understanding a lockless ircuit.decide which inputs and outputs your module exposes to the environment (set, reset, out) 2. reate a Signal Transition Graph module set reset out environment 25

39 Understanding a lockless ircuit.decide which inputs and outputs your module exposes to the environment (set, reset, out) 2. reate a Signal Transition Graph 3.Determine which transitions are permitted and which are not. module set reset out environment 25

40 Understanding a lockless ircuit.decide which inputs and outputs your module exposes to the environment (set, reset, out) 2. reate a Signal Transition Graph 3.Determine which transitions are permitted and which are not. 4.Express this as a set of rules that the environment must follow: set and reset may never be high at the same time if out=0 and the environment raises set, it must hold it high until out rises if and the environment raises reset, it must hold it high until out falls set reset module environment out 25

41 Recap Understanding clockless systems Signal Transition Graphs instead of Mealy/Moore FSMs States determined by input/output levels At least one state for every possible combination of levels Arcs determined by input and output transitions... rather than input level when the clock hits Some transitions are forbidden Missing input transitions determine restrictions on environment Missing output transitions determine circuit s behavior So do real clockless system designers work with Signal Transition Graphs all day? 26

42 Recap Understanding clockless systems Signal Transition Graphs instead of Mealy/Moore FSMs States determined by input/output levels At least one state for every possible combination of levels Arcs determined by input and output transitions O(2 n)... rather than input level when the clock hits states! Some transitions are forbidden Missing input transitions determine restrictions on environment Missing output transitions determine circuit s behavior So do real clockless system designers work with Signal Transition Graphs all day? 26

43 Petri Nets, Process Algebras We re trying to design circuits Just a preview ircuits 27

44 Petri Nets, Process Algebras We re trying to design circuits Just a preview We can use Signal Transition Graphs, but they get big fast STGs ircuits 27

45 Petri Nets, Process Algebras We re trying to design circuits Just a preview We can use Signal Transition Graphs, but they get big fast Petri Nets (PNs) A more natural clockless FSM analogue Size proportional to the amount of relevant state in the system Very straightforward compilation from PN=>STG=>ircuit One tool for this is called PETRIFY Sadly, all interesting analyses on PNs are PSPAE-complete. PNs STGs ircuits 27

46 Petri Nets, Process Algebras We re trying to design circuits Just a preview We can use Signal Transition Graphs, but they get big fast Petri Nets (PNs) A more natural clockless FSM analogue Size proportional to the amount of relevant state in the system Very straightforward compilation from PN=>STG=>ircuit One tool for this is called PETRIFY Sadly, all interesting analyses on PNs are PSPAE-complete. Process Algebras This leads us to a variety of process algebras Higher level Often restricted in some way (ie exist some PNs with no corresponding PA term) to get tractable analysis Process Algebras PNs STGs ircuits Tangram, Haste, SP, S, HP, GasP diagrams, etc. 27

47 Announcements 28

48 Back to Signal Transition Graphs What does this STG describe? out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ out+ out+ B+ A+ B- A- out- A B? out A- B- 29

49 Back to Signal Transition Graphs What does this STG describe? out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ out+ out+ B+ A+ B- A- out- A B? out A- B- 29

50 Back to Signal Transition Graphs What if I delete the two green arcs? out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ out+ out+ B+ A+ B- A- out- A B? out A- B- 30

51 Back to Signal Transition Graphs What if I delete the two green arcs? out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ B+ A+ B- A- out- A B? out A- B- 30

52 Back to Signal Transition Graphs What if I delete the two green arcs? out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ B+ A+ B- A- out- A B? out A- B- Output rises when both inputs are high, falls when both are low. 30

53 Back to Signal Transition Graphs What if I delete the two green arcs? out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ B+ A+ B- A- out- A B? out A- B- Output rises when both inputs are high, falls when both are low. 30

54 Muller -Element Majority gate with output looped back A two-voter election with incumbent advantage in event of a tie majority gate c Muller Element c a 0 M = = a b a b b 0 0 c c 3

55 Foam Rubber Wrapper ritera for speed-independent circuits Adding or removing delay at the inputs or outputs of the circuit should never change behavior. Assuming the environment does not attempt transitions which are prohibited in the STG. Imagine a foam rubber wrapper around the circuit. Our SR latch is speed-independent for the given STG. Our OR gate is not foam set boundary reset out 32

56 Is our -Element Speed Independent? Environment asserts A+,B+,B- out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ B+ A+ B- A- out- A B? out A- B- 33

57 Is our -Element Speed Independent? Solution: remove (prohibit) some transitions out=0 A+ B+ B+ A+ out=0 out=0 out=0 B- A- out+ B+ A+ B- A- out- A B? out A- B- 34

58 Is our -Element Speed Independent? Solution: remove (prohibit) some transitions out=0 A+ B+ B+ A+ out=0 out=0 out=0 out+ out- A B? out B- A- A- B- 34

59 Threshold Gate (T-Gate) T-Gate is a generalization of OR and gates Gate output goes low when all inputs are low goes high when #threshold inputs are high rise threshold # inputs 35

60 Threshold Gate (T-Gate) T-Gate is a generalization of OR and gates Gate output goes low when all inputs are low goes high when #threshold inputs are high rise threshold # inputs 35

61 Threshold Gate (T-Gate) T-Gate is a generalization of OR and gates Gate output goes low when all inputs are low goes high when #threshold inputs are high rise threshold # inputs 35

62 Threshold Gate (T-Gate) T-Gate is a generalization of OR and gates Gate output goes low when all inputs are low goes high when #threshold inputs are high rise threshold # inputs 35

63 Threshold Gate (T-Gate) T-Gate is a generalization of OR and gates Gate output goes low when all inputs are low goes high when #threshold inputs are high rise threshold # inputs 35

64 Threshold Gate (T-Gate) T-Gate is a generalization 4 of OR and gates Gate output goes low when all inputs are low rise threshold 3 2 goes high when #threshold inputs are high # inputs 35

65 Threshold Gate (T-Gate) T-Gate is a generalization 4 of OR and gates Gate output goes low when all inputs are low rise threshold 3 2 goes high when #threshold inputs are high # inputs 35

66 Threshold Gate (T-Gate) T-Gate is a generalization 4 of OR and gates Gate output goes low when all inputs are low rise threshold 3 2 goes high when #threshold inputs are high # inputs 35

67 Threshold Gate (T-Gate) T-Gate is a generalization 4 of OR and gates Gate output goes low when all inputs are low rise threshold goes high when #threshold inputs are high # inputs 35

68 Threshold Gate (T-Gate) T-Gate is a generalization 4 of OR and gates Gate output goes low when all inputs are low rise threshold goes high when #threshold inputs are high # inputs 35

69 Threshold Gate (T-Gate) T-Gate is a generalization 4 of OR and gates Gate output goes low when all inputs are low rise threshold goes high when #threshold inputs are high # inputs 35

70 How can we compute with -Elements? Simplest approach: DIMS Delay Insensitive Minterm Synthesis Replace each wire with a pair of wires One wire goes high to signal a zero The other goes high to signal a one Both low means data not ready yet 36

71 DIMS Example: XOR gate

72 DIMS Example: XOR gate

73 DIMS Example: XOR gate

74 DIMS Example: XOR gate

75 DIMS Example: XOR gate

76 DIMS Example: XOR gate

77 DIMS Example: XOR gate

78 DIMS Example: XOR gate

79 DIMS Example: XOR gate

80 DIMS Example: XOR gate

81 DIMS Example: XOR gate

82 DIMS Example: XOR gate

83 DIMS Example: XOR gate

84 How can we communicate with -Elements? Simplest communication path is a FIFO First KLA Look to your left: this is your predecessor Look to your right: this is your successor Use ONLY ONE HAND (put the other one behind your back) You may TAKE a plate from your predecessor when your desk is empty You may take as long as you like to do so. You may not foist a plate upon your successor 50

85 How can we communicate with -Elements? Second KLA Look to your left: this is your predecessor Look to your right: this is your successor Start with your hand down When predecessor and successor are in different states, copy your predecessor s state 5

86 How can we communicate with -Elements? Simplest FIFO rule: When predecessor and successor are in different states, copy your predecessor s state out predecessor successor pred 0 succ 0 c 0 c 52

87 Micropipelines 53

88 Demo 54

89 altech MiniMIPS 250 "foo.dat" 200 MIPS Designed Actual results: 250% the performance of the best synchronous MIPS on the same fabrication process, 00% die yield. SPIE predicts >350% after fixing a single layout error (long poly wire) Performance scaled automatically with voltage and temperature changes over a wide range voltage 55

90 Epson Flexible Microprocessor The industry s first flexible 8-bit asynchronous microprosessor. 56

91 Fulcrum FM2224 0Gb/s 24-port full-crossbar 802.X switch Full 240Gb/s bandwidth, non-blocking 200ns solder-ball-to-solder-ball Power scales linearly with throughput QDI Design 57

92 ARM996HS (Handshake Solutions) 58