An Asynchronous High-Throughput Control Circuit For Proximity Communication Justin Schauer

Transcription

1 An Asynchronous High-Throughput Control Circuit For Proximity Communication VLSI Research Group Sun Microsystems Laboratories

2 To Discuss: Proximity communication The timing challenge Our asynchronous solution Our test chip Future work Questions 2/25

3 Proximity Communication Chip2 Chip1 Transmit Receive Receive Transmit Interconnect technology > Low power, high density Developed by our group at Sun Labs 3/25

4 The Timing Challenge Traditional interconnect challenges > Timing > Flow control > Power consumption New challenges > Amplifying small signals > Chip alignment > Variable performance 4/25

5 Chip Alignment Chip 1 Chip 2 Tx Rx Typical channel delay ~ 5 gate delays > Varies with chip alignment 5/25

6 The Timing Challenge Our Solution Asynchronous timing protocol Performance goal: > One data item every GasP cycle (6 gate delays) > Around 3 Giga tokens per second (Gtps) in 180 nm 6/25

7 Our Asynchronous Solution Uses GasP circuit family > Cycle time around 6 gate delays > One shared signal wire for request and acknowledge > Pulse signaling req/ack req/ack 3 gate delays Latching signal 6 gate delays 7/25

8 GasP: Challenges Proximity channel is unidirectional > GasP uses bidirectional state wires Chip-to-chip signal transitions are expensive > Pulse signaling requires two transitions per token Handshake requires two channel crossings plus overhead > Exceeds 6 gate delay GasP cycle time 8/25

9 GasP: Challenges Bidirectional GasP State Wires Use separate request and acknowledge wires at proximity channel req req/ack ack latch signal 9/25

10 GasP: Challenges Pulse Signaling Convert pulse to transition signaling req req/ack ack 10/25

11 GasP: Challenges Control Latency Multiple concurrent control paths Single datapath channel Three-way round-robin scheme > Sequences control > Determines total throughput 11/25

12 Round-robin Control Paths round-robin signal merged datapaths 12/25

13 Our Asynchronous Solution chip 1 Async Tx FIFOs Round-Robin Tx Control chip 2 Rx Control Async Rx FIFOs 13/25

14 Our Test Chip Fabricated to test asynchronous control scheme Funded by DARPA as part of Sun's HPCS initiative Taped out November 2004 in the 1.8V,180 nm MOSIS TSMC process Demonstrated timing over a capacitively coupled interface for the first time 14/25

15 Test Chip Features On-chip varactors to emulate proximity interface > Only one chip needed for testing Dummy loads to represent 72-bit datapath Asynchronous GasP sources and sinks for tokens Counters at the sources, sinks, and on the round-robin path 15/25

16 Token Sources Token Sinks Counter Taps Dummy Datapath Loads 16/25

17 The Proximity Channel Emulates an inter-chip channel on a single chip > 120 μm x 120 μm pad size > Nominally 2.5 μm chip separation Varactors emulate chip misalignment coupling cap Tx 200 f F parasitic Rx 40 f F 120 f F parasitic 17/25

18 On-chip Varactors 25 plates Emulates coupling caps from f F > Chip separation of 0 30 μm Independently programmable 18/25

19 Testing Schmoo Plot Capacitance (ff) Simulated chip separation (µm) VDD (V) /25

20 Performance Throughput (Giga tokens per second) Testing Throughput vs Capacitance VDD: V 1.8 V 2.1 V Coupling Capacitance (ff) /25

21 Testing Results Exemplified robustness of asynchronous design > Performs well (> 1 Gbps) from 1.2 to 2.1V and 17 f F up Met our performance goal > 3 Gtps at 42 f F Revealed that our counters are too slow 21/25

22 Our Test Chip Main experiment 22/25

23 Future Work Attach a real datapath Increase performance and decrease power consumption > Differential signaling > Different asynchronous circuit family 23/25

24 Thanks! DARPA for funding us (Contract #NBCH ) Co-authors: Jo Ebergen, Alex Chow, Bill Coates, David Hopkins The rest of the VLSI Research Group and our contractors 24/25

25 Questions?