A Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker

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1 A Prototype Amplifier-Discriminator Chip for the GLAST Silicon-Strip Tracker Robert P. Johnson Pavel Poplevin Hartmut Sadrozinski Ned Spencer Santa Cruz Institute for Particle Physics

2 The GLAST Project An orbiting gamma-ray pair conversion telescope for observation of photons above 10 MeV from astronomical sources. GLAST will view nearly half the sky at once, with excellent sensitivity to rapidly varying sources. GLAST will improve by one to two orders of magnitude on the sensitivity of the highly successful EGRET experiment operating since 1991 on the Compton Gamma Ray Observatory. A compact silicon-strip based tracker affords a very large field of view with low dead-time, excellent pattern-recognition capability and background rejection, and optimal angular resolution. Plastic scintillator veto counters work together with the tracker to provide a fast. Segmentation minimizes self-veto from the calorimeter back-splash. A highly segmented CsI calorimeter provides good energy resolution over a large dynamic range and aids in background rejection.

3 The GLAST Instrument Concept GLAST Conceptual conceptual Design design. of (The GLAST current Gamma Large Area Space Telescope baseline design is for a 5 5 array of 32-cm square towers, each with 16 x,y layers.) Complete GLAST Gamma Ray 60 cm 7 x 7 Array of Towers 175 cm Si Strip Detector Assembly of identical modules, each with a veto shield, a silicon-strip tracker, and a calorimeter. One Tower Module of GLAST 60 cm 24 cm 24 cm Scintillator Veto Electron Positron 8 x 8 Array CsI(Tl) Xtals Diode Readout Converter (.5 rl) Calorimeter (10 rl) 6 cm 6 cm 236 um pitch Preamps 10 Layers of.05 rad length converter each with xy silicon strips 2 Layers of XY silicon strips only Trigger and Computer Tray

4 Tracker Electronics Requirements Challenge: 1.3 million readout channels operating with high reliability in a space environment. Power less than 300 µw/channel, including amplifiers and digital readout. Low noise occupancy (<0.05%) and good threshold uniformity. Microsecond peaking time for the amplifiers. Self ing. Radiation hard to 10 krad with latch-up immunity. <1% dead-time at a 10 khz rate (must be able to acquire while reading out previous events). Sparse readout and formatting close to the front end. Sufficient redundancy to be immune to single-point failures.

5 Electronics Status 16-channel prototype produced on the HP 0.8µm process and tested. 32-channel prototype produced and 60 used in an extensive beam test last month ( analysis is in progress). Final 64-channel design with full digital readout capability is nearly ready for prototype production. Digital readout controller design is in progress. GLAST Silicon-Strip Dectectors Single sided 6.4 cm square wafers 400 µm thick. AC coupling; polysilicon resistors for biasing. 195 µm strip pitch; 50 µm strip width. 5 detectors ganged together in series, for a total strip capacitance of 38 pf.

6 Preamplifier Design Standard folded cascode amplifier with 2V bias for the front end, to save power. 25 µa bias current set by an external resistor. Slow differential amplifier stabilizes the bias point and provides a continuous reset. Input impedance 5 kω gives 200 ns time constant with GLAST 38 pf detector load. Open loop gain: 64 db at 0 Hz Power: 90 µw Preamplifier schematic.

7 Shaping Amplifier Design AC coupling from the preamplifier. Conventional cascode amplifier with capacitive feedback. Slow differential amplifier in the feedback provides the differentiation function and stabilizes the output bias point. (Ref.: I. Kipnis, LBNL) Open loop gain: 62 db at 0 Hz Voltage gain: 26 Peaking time: 1.3 µs Pulse shape: reset current source makes a tail that is more linear than exponential, except at the lowest pulse heights. Power: 35 µw Shaping Amplifier Schematic

8 Comparator Design Conventional two-stage comparator, with DC coupling from the shaper output. No current in the second stage in the quiescent state (with no input signals). Only 17µW of quiescent power. Comparator Schematic

9 Analog Signal Shapes 4 fc Top: preamp, shaper, and comparator outputs for a 4 fc input charge. Bottom: 1 fc input charge. In both cases, the shaper baseline and the threshold (90 mv) are shown by solid black horizontal lines. 1 fc

10 Measured Amplifier Performance Gain (shaper output): 125 mv/fc Peaking time: 1.3 µ s Power consumption, including bias circuitry: 150 µw/channel Noise: ENC= C electrons, with C in pf, measured by several methods, as shown here. RMS Noise (electrons) With Si Strip Detector Attached Average ENC=407 electrons Noise measured from threshold curves on 16 channels connected to detector strips with 7 pf capacitance Channel Number RMS Noise (electrons) ENC= C External Capacitors ENC (electrons) Noise measured from threshold curves on 10 channels External Capacitance (pf) Channel 14 Noise ENC= C External Capacitors Noise measured by probe and spectrum analyzer C (pf)

11 Threshold Matching Threshold matching from channel to channel across a given chip depends primarily on the transistor pairs in the shaper feedback. Most chips meet the desired upper limit of about 15 mv rms threshold variation (compared with the 32 mv rms noise level). Work is in progress to try to improve this figure further in the next prototypes. Number of Chips Threshold (electrons) RMS variation=325 electrons=6.5 mv Results from threshold scans on a single 16-channel prototype connected to a single detector Channel Number Results from threshold scans on channel chips, with no detectors attached RMS Offset (mv)

Digital Readout Design The 64-channel chip currently being designed has the following additional features: Calibration mask, to select any subset of channels to be pulsed.

12 Digital Readout Design The 64-channel chip currently being designed has the following additional features: Calibration mask, to select any subset of channels to be pulsed. 7 bit DACs for setting calibration and threshold levels. Separate masks for and. 8-deep FIFO event buffer. Dual redundant serial command decoders. Dual redundant output shift registers and outputs. Bypasses to avoid clocking out from empty chips. External communication via lowvoltage-swing differential signals. Simplified block diagram of a readout chip.

13 cmd clk trg ack cmd clk trg ack trg ack clock cmd cmd clock trg ack token token trg ack clock cmd cmd clock trg ack token token Digital Readout Design channel readout chips handle a single detector layer. Data can shift out left or right, or in both directions, with a readoutcontroller chip at each end of the chain. Trigger signals also move left or right, or in both directions. Either readout controller chip can reprogram the readout direction of any of the front-end readout chips, so a single dead chip can be bypassed without losing from any other chips. The readout controller chips pass down the tower in a tokencontrolled protocol. Controller Trigger Controller Trigger To the next layer FE FE FE FE FE FE To the Tower Controller Controller Trigger Trigger Controller Simplified block diagram of the readout of a GLAST tower, showing only 2 of 16 layers and only 3 of 25 readout chips on each layer.

14 Commands Clock Trigger Acknowledge Readout Controller Chip Control initialization, calibration, and readout of the front-end readout chips. Sparse readout build list of hitstrip addresses. Calculate the time-over-threshold of the prompt output. Build events and coordinate the readout with neighboring layers via a serial line and a token. External communication via lowvoltage-swing differential lines. Currently being designed for the HP 0.8 µm process using the CMOSX standard cells. Commands Clock Trigger Acknowledge Trigger Out TOT Counter FIFO for TOT Global Control Comand Decoding To Front End Chips Gate Hit Counter Event buffer 1 token Previous Layer Event buffer 2 I/O Control Simplified block diagram of the readout controller chip. Triggers from the Front-End Chips token Next Layer Data from Front End Chips

15 Conclusions The basic amplifier-discriminator requirements of the GLAST silicon-strip tracker have been met and demonstrated with prototypes. A month-long beam test with electrons and tagged-photons has just been completed. (See another poster in this session with preliminary results.) Design of a complete readout system meeting the GLAST flight requirements is in progress. A complete prototype GLAST tower, utilizing this readout system for the tracker, will be fabricated and tested during the next two years. The electronics design will continue to be improved (and must migrate away from the HP 0.8 µm process), leading up to a GLAST construction start projected for the year 2000.

ASIC Development for the GLAST Tracker

ASIC Development for the GLAST Tracker Robert P. Johnson Santa Cruz University of California at Santa Cruz GLAST Instrument Concept GLAST Tracker Electronics Requirements Analog Channel Preamplifier Shaper Comparator Performance Readout Architecture