Study of the ALICE Time of Flight Readout System - AFRO

Transcription

1 Study of the ALICE Time of Flight Readout System - AFRO Abstract The ALICE Time of Flight Detector system comprises about channels and covers an area of more than 100 m 2. The timing resolution has to be better than 150 ps. The readout system is based on a modular architecture. Detector cells are combined to modules of 2880 channels. A VHDL model of the readout system has been developed. Results of prototype electronics used in test beams are presented. INTRODUCTION The ALICE experiment at the Large Hadron Collider heavy ion program at CERN will include a large area Time of Flight (TOF) system, spanning over a hundred square meters with more than individual read-out channels. Up to charged particles are detected per unit of rapidity per event at midrapidity by this detector; particle identification of most of these particles is covered by the time of flight technique. The design of the detector is not fixed yet. However, the readout model is as flexible as to allow adaptations to modularity and data flow easily. In the present design it is planned to divide the ALICE Time of Flight Detector into φ segments and m long z-segments. As a result the maximum number of TOF modules is 72. Each module is 1.74 m long and 1.3 m wide. It is equipped by 2880 chamber cells (60 cells x 48 cells) [1]. One option for the implementation of the detector cell is a glass-rpc detector cell [2]. The cells are constituted by a pair of identical double-gap chambers, each consisting of an aluminium anode and cathode and a central resisistive plate at a floating potential. The different elements are assembled in a plastic box that provides electrical insulation and mechanical rigidity. This box has holes for wires connected to the metallic electrodes, for gas circulation and for insertion of spacers that define the gaps [3]. READOUT SYSTEM Timing measurements are performed using an 8 channel TDC (time to digital converter) chip which requires a 40 MHz reference clock signal. The chip is being developed by the CERN microelectronics group [5]. The TDC chip has multi hit capability and generates a time tag for each hit onto a parallel bus. It allows hit data to be stored in an internal buffer until the level1 (L1) trigger decision has been reached. A trigger feature supports readout of only those data which are located within a programmable time window before and after the triggered event. A. Kluge, M. Spegel CERN CH-1211 Geneva 23, Switzerland In order to perform slew correction the time over threshold method is used to measure the amplitude of the signal. The advantage of the scheme is that no parallel ADC channels are needed. The amplifier produces a fast leading edge (~1-2 ns) and a slow trailing edge (~100 ns). The pulse width of the amplifier is proportional to the input charge. A slew correction can be undertaken using the over threshold time pulse duration. The TDC chips allows to measure both the time of the leading and the trailing edge with the same TDC channel. The readout system is based on a modular architecture, detector cells are combined to modules of 2880 channels. Each of these modules can be read out and calibrated independently from each other. By distributing a reference signal, a timing relationship between the modules is established. The readout architecture is divided into three stages; the TDC chip and its TDC controller, the module controller and the detector data link interface. The TDC controller programs the TDC. Upon arrival of a L1 trigger accept, 5.5 µs after the corresponding event, the TDC controller transfers hit data from the internal TDC memories to the memory of the module controller. In case of L1 trigger reject, the corresponding data are either discarded in the TDC buffers or transferred to the module controller for monitoring purposes. The module controller prepares the data for transmission to the data acquisition system. In case a level2 (L2) trigger accept is issued, the module controller sends the corresponding data to the detector data link interface [4]. The maximum L2 trigger latency will not exceed 100 µs [7]. An detector data link interface acts as a data collector and as interface to the ALICE data acquisition system. Fig. 1 shows a block diagram of the full system. 12 TDC chips (= 96 channels) are connected to one TDC controller. 30 TDC controllers are supervised by one module controller. 4 module controllers are read out by one detector data link. On average, 10 4 minimum bias events per second are expected. The L1 trigger rate will not exceed 2800 Hz. The maximum L2 trigger rate will not exceed 660 Hz. A model of the readout system has been developed and an optimization process was performed using the hardware description language VHDL. It is planned to complete a FPGA based prototype of the TDC readout by the end of For the estimation of the system data rate a maximum average cell occupancy of 30 % has been assumed unless stated otherwise. This number is grossly overestimated [8]. TDC CONTROLLER The purpose of the TDC controller is to program the TDC and to read out and transfer data from the TDC to the module controller. One TDC controller processes 96 channels (12 TDC 1

2 signal and to prepare the transmission to the ALICE DAQ via the detector data link DDL. Data are stored in a RAM which is controlled by the module controller until a L2 trigger decision has been issued. The use of a dual port memory allows the start of the transfer to the detector data link interface before the data transmission from the TDCs has terminated. However, a L2 reject signal might have been issued even before the end of the transmission of the hit data from the TDC buffers to the module controller. In this case the transmission is aborted, the external module controller memory is cleared and a command to the TDC controllers is issued to clear the corresponding remaining data in the internal TDC memories. The average data rate at the input of the module controller can be calculated as follows: 2880 chamber cells * 30 % occupancy * 2800 khz maximum average L1 trigger rate * 64 bit = 2.4 MHz * 64 bit = 1.5 * 10 8 bit/s. Given modern FPGA technologies this requirement allows the implementation of the module controller by means of commercial FPGAs (XCS40, [6]). DETECTOR DATA LINK INTERFACE Fig. 1: ALICE time of flight detector data flow. chips). The TDC controller passes the L1 trigger decision to the TDC chips. The trigger feature of the TDC chips [5] allows read out of only those hit data from the internal buffer memories which have occurred within a programmable time window before and after the triggered event. The TDC controller passes the data flow directly to the module controller without additional stages of buffering. The TDC controller has been implemented using a commercial FPGA (XCS20, [6]) which works in a synchronous mode. Data may be transmitted at a 10 MHz rate. Although the overall occupancy will not exceed 30 %, the local occupancy used to design the system may be much higher. Considering the worst case of 100 % occupancy the resulting data flow from one TDC via the TDC controller to the module controller yields: 96 channels * 100 % occupancy * 2 32-bit words per hit * 2800 Hz = 1.7 * 10 7 bit/s or 5.4 * 10 5 data words per second. A 10 MHz data transmission rate between the TDC controllers and the module controller for all TDC controllers yields a maximum average transfer time of: 2880 cells * 30 % occupancy * 100 ns * 2 words = µs. That means that within µs after the L1 trigger accept signal all data have been transferred from the TDC controllers to the module controller where the maximum average L1 trigger rate is 2800 Hz [7] (or 357 µs time period). MODULE CONTROLLER The purpose of the module controller is to collect the hit data from the TDC buffers after the arrival of a L1 trigger accept The detector data link interface acts as data concentrator. It collects data from four module controllers and transfers it to the ALICE DAQ using the detector data links - DDL. 18 detector data link interfaces are employed. Each 4 module controllers are connected to a detector data link interface. PHYSICAL IMPLEMENTATION The physical implementation of the electronic system is divided into three building blocks: signal pickup cards, module reader cards, and detector data link (interface). SIGNAL PICKUP CARD Signal pickup cards contain shaping amplifiers, discriminators and TDCs for 16 channels. These cards are attached to the chamber PCB vertically. The chamber signals and the high voltage ground signals are connected to the bottom whilst the low voltage, clock signal, test signal input and digital data bus are connected to the top. Fig. 2: Physical implementation of signal pickup card. Fig. 2 illustrates the physical implementation of a signal pickup card. It contains four 4 channel analog chips and two 8 channel TDC chips. Fig. 3 illustrates the layout of the signal pickup cards on the chamber PCB. 6 TDCs, located on 3 signal pickup cards, are connected onto the same parallel data bus. 2

3 The signal pickup cards are able to send test pulses to all connected channels at the same time. This feature is used to test the time sensitive part of the electronic chain. The signal path from the chamber to the amplifier is kept as short as possible. The amplifiers are located directly on top of the chambers. MODULE READER The module reader unit has three module reader cards. Each module reader card contains 10 TDC controllers, the module controller, one clock receiver unit and one clock distribution unit. 12 TDCs are connected to a TDC controller. The module reader cards plug directly onto the digital data bus connectors of the signal pickup cards. The layout of all three cards is identical. All three module reader cards are plugged onto the same 32 bit wide module bus (see fig. 4). However, only one out of the three, the main module reader card, contains also the clock receiver unit, which distributes the clock to the three clock distribution circuits on the module readers, and a module controller FPGA. The main module reader card of a module plugs in the middle. This ensures a minimum propagation delay of the clock signal on the module. Fig. 4: Entire module including all readout electronics (180 x 16 channel signal pickup cards and three module reader cards). Module reader cards are connected to each other via the module data bus. test pulses are sent to test inputs of the analog amplifiers. The time difference between the time of transmission and the reception of the signal is measured permanently in order to monitor time drifts of the electronics. The TDC chips require a 40 MHz clock signal as a reference signal. Independent chamber modules must be referenced to each other in order to be able to compare time measurements of independent modules. Several options are possible. One option is to distribute a unique clock signal to each module where it is again distributed to each TDC chip. The timing reference between modules is established by the clock signal. Another possibility is to foresee independent clock generators on each module. The local clock generators must be calibrated on board by means of constant (cable) delays. Additionally the so called t 0 -signal, which is generated by a dedicated detector at the time an event occurs, is distributed to each module. In this case the timing reference is established by the t 0 -signal. Further studies will reveal the most practical solution. DETECTOR DATA LINK INTERFACE Fig. 3: One third of the module including 30 signal pickup cards. The TDC bus of each three signal pickup cards are connected together. The module reader card contains additionaltdc chips for calibration purposes. They are used to measure the time when For practical reasons the detector data link interface merges the data from four modules mounted on the same detector φ-segment. One DDL unit is foreseen for each detector φ-segment. Fig. 5 illustrates how 4 modules in a detector φ-segment are connected to each other and read out via a DDL unit. The maximum length of the data bus which connects the four modules does not exceed the length of three modules (< 6 m). The DDL interface is directly connected to the main module reader of the module closer to the readout side of ALICE. 3

4 Fig. 5: 4 modules are connected together via the DDL bus. Fig. 7: Picture of prototype signal pickup card. Fig. 6: Detector printed circuit board for eight detector cells; top: compontent side; bottom: detector side. PROTOTYPE A prototype of the frontend electronics and readout chain has been developed. The concept was validated during the test beam phases in 1999 using a 32 cell detector module constructed by the TOF collaboration [3]. An important issue for the design of the prototype electronics was to implement a system which is as close as possible to the ALICE implementation scheme [10]. Independent systems of high voltage distribution, low voltage distribution, and signal distribution are kept separated from each other. Also the number of chamber cells contained by a modular unit is low. However, for a large scale implementation this does not imply geometrically small units. A large mechanical structure can carry a high number of electrically separated modules. The physical implementation of the prototype system consists of three parts: the chamber printed circuit board holding chamber cells, and the high voltage circuitry [12]; the signal pickup cards, holding amplifiers, discriminators and edge detecting circuitry, and the time measurement system. The time measurement system for the test beam measurements was built up using standard LeCroy 2228A TDCs. The signal charge of each channel was measured using standard LeCroy 2249 ADC modules. It is planned to upgrade the prototype signal pickup cards with 4 channel prototype TDC chips [11] and read out the data using prototype module reader cards. The 4 x 8 individual detector cells are arranged in a chessboard pattern in two layers, providing a geometrical Fig. 8: Picture of prototype signal pickup card mounted on CERN chamber prototype. coverage of 97%. Mechanical support for the cells is provided by plastic spacers glued onto the detector PCB, which carries the high voltage circuitry, signal feed-throughs to the readout electronics, and closes the gas volume. The physical layout (fig. 6) of the high voltage distribution is carefully optimized to minimize crosstalk between neighboring channels across the electrical connections to a level of 1/2500. In particular the signal ground is separated from the HV ground for optimum picked-up noise and crosstalk rejection. All metallic parts on both sides of the PCB which are at HV potential are concentrated in the center of a 8-cell unit and covered by protective glue (Araldite) to avoid surface currents and discharges. The ground loop surrounding this HV area is only 6 x 12 cm wide and therefore rather insensitive to external high frequency noise. Four of the 8-cell units are connected to a common HV supply. The detector PCB with the array of 32 cells is mounted on a metallic box which closes the gas volume, carries gas connections and allows to fix the module to a moving table. All six faces of the box are covered by a thin PCB with a copper layer connected to the HV ground for electrical shielding, leaving 4

5 only small holes for the connectors to the readout electronics [3]. The signal pickup cards are attached to the detector PCB vertically. From the bottom the chamber signals and the high voltage ground signals connect to the signal pickup card. At the top side low voltage, the test input signal and the digital signals are connected. Fig. 7 shows a picture of the card. The amplifiers are plugged directly onto the signal pickup card. These amplifiers have been built by the Institute of Theoretical and Experimental Physics (ITEP), Moscow, using discrete components. The rise time of the output signal is less than 1.8 ns. The fall time of the output signal corresponds to the input charge and lies within the range of 15 to 50 ns. A commercial ECL discriminator (AD96685BR) is used to build up a fixed threshold discriminator scheme. A hysteresis of 14 mv is applied. The chip drives a trigger circuit for detection of positive and negative edges using components from the Motorola 10EL family. The positive edge of the discriminated amplifier signal gives the timing information. The negative edge of the signal gives the amplitude information. The location of the amplifiers has been chosen to provide a minimum signal path length from chamber to amplifier. Discriminators are located directly behind the amplifier maintaining a signal path length between amplifier and discriminator of only 1.5 cm. The low voltage supply of the card is distributed by external cables and not by the chamber printed circuit board. The card has its own voltage regulators. A test pulse signal can be sent to each amplifier. The analog output signal of the amplifier is buffered and can be measured independently from the digital output. Fig. 8 shows the 32 cell module with 2 signal pickup cards. Fig. 10: : Time resolution of 31 detector cells. One read-out channel was modified to serve a special purpose. unfavourable trailing pulse shape of the amplifier output. However, future versions incorporating an integrated amplifier adapted with a fast rise time for time measurement and pulse shape for amplitude measurement should correct this problem. CONCLUSION A readout concept and electronics implementation scheme for the ALICE time of flight detector have been presented complying to both the requirements of the detector and the ALICE data acquisition. A prototype electronic system has been proven to be effective in the test beam phase. Although signals were transmitted over 15 m we could prove that the electronics is capable of accurately measuring time to the ALICE specification. A system time resolution of 89 ps including the chamber cells was achieved. The overall system performance is very much dependent by the optimum modularity and careful location of the electronics. ACKNOWLEDMENTS The following colleagues contributed to this work with their invaluable advice and help: J.C. Berset, P. Fonte, F. Formenti, A. Martemianov. REFERENCE Fig. 9: : Time resolution of 31 electronics channels, measured by variable pulse height pulsing of all amplifiers. One read-out channel was modified to serve a special purpose. In the test setup the cable length from the ECL drivers on the signal pickup card to the TDC electronics was about 15 m. This layout was necessary for the test setup, nevertheless an electronics time resolution of the leading edge signal of 45 ps ([3], fig. 9) could be achieved using standard Lecroy 2228A TDCs. The total system noise level was < 1 fc. The 32 cell module yielded a uniform time resolution of 89 ps and an efficiency of 98% (fig. 10). Using the pulse width of the amplifier output signal as a measure for the input charge a slewing correction was performed without the use of the ADCs. A time resolution of 100 ps could be achieved. The degradation of 10 % compared to the measurement with the ADCs can be explained by the [1] C. Williams, private communication, June [2] P. Fonte et al., High resolution RPCs for large TOF systems, Preprint LIP 1/99, CERN EXT 99-06, ALICE Note INT (9 July 1999). [3] A. Akindinov et al., A glass-rpc time-of-flight array with 90 ps time resolution, in preparation. [4] G. Rubin, P.V. Vyvre, ALICE Detector Data Link, ALICE-DDL, Hardware Guide for Front-end Designers, ALICE/98-21, Internal Note/DAQ, 19 May [5] J. Christiansen and M. Mota, Proposal of a high resolution TDC chip, presentation given May 1999, J. Christiansen and M. Mota, A high resolution TDC to be used together with the TOF detector of ALICE, to be published as ALICE note, June M. Mota and J. Christiansen, A high resolution time interpolator based on a Delay Locked Loop and an R-C delay line, EP/MIC note, submitted to IEEE Journal of Solid State Circuits [6] XILINX, Spartan and SpartanXL FPGA Series (XCS00) v1.4, 1/99, 5

6 [7] O. V. Baillie, A modified trigger scheme for the ALICE trigger, March 9, 1999, talk given at ALICE week. ALICE, ITS Technical Design Report, LHCC O. V. Baillie et al., Data Acquisition, Control and Trigger: Common Report for the preparation of the ALICE Technical Design Reports, ALICE/98-23, Internal Note-DAQ, Trigger, June 23, 1998, Draft 1.2. [8] G. Paic, private communication, July [9] ALICE, Technical Proposal, CERN/LHCC 95-71, LHCC/P3, December 15, [10] A. Kluge, ALICE Time of Flight Readout - AFRO - Study of Requirements and Architecture, Document 1.2, August 23, 1999, ALICE note INT [11] M. Mota, A High Resolution Time to Digital Converter, Users Manual, Preliminary Draft 2.2, July 1, [12] M. Spegel, The Chamber PCB for a glass RPC time of flight array with 90 ps time resolution, 6