CMOS Detectors Ingeniously Simple!

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Doreen Farmer
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1 CMOS Detectors Ingeniously Simple! A.Schöning University Heidelberg B-Workshop Neckarzimmern

2 Detector System on Chip? 2

3 ATLAS Pixel Module 3

4 ATLAS Pixel Module MCC sensor FE-Chip FE-Chip 4

5 ATLAS Insertable B-Layer 5

6 ATLAS Pixel Module FE chip ~250 µm ~ e 6

7 Silicon Hybrid Detectors Features high signal and high noise complex compound bump bonding wire wrapping custom-made sensor lots of material (radiation lengths!) MCC sensor FE-Chip FE-Chip expensive (e.g. ATLAS II pixel HW: 16 mill.chf for ~5m2) scalability problem (e.g. Future experiments at FCC) miniaturization problem >108/m2 bump bonds? quality assurance problem 7

8 Silicon Detector cables sensor (silicon) CMOS (intelligence) (cooling) 8

9 Silicon Detector CMOS chip no composite no interconnects simplified design (ASIC design) profits from miniaturisation System on a chip 9

10 CMOS Features minimum pixel size feature size 5µm possible!!! low power (CMOS) low noise compared to hybrids compact VLSI design standard process cheap 10

11 Dopings n-type p-type electrons are majority charge carriers holes are majority charge carriers 11

12 What is CMOS? Complementary Metal Oxide Semiconductors n-channel MOSFET (NMOS) p-channel MOSFET (PMOS) MOSFET= metal oxide semiconductor field effect transistor Metal-Isolator-Semiconductor (MISFIT)- structure 12

13 What is CMOS? Complementary Metal Oxide Semiconductors n-channel MOSFET (NMOS) p-channel MOSFET (PMOS) MOSFET=metal oxide semiconductor field effect transistor n-channel (NMOS) 13

14 Advantages of CMOS fast switching characteristics used for CPUs no ohmic resistors needed low power easy to implement capacitors PMOS NMOS CMOS Inverter 14

15 Monolithic Active Pixel Sensors (MAPS) How to design a CMOS particle detector? particle monolithic = single process problem: low resistivity fast recombination small charge collection 15

16 The MAPS Principle D.Husson, NIMA 461 (2001) MIMOSA = Minimum Ionizing MOS Active pixel sensor ~15 μm 80 e- per μm p- space charge diffusion random walk recombination! time scale: τ ~ 100 ns p++ voltage ~3V 16

17 MIMOSA Schema pixel outside pixel Idea dates back to the 1980ies SSC reset source follower sensor readout control Sh. Parker, NIMA 275 (1989) 494 Challenge: separation of analog and control signals e.g. readout control should not affect signal Berst et al. (1999) 17

18 MIMOSA Pixel Layout 1-diode pixel 4-diode pixel transistors (intelligence) on sensor! 18

19 Rolling Shutter MAPS Readout Turchetta et al. NIMA 458 (2000) 677 analogue output discriminator 64 x 64 array 20 x 20 μm2 19

20 MIMOSA: Energy Distribution Berst et al., LEPSI x 3 pixel á 20 x 20 μm2 20

21 The charge collection efficiency D. Husson, NIMA 461 (2001) 511 Simulation 0.6 μm process ENC = ~ 20e- charge is spread over many pixels! ENC = equivalent noise charge 21

22 MAPS Charge Collection Time Berst et al. (2001) 5 µm 20 µm 22

23 Noise in CMOS Sensors usually dominant source is the so called Reset or Capacitive Noise: kt V RMS = C Q = C V RMS n RMS = ktc e typical signal over noise: S/N=20-50 Other sources: thermal noise S ν (w) = 4kTR shot noise flickering noise (1/f) 23

MAPS Applications MIMOSA originally proposed for

applications where time resolution is not an

24 MAPS Applications MIMOSA originally proposed for ILD vertex detector used in DESY Aconite telescope (EUDET) STAR vertex detector (350 mill. pixel) new ALICE vertex detector (~ 10 m2) applications where time resolution is not an serious issue STAR 0.16 m2 MAPS BILDER Aconite (DESY) ALICE 7 layers of MAPS 24

25 High Voltage MAPS Ivan Perić, NIMA 582 (2007) 876 Floating structure MOSFETS in well 100% fill factor high depletion at 50 V Low Voltage HV 25

HV-MAPS Pixel Design ~ 35-40 µm Fast circuit and thin sensor!

26 HV-MAPS Pixel Design ~ µm Fast circuit and thin sensor! DAC = digital to analog converter adjustment of threshold 26

27 HV-MAPS and Multiple Scattering HV-MAPS: allow for small pixel sizes can measure very low momentum tracks (thin sensor) limited hit resolution regime multiple scattering regime multiple scattering regime 27

28 Mu3e Experiment Search for µ+ e+ e+ e- (signal) Background: µ+ e+ v v p(e+) < 53 MeV µ+ ~ 1 muon decay / ns Fast and very thin detector required MuPix sensor 28

29 Mupix Chip 29

30 Mupix Chip Mupix7 prototype: ~ 3 x 3 mm2 ~1200 pixels pixel size ~ 80 x 100 µm2 Mupix7 features: Tune DACS for every pixel double stage amplifier (every pixel) zero suppression timestamp generation up to ~100 MHz 10 ns 1.2 GHz PLL integrated 1.2 (2.4) Gbit/s link about 40 pads needed (wire bond) System on Chip! 30

31 Mupix Readout Design Mupix7 prototype: ~ 3 x 3 mm2 ~1200 pixels pixel size ~ 80 x 100 µm2 Readout periphery 46 µm Comparator 7µm DAC and SRAM Coupling capacitor Address ROM TS DRAM CMOS digital part 31

32 MuPix Time Resolution DESY Testbeam with 5 GeV electrons includes time resolution of setup and sampling fastest monolithic pixel sensor! 32

33 MuPix Time Resolution signal height PSI Testbeam with 500 MeV protons timewalk correction possible 33

34 MuPix Pixel Efficiency Efficiency > 99.5% 34

35 MuPix Requirements 35

36 MuPix Tracker Construction Ultra-thin detector mock-up: sandwich of 25 µm Kapton 50/100 µm glass (instead of Si) 50 mu silicon wafer Sandwich X/X0 ~ 0.1% per layer 36

37 Summary CMOS detectors = System on Chip provides very thin sensors and small pixels used and/or considered for many upgrade projects HV-CMOS (HV-MAPS) solves timing and rate issues clearly the way to go in future! 37

X/X0 ~ 1-2% per layer ATLAS stereo strip module HV-MAPS Pixel only tracker?

38 Outlook HV-MAPS for LHC or FCC experiments? ATLAS II tracker (ITK) costs ~130 MCHF 14 tracking layers (10 strip + 4 pixel) X/X0 ~ 1-2% per layer ATLAS stereo strip module HV-MAPS Pixel only tracker? only 6-9 pixel layers required % per radiation length reduced material costs reduced assembly costs 3D tracking performance 38

39 BACKUP 39

40 Pulse Shape Measurement with ToT ToT= time over threshold 40

41 Noise Measurement with Threshold Scan 41

42 Silicon on Insulator (SOI) Concept CMOS buried oxide layer (insulator) depletion zone depletion ~50 um signal ~ 3000e noise ~ 30e higher radiation tolerance with n-well and p-well T.Hemperek et al. (Bonn) 42

43 Austria Microsystems (AMS) High-Voltage CMOS technology H18 process 0.18 um available since March V, 5V, 20V and 50V devices on a single chip without any process modifications 43

44 Mu3e Baseline Design Long cylinder! not to scale ~180 cm ~15 cm B = 1 Tesla 44

The High-Voltage Monolithic Active Pixel Sensor for the Mu3e Experiment

The High-Voltage Monolithic Active Pixel Sensor for the Mu3e Experiment Shruti Shrestha On Behalf of the Mu3e Collaboration International Conference on Technology and Instrumentation in Particle Physics