Meeting with STM HV-CMOS

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Scarlett Reeves
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1 Meeting with STM HV-CMOS!! Giovanni Darbo INFN- Genova o Credits: Most of the material in these slides come from presenta<ons of: Ivan Peric 9 th Trento Workshop on Advanced Silicon Detectors Genova, Feb 2014 Malte Backhaus 9 th Trento Workshop on Advanced Silicon Detectors Genova, Feb 2014!!! Agrate, 4 March 2014

2 HV- CMOS The Original Idea (Monolithic Pixel) Ideas: Use the standard (HV- )CMOS technologies to implement par<cle detectors Use a high voltage to deplete the sensor volume charge collec<on by drix Original Implementa<on: CMOS electronics inside the deep n- well- collec<ng electrode Smart diode Ref.: I. Peric, Nucl. Instr. And Meth. A 582 (2007) PMOS NMOS Shallow n- well Deep n- well Shallow p- well n- well ~60 V P- Substrate Agrate, 4 March

3 Advantages of Monolithic Pixels Cost: Use of high- volume standard IC technologies to implement par<cle detectors Avoid the high- density bump- bonding (this is a cost and a bo^leneck) Simplifica<on: Skip some of the produc<on steps Extend the use of wafer- probe test facili<es Time: The detector can be built in less <me (no or small industrial produc<on bo^lenecks) Performance: Smaller pixel (i.e. be^er space resolu<on) possible Thinner detectors (important not to degrade the informa<on for the detectors following the tracker). Agrate, 4 March

4 HV- CMOS The Original Idea (limita=ons) Limita<ons: The standard substrates are rela<vely low resis<ve (~20 Ωcm) The depleted region is up to ~15 µm thick MIP signals are rela<vely weak ~1800 e The collec<on electrode is, at the same <me, the PMOS bulk there is a strong capaci<ve crosstalk from PMOS transistors to the detector input. General drawback of monolithic sensors: Complex in- pixel electronics leads to increased detector capacitance (if everything in the same n- well) or to decreased electrode- /pixel- size ra<o (if separated n- well in the same pixel), PMOS NMOS Shallow n- well Deep n- well Shallow p- well n- well ~60 V P- Substrate Agrate, 4 March

5 HV- CMOS The Hybrid Solu=on: CCPD Hybrid detector with a smart HV- CMOS sensor and capaci<ve signal transmission to the readout ASIC (capaci<ve coupled pixel sensor CCPD): Overcomes drawback of monolithic detector: CCPD has small pixel and high electrode- /pixel- size ra<o Size: 50 µm x 250 µm Readout pixel ATLAS FE- I4 TOT = sub pixel address digital outputs of three pixels are mul<plexed to one pixel readout cell HV- CMOS pixel contains an amplifier and a comparator Different logic 1 levels + Size: 33 µm x 125 µm Agrate, 4 March

6 CCPD Improvements: Triple Well Detector structure improvements: Isolated PMOS Eliminates PMOS to sensor crosstalk, allows more freedom when pixel electronics is designed NMOS PMOS NMOS PMOS 3.3V Improvement: Deep n- well Deep p- well Shallow n- well Agrate, 4 March

7 CCPD Improvements: Higher Ωcm Detector structure improvements: High resis<ve substrates Around 80 Ωcm looks op<mal These processes are available within AMS and Lfoundry AMS agrees to use substrates of up to 3000 Ωcm (350 nm process H35) Uniformly doped substrate 20 Ω cm Signal 1800e (50%- 50% drix- diffusion) ParWcle Uniformly doped substrate 80 Ω cm Signal: ~ 2700e- 4500e (eswmawon) ParWcle Primary signal 100% - Signal collecwon: drix Secondary signal ParWal signal collecwon: diffusion Signal loss: recombinawon Deep- n- well Depleted 12 µm 12 um Signal loss Primary signal 100% - Signal collecwon: drix Deep- n- well Depleted 24µm (@ equal bias voltage) Depleted 48µm (@ equal field, doubled bias voltage) DepleWon ResisWvity Agrate, 4 March

8 HV-CMOS Hybridization Ac<ve sensor HV- CMOS coupled to FE: Capaci<ve coupling through bump pads dielectric layer very thin (<5 µm). Bump- pads are 18 µm diameter Cheap process to be developed HV- CMOS need signal/power Engineered solu<on for module hybridiza<on: TSV? Fig.: Prototype HV2FEI4 in AMS 180 nm process (H18) The Wny HV2FEI4p1 prototype glued on the large FE- I4 FE-I4 HV2FEI mm columns 24rows Agrate, 4 March

HV2FEI4 Chip: Prototype Results The HV2FEI4 chip works coupled with FE- I4 Seen signal from sources Measured detector efficiency at tests- beam: 85-90% efficiency seen.

9 HV2FEI4 Chip: Prototype Results The HV2FEI4 chip works coupled with FE- I4 Seen signal from sources Measured detector efficiency at tests- beam: 85-90% efficiency seen. Must understand if is missing collected charge at the pixel edge or Wming / threshold tuning pixel row 0 Full FE-I4 Hit Map pixel row HVCMOS Hit Map pixel column pixel column 0 (a) Agrate, 4 March Figure 7.5: Occupancy maps of the HV2FEI4 glued to an FE-I4 readout chip obtained with electrons from 90 asr (b)

HV2FEI4 Chip: Timing Response One of the issues of the chip is the <ming response Not yet

improve 22000 20000 18000 16000 14000 12000 10000 8000 6000 4000 2000 Hit Timing Resolution

379 0 0 2 4 6 8 10 12 14 16 lvl1 45000 40000 35000 30000 25000 20000 15000 10000 5000 Hit

10 HV2FEI4 Chip: Timing Response One of the issues of the chip is the <ming response Not yet understood if it is a poor design (nmos amplifier and discriminator) Need to understand & improve Hit Timing Resolution 1bin=25ns sumtot_20_matchlvl1 Entries Mean RMS lvl Hit Timing Resolution 1bin=25ns sumtot_21_matchlvl1 Entries Mean RMS lvl1 Agrate, 4 March

11 HV2FEI4 Chip: Radiation Tolerance Chips have been irradiated and annealed up to 860 Mrad. The amplifier recovers up to 90% their original gain The adiation design uses circular Studies transistors to withstand Electronics radia<on damage! 100" 2 70 C annealing every 100 Mrad Rela,ve"Amplifier"Gain"(%)" 80" 60" 40" 20" C annealing Adjustment of settings Pixel"One" Pixel"Two" Pixel"Three" Pixel"Four" 0" 0" 200" 400" 600" 800" 1000" 1200" Dose"(Mrad)" Agrate, 4 March

12 ATLAS Upgrade Cost Sensors are 30% of total ATLAS%%PHASE%II%upgrade%(LS3) ATLAS Cost Time Profile Phase I use TDR CosWngs Phase- II uses LoI coswngs, and includes opwons it#will# happen [MCHF] it#might# happen [MCHF] 1 New#Inner#Detector LAr#upgrades Tiles#upgrades Muon#spectrometer#upgrades TDAQ#upgrades Infrastructure#items TOTAL CORE%PAYMENTS%[MCHF]% 70" 60" 50" 40" 30" 20" 10" 0" ATLAS"Phase5II" ATLAS"Phase5I" R&D pre- / - producwon 2012" 2013" 2014" 2015" 2016" 2017" 2018" 2019" 2020" 2021" 2022" YEAR% Comment: devoted to RD pre- produc<on produc<on Agrate, 4 March

13 ATLAS Technology Inventory AMS H35 Early prototypes done in this process. High breakdown voltages (> 100V) somewhat elevated power consumpwon AMS H18/IBM 7HV Currently the main development process: HV2FEI4 and other chips GF 130nm HV HV process by GlobalFoundries in even smaller feature size, used to implement the HV2FEI4_GF. Actual experimental breakdown voltage is ~30 V before irradiawon. TowerJazz 180 nm High Resis<vity Process Bonn teswng. Possibly a process for monolithic detectors IBM 130 nm with Triple Well (T3) Process aqracwve as it is the process of the FE- I4 readout chip, it is not an HV/HR process and therefore does not allow high bias voltages leading to rather low signal- to- noise values. TSMC 65 nm process Process selected for future FE- I5 chip. Probably not for CCPD Agrate, 4 March

14 Documentations Talks: Ivan Peric, HV- CMOS Overview, at 9 th Trento Workshop, Genova 26-28/02/2014 hqp://indico.cern.ch/event/273880/session/5/contribuwon/64/material/slides/1.pdf Malte Backhaus, RadiaWon- hard AcWve Pixel Sensors for HL- LHC Detector Upgrades based on HV- CMOS Technology, at 9 th Trento Workshop, Genova 26-28/02/2014: hqp://indico.cern.ch/event/273880/session/5/contribuwon/65/material/slides/0.pdf Papers I. Peric, A novel monolithic pixelated parwcle detector implemented in high- voltage cmos technology, Nucl. Instr. and Meth. in Phy. Res. A 582(2007) I. Peric, C. Kreidl, and P. Fischer. Hybrid pixel detector based on capaciwve chip to chip signal- transmission. Nucl. Instr. and Meth. in Phy. Res. A 617(2010) I. Peric. AcWve pixel sensors in high- voltage CMOS technologies for ATLAS. JINST 7(08):C08002, Agrate, 4 March

Conclusions For ATLAS applica<on we consider CCPD a good alterna<ve to passive silicon sensors we expect this to be cheaper, easier to build, thinner and with be^er space resolu<on.

15 Conclusions For ATLAS applica<on we consider CCPD a good alterna<ve to passive silicon sensors we expect this to be cheaper, easier to build, thinner and with be^er space resolu<on. Process needs few tens of volt breakdown, few ohm resistance (80 Ωcm looks somewhat op<mal), triple well makes easier CMOS design. Produc<on cost is O[10M ] for Pixel only (it may increase if the strip tracker also adopt this technology) 3 years R&D before produc<on Plan to prepare an EU program (under Horizon 2020) to cover part of the R&D effort (part covered by INFN). This should be a joint venture with industrial partners and may bring to produc<on if successful.! Agrate, 4 March

16 BACKUP SLIDES Agrate, 4 March

HV-CMOS Hybridization Ac<ve sensor HV- CMOS coupled to FE: Capaci<ve coupling through bump

) and well aligned (<few µm) Combine 3 pixels together to ﬁt one FE- I4 pixel (50 250μm2),

Large chips (>2x2 cm2) or Wafer- Wafer bonding Uniformity of the dielectric layer Cheap

hybridiza<on: TSV? Prototype HV2FEI4 AMS 180 nm process (H18) G.

17 HV-CMOS Hybridization Ac<ve sensor HV- CMOS coupled to FE: Capaci<ve coupling through bump pads Bump- pads are 18µm diameter Dielectric layer very thin (<5µm?) and well aligned (<few µm) Combine 3 pixels together to ﬁt one FE- I4 pixel (50 250μm2), with HV- CMOS pixels encoded by pulse height. CCPD: CapaciWvely coupled to pixel IC. Large chips (>2x2 cm2) or Wafer- Wafer bonding Uniformity of the dielectric layer Cheap process to be developed HV- CMOS need signal/power Engineered solu<on for module hybridiza<on: TSV? Prototype HV2FEI4 AMS 180 nm process (H18) G. Darbo INFN / Genova The Wny HV2FEI4p1 prototype glued on the large FE- I4 FE-I4 HV2FEI mm2. 60 columns 24rows ST-Microelectronics Agrate, 4 March

ATLAS R&D CMOS SENSOR FOR ITK

30th march 2017 FCPPL 2017 workshop - Beijing/China - P. Pangaud 1 ATLAS R&D CMOS SENSOR FOR ITK FCPPL 2017 Beijing, CHINA Patrick Pangaud CPPM pangaud@cppm.in2p3.fr 30 March 2017 On behalf of the ATLAS