Depleted CMOS Detectors

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1 Depleted CMOS Detectors D. Bortoletto University of Oxford D. Bortoletto IAS-HKUST 1

Outline Impossible to cover all activities ongoing on

Many technologies Many new ideas A lot of enthusiasm

aimed at HL-LHC (support also from AIDA2020) SOI CMOS

LFOUNDRY AMS 150 nm Global Foundry 130 nm ESPROS 150 nm

2 Outline Impossible to cover all activities ongoing on depleted CMOS in 20 min. Many technologies Many new ideas A lot of enthusiasm Clearly they are the future I will mainly cover activities aimed at HL-LHC (support also from AIDA2020) SOI CMOS Pixel XFAB 180 nm HR CMOS (sometime with HV adds on) LFOUNDRY AMS 150 nm Global Foundry 130 nm ESPROS 150 nm Toshiba 130 nm TowerJazz 180 nm IBM T3 130 nm STM 180 nm HV CMOS AMS 350 nm AMS 180 nm D. Bortoletto IAS-HKUST 2

3 D. Bortoletto IAS-HKUST 3

HYBRID PIXEL DETECTORS PROS: complex signal processing

Temporary storage of hits during L1 latency radiation

2 ) Good spatial resolution ~ 10 15 μm The ATLAS pixel

5-1.5% X 0 /layer in ATLAS/CMS ATLAS IBL pixel Layer

Support, cooling (-10 o C operation), services Complex

4 HYBRID PIXEL DETECTORS PROS: complex signal processing already in pixel cell possible Zero suppression Temporary storage of hits during L1 latency radiation hard to >10 15 n eq /cm 2 high rate capability (~MHz/mm 2 ) Good spatial resolution ~ μm The ATLAS pixel The CMS pixel CONS Relatively large material budget: % X 0 /layer in ATLAS/CMS ATLAS IBL pixel Layer Sensor + chip + flex kapton + passive components Support, cooling (-10 o C operation), services Complex module production Bump-bonding / flip-chip expensive D. Bortoletto IAS-HKUST 4

5 From hybrid to monolithic pixels Sensor FE Can we combine detection and readout in one ROC? Cheaper & better performance? Better resolution Easier module production No bump-bonding Lower material budget Bump bonding STAR MAPS m 2 Technology of choice for ILC D. Bortoletto IAS-HKUST 5

Monolithic Active Pixels (MAPS) Lightly doped p-type epitaxial layer (~14-20 μm, active volume) MIPs produce ~80 e-/h+ pairs per μm (~1000 e- ) Not fully depleted Charge collection mainly by

6 Monolithic Active Pixels (MAPS) Lightly doped p-type epitaxial layer (~14-20 μm, active volume) MIPs produce ~80 e-/h+ pairs per μm (~1000 e- ) Not fully depleted Charge collection mainly by diffusion (~100 ns) 100% fill-factor N-well implantation used for collecting electrode Only nmos transistors (in p-well) are possible in the pixel area Limited in-pixel electronics More complex electronics at the periphery of the sensing matrix Fabricated in commercial CMOS technologies (leading edge performance, low-cost) Ionizing Particle IPHC Strasbourg (PICSEL group)) Applications: STAR-detector (RHIC Brookhaven) and Eudet beam-telescope D. Bortoletto IAS-HKUST 8

MAPS in STAR Data taking since 2014 (Au-Au,

sector tubes (~ 200 μm thick) Topological

7 MAPS in STAR Data taking since 2014 (Au-Au, p-p, p-aucollisions) 356 M pixels in 2 layers ~0.16 m 2 Ladder with10 MAPS carbon fiber sector tubes (~ 200 μm thick) Topological reconstruction of charm hadrons such as D 0 which a lifetime 120 μm D. Bortoletto IAS-HKUST 9

INMAPS TowerJazz and Rutherford Appleton Laboratory Deep P-Well to shield the PMOS transistors from epi layer No charge loss occurs Full CMOS Smart pixels possible

substrate ALICE ITS, SEM picture of prototype chip Application in HEP: ALICE INMAPS on High Resistivity resistivity (> 1kΩ cm) p- type epi-layer 18-40 µm thick Moderate

8 INMAPS TowerJazz and Rutherford Appleton Laboratory Deep P-Well to shield the PMOS transistors from epi layer No charge loss occurs Full CMOS Smart pixels possible Disadvantages Not a standard process limited number of producers epitaxial layer ~ 24 µm standard low res. substrate ALICE ITS, SEM picture of prototype chip Application in HEP: ALICE INMAPS on High Resistivity resistivity (> 1kΩ cm) p- type epi-layer µm thick Moderate reverse bias to increase depletion zone around NWELL diode some charge collection by drift Small n-well collecting diodes small Ci n Radiation tolerance (TID) to 700 krad (= 1/1500 of HL-LHC-pp) R. Turchetta, W. Snoeys D. Bortoletto IAS-HKUST 10

15 mm 30 mm ALPIDE Pixel size: 29 x 27 µm 2 with low power front-end ~40 nw/pixel Extensive tests before and after irradiation 0.5 x 10 6 pixels Detection Resolution Efficiency (mm) 7 1 0.995 6 0.

9 15 mm 30 mm ALPIDE Pixel size: 29 x 27 µm 2 with low power front-end ~40 nw/pixel Extensive tests before and after irradiation 0.5 x 10 6 pixels Detection Resolution Efficiency (mm) µm epitaxial layer, -6V back bias Resolution Efficiency Fake-Hit Cluster Size Rate Non-irradiated MeV n eq /cm Fake-Hit Cluster Rate/Pixel/Event Size (Pixel) sensitivity limit % pixels masked Threshold Current I THR (pa) Efficiency > 99.5% and fake hit rate << 10-5 over wide threshold range Excellent performance also D. after Bortoletto irradiation IAS-HKUST to (1MeV n eq )/cm

HL-LHC Specifications Outer layers Occupancy 1-2 MHz/mm 2 NIEL ~ 10 15 n eq /cm 2 TID ~ 50 Mrad Larger area O(10m 2 )

10 HL-LHC Specifications Outer layers Occupancy 1-2 MHz/mm 2 NIEL ~ n eq /cm 2 TID ~ 50 Mrad Larger area O(10m 2 ) Inner layers Occupancy MHz/mm 2 NIEL ~ neq/cm 2 TID ~ 1 Grad Smaller area O(1 m 2 ) D. Bortoletto IAS-HKUST 13

Depleted CMOS HL-LHC The rate/radiation environment of the HL-LHC is challenging but CMOS could: Lower cost large area detectors using commercial fabs More pixel layers in trackers A reduction of

11 Depleted CMOS HL-LHC The rate/radiation environment of the HL-LHC is challenging but CMOS could: Lower cost large area detectors using commercial fabs More pixel layers in trackers A reduction of material and power R&D is ongoing with the goal of: Achieve a depletion depth of μm Fast charge collection (for < 25ns in-time collection) Reasonably large signal ~4000 e- d Small collection distance to avoid trapping and increase rad hardness ρv low resistivity & Low Voltage 10 Ω cm High resistivity & higher voltages 2 kω cm NW: 1V PW: 0V D. Bortoletto IAS-HKUST 14

12 Enabling technologies High Voltage High resisitivity Technology features Backside processing Special processing for automotive and power management application to allow the HV necessary to create a depletion layer in a well s pn-junction of o(10-15 μm). Hi/mid resistivity silicon wafers accepted/qualified by the foundry to facilitate the needed depletion layer Radiation hard processes with multiple wells. Foundry must accept some process/drc changes to optimize the design for HEP. Wafer thinning from backside and backside implant to fabricate a backside contact aner CMOS processing D. Bortoletto IAS-HKUST 15

13 Design choices toward DMAPS Electronics inside charge collection well Electronics outside collection well Charge signal Charge signal Electronics (full CMOS) Electronics (full CMOS) P+ p-well nw P+ n+ p-well nw n+ Deep n-well deep p-well - p-substrate - p-substrate Deep n and p wells Large collection node Large sensors capacitance sensor capacitance (DNW/PW junction!) X-talk, noise & speed (power) penalties Short drift path Full CMOS with additional deep-p implant Small collection node Smaller capacitance less power Long drift path D. Bortoletto IAS-HKUST 16

production offered by HV- CMOS foundries Concept could be used also for strip detector (HVstrip1,

14 Capacitive Coupled Pixel Detector (CCPD) Hybrid Pixels with Smart Diodes Preamplifier very close to the collection node large signal output Cheaper: Capacitive coupling could yield cost reduction Large scale production offered by HV- CMOS foundries Concept could be used also for strip detector (HVstrip1, CHESS, CHESS2) DMAPS chip FEI4 Ivan Peric proof-of-concept HV- AMS 0.35 μm (2006) D. Bortoletto IAS-HKUST 18

15 CCPD CCPD with sub-pixel address encoding CCPD with one-to-one pixels 50 μm x 250 μm S33 μm x 125 μm AMS H18: KIT, Geneve, Heidelberg, IFAE, Liverpool, Brookhaven, CERN, Tsukuba D. Bortoletto IAS-HKUST 19

HV-CMOS strip o Pseudo strips made up of pixels (~40 mm x 800 mm ) o Amplifiers and comparators could be

Faster construction o Less material in the tracker o Max reticle sizes are ~2x2 cm 2.

for CMOS Evaluation of Strip Sensors H 350 nm AMS, 20 Ωcm CHESS 2: full reticle size of 20 mm x 24 mm

16 HV-CMOS strip o Pseudo strips made up of pixels (~40 mm x 800 mm ) o Amplifiers and comparators could be on sensor but the rest of processing into a readout ASIC o Can yield : o 2D coordinates o Cost savings o Faster construction o Less material in the tracker o Max reticle sizes are ~2x2 cm 2. Therefore rows of 4-5 chips could be the basic units (yield performance is critical here) CHESS 1 - CHip for CMOS Evaluation of Strip Sensors H 350 nm AMS, 20 Ωcm CHESS 2: full reticle size of 20 mm x 24 mm AMS-H35 technology with different resistivity: 20, , , Ω -cm. (SLAC & UCSC) D. Bortoletto IAS-HKUST 20

CCPD sensor family (HV-AMS 180 nm) CCPDV1 and 2 Chip size:

4mm Pixel matrix: 60x24 (sub-pixels of 33 μm x 125μm)

Tune DAC 3 operation modes; Standalone, strip-like, and

containing only amplifier Matching the CLICPix65nm ASIC

17 CCPD sensor family (HV-AMS 180 nm) CCPDV1 and 2 Chip size: 2.2mm x 4.4mm Pixel matrix: 60x24 (sub-pixels of 33 μm x 125μm) Pixels contain charge sensitive amplifier, comparator and Tune DAC 3 operation modes; Standalone, strip-like, and pixel (with FEi4) CCPDv3 (shared with CLIC) 25x25μm pixels containing only amplifier Matching the CLICPix65nm ASIC CCPDv4 (AMS H18) With 4 types of pixels NewPixels with Separated electronic and electrode D. Bortoletto IAS-HKUST 22

CCPD-LF LFoundry 150 nm CMOS technology: 2kΩcm p-type bulk Bonn, CPPM (Marseille),

alternative 5 mm x 5 mm CCPD_LF (A/B) subm.

18 CCPD-LF LFoundry 150 nm CMOS technology: 2kΩcm p-type bulk Bonn, CPPM (Marseille), IRFU (Saclay) collaboration R&D includes passive CMOS sensors as a potential sensor alternative 5 mm x 5 mm CCPD_LF (A/B) subm. Sep 2014 fast R/O coupled to FE-I4 also stand-alone testable 33 x 125 μm 2 LF-CPIX Demonstrator subm. March 2016 fast R/O coupled to FE-I4 also stand alone testable 50 x 250 μm 2 pixels LF-Monopix01 subm. Aug LF_CPIX Demo + stand-alone fast R/O column drain type R/O variants D. Bortoletto IAS-HKUST 23

19 E-TCT results Reactor neutron: 2e14, 5e14, 1e15, 2e15, 5e15, 1e16n/cm 2 E-TCT Scan along the sensor depth C H A R G E 1E16 2E15 AMS H350 (20 Ω cm) Chip surface laser pulse injected into different regions of the pixel IR laser 1 mm absorp. length Beam size 10 µm Charge= time integral of induced current Charge collection width: Increases with fluence up to 2e15 n/cm 2 due to initial acceptor removal Decreases with fluences above 2e15 n/cm 2 but larger than before irradiation even at 1e16 n/cm 2 Bojan Hiti (Ljubljana) D. Bortoletto IAS-HKUST 24

E-TCT results Reactor neutrons, steps: 1e14, 5e14, 1e15, 2e15, 5e15, 8e15n/cm 2 E-TCT Scan along the sensor depth LF (2 KΩ cm) Chip surface laser pulse injected into different regions of the pixel IR

20 E-TCT results Reactor neutrons, steps: 1e14, 5e14, 1e15, 2e15, 5e15, 8e15n/cm 2 E-TCT Scan along the sensor depth LF (2 KΩ cm) Chip surface laser pulse injected into different regions of the pixel IR laser 1 mm absorp. length Beamsize 10 µm charge= time integral of induced current A Charge Collection width of 35 µm (2,800 e-) can be achieved after 8e15 n/cm 2 Bojan Hiti (Ljubljana) D. Bortoletto IAS-HKUST 25

CCPDv4 2016 beam test after irradiation CERN SPS test beam, 180 GeV pions Two

chip DUT matrix 8 x 12 pixels (pitch of 100 µm x 125 µm) edge pixels excluded 1e15

21 CCPDv beam test after irradiation CERN SPS test beam, 180 GeV pions Two n-irradiated AMS CCPDv4 samples: 1e15 n/cm 2, 5e15 n/cm 2, glued to FEI4 readout chip DUT matrix 8 x 12 pixels (pitch of 100 µm x 125 µm) edge pixels excluded 1e15 n/cm 2 average efficiency 99.6 % 5e15 n/cm 2 average efficiency 92.9 % D. Bortoletto IAS-HKUST 26

) Time walk Fraction of in-time (25ns) hits Low threshold : 79% High threshold : 91% Passive

22 CCPD_LF prototypes Base line ENC=136e 55 Fe ENC=149e Signal spectra (sources and 3.2 GeV e- beam) 160μm depletion 110V bias Noise ~150 (100)e- for version A (B, low cap.) Time walk Fraction of in-time (25ns) hits Low threshold : 79% High threshold : 91% Passive sensors 20V 6.2 ke i.e. ~86 μm depl. depth DMAPS Test structures CCPD_A 10V CCPD_B 5V D. Bortoletto IAS-HKUST 27

23 CCPD_LF prototype CCPD_LF_vA irradiated with neutrons to 1e 15 n/cm 2 Spectrum of 55 Fe and 241 Am HV bias100 V (125 V) for irradiated (unirradiated) sample Monitor output of charge sensitive amplifier (CSA) in a single active pixel 55 Fe 55 Fe 241 Am n eq /cm 2 Unirradiated n eq /cm 2 Unirradiated D. Bortoletto IAS-HKUST 28

24 Tower Jazz 180nm Investigator Technology Deep P-well allows full CMOS in pixel Gate oxide 3 nm good for TID Epitaxial layer Thickness: μm High resistivity: 1 8 kω.cm Reverse substrate bias Small collection NW in p-type epi to minimize capacitance (2-5fF) Modified process to improve lateral depletion and in particular charge collection after irradiation Measurements on 25um EPI: 50x50um pixel size 20x20um pixel size D. Bortoletto IAS-HKUST 29

25 Tower Jazz 180nm Investigator Neutron fluences: 1e14, 1e15, 1e16 (ongoing) 90Sr spectrum Monitor output of CSA Clear signals observed after 1e15 irradiation with only a small reduction of amplitude. Initial test beam results indicate no efficiency loss on pixel boundaries after 1e15 n/cm 2. H. Pernegger, C. Riegelet al. D. Bortoletto IAS-HKUST 30

26 Monolithic DMAPS Many readout under consideration: Column-drain R/O logic (FE- I3 like) MU3E D. Bortoletto IAS-HKUST 31

27 Scaling The main issue is scaling How do we scale up from 0.25 mm 2 sensors (Industry) to 1 hectare (HL-LHC, ILC Calorimetry, FCC) and meet all the requirements? D. Bortoletto IAS-HKUST 34

28 Scaling The main issue is scaling How do we scale up from 0.25 mm 2 sensors (Industry) to 1 hectare (HL-LHC, ILC Calorimetry, FCC) and meet all the requirements? D. Bortoletto IAS-HKUST 35

29 Conclusion PROMISING RESULTS: ARE WE ON THE VERGE OF A DCMOS REVOLUTION? D. Bortoletto IAS-HKUST 36

30 D. Bortoletto IAS-HKUST 37

31 Available foundries D. Bortoletto IAS-HKUST 38

32 D. Bortoletto IAS-HKUST 39

33 Total Ionizing Dose AMS H180 irradiated to 60 MRad LFoundry after 50 Mrad(X-ray, 60 kev) 3 flavors of CSA Normal (L=0.9µm), Long (L=1.5µm) and Enclosed Layout Transistor Gain change about 20% for lower doses Noise Increase minimal for enclosed layout Gain Noise Largest Noise increase after few Mrad dose range D. Bortoletto IAS-HKUST 40

34 Passive CMOS C4 bumps: come with chip fabrication at low cost (saving x3) LFoundry 150 nm CMOS AC- Coupled Bias resistor DC-Coupled Punch through bias Bean test ELSA D. Bortoletto IAS-HKUST 41

35 HV-CMOS radiation hardness TJ Investigator (similar technology to ALICE) High resistivity: 1 8 kω cm Emphasis on small fillfactor and small capacitance (< 5fF ) AMS 180 nm ρ = 10 Ωcm 1 kωcm Capacitive coupled to FEI4 (glue bonding) LFoundry 150 nm 2kΩcm p-type bulk passive sensor CCPD_ A CCPD_ B 55 Fe FE-I4 telescope SpS data 2016 (π +, 180 GeV) CCPDv4 irradiated to n eq /cm 2 D. Bortoletto IAS-HKUST 42

36 HV-CMOS radiation hardness TJ Investigator (similar technology to ALICE) High resistivity: 1 8 kω cm Emphasis on small fillfactor and small capacitance (< 5fF ) AMS 180 nm LFoundry 150 nm PROMISING RESULTS ρ = 10 Ωcm 1 kωcm passive Capacitive coupled to ARE WE ON FEI4 THE sensor (glue bonding) VERGE OF A CCPD_ A CMOS REVOLUTION? CCPD_ B 2kΩcm p-type bulk 55 Fe FE-I4 telescope SpS data 2016 (π +, 180 GeV) CCPDv4 irradiated to n eq /cm 2 D. Bortoletto IAS-HKUST 43

Filter farm reconstructing and processing 10 8-10 9 tracks per second periphery CSA pixel TH CMP READOUT data Comparator and readout

37 MU3e MuPix7 Prototype (AMS 180) Main technological Challenges Large area O(1m 2 ) monolithic pixel detectors with X/X 0 = 0.1% per layer Novel helium gas cooling concept Thin scintillating fiber detector with 1mm thickness Timing resolution ps Filter farm reconstructing and processing tracks per second periphery CSA pixel TH CMP READOUT data Comparator and readout in the periphery: less digital crosstalk more space at periphery needed complex routing of (analog) signals D. Bortoletto IAS-HKUST Andre SchÖning44

SOI Monolithic Pixels Yasuo Arai Transistors does not work with Detector High Voltage (Back-Gate Effect) Circuit signal and sense node couples (Signal Cross Talk) Oxide trapped hole induced by

38 SOI Monolithic Pixels Yasuo Arai Transistors does not work with Detector High Voltage (Back-Gate Effect) Circuit signal and sense node couples (Signal Cross Talk) Oxide trapped hole induced by radiation will shift transistor threshold voltage. (Radiation Tolerance) Single SOI Detector Buried-Well shield back-gate potential Good for Integration-type sensor Relatively Low radiation applications D. Bortoletto IAS-HKUST 45

39 SOI Monolithic Pixels Yasuo Arai Transistors does not work with Detector High Voltage (Back-Gate Effect) Circuit signal and sense node couples (Signal Cross Talk) Oxide trapped hole induced by radiation will shift transistor threshold voltage. (Radiation Tolerance) Double SOI Detector SOI Photon-Imaging Array Sensor (SOPHIAS) Middle Si layer shields coupling for X-ray Free Electron Laser (XFEL) SACLA between sensor and circuit. It also compensate E-field generated by radiation trapped hole. Good for Complex function and Counting-type sensor. Can be used in High radiation environment. XRPIX5: Event Driven X-ray Astronomy Detector SOFIST: SOI sensor for Fine measurement of Space and Time at ILC D. Bortoletto IAS-HKUST 46

40 Double SOI In the SOI process, it is possible to merge NMOS & PMOS Active region and share contacts. With increasing Implantation dose of P lightly doped drain region 6 times higher than present value, the degradation is reduced from 80% to 20% at 112 kgy(si). SOI Photon-Imaging Array Sensor (SOPHIAS) for X-ray Free Electron Laser (XFEL) SACLA XRPIX5: Event Driven X-ray Astronomy Detector SOFIST: SOI sensor for Fine measurement of Space and Time at ILC D. Bortoletto IAS-HKUST 47

41 CMOS CMOS complementary metal oxide semiconductor transistor (a type of field effect transistor, F. Wanlass 1963) First MOSFET was realized in 1959 Dawon Kahng and Martin M. Atalla. Reza Mirhosseini D. Bortoletto IAS-HKUST 48 48

42 Full CMOS MAPS If PMOS transistors are introduced, signal loss can happen D. Bortoletto IAS-HKUST 49

43 Charge Profile versus depletion voltage AMS H350 (20 Ω cm) FL (2 KΩ cm) Measurements can be used to extract N eff Acceptor removal Radiation induced acceptor D. Bortoletto IAS-HKUST 50

44 AMS CHESS1 (20Ω cm) 90 Sr measurements Largest charge collection at 1-2e15n/cm 2 D. Bortoletto IAS-HKUST 51

45 CCPDv beam test Timing performance on par with IBL modules in the telescope D. Bortoletto IAS-HKUST 52

Towards Monolithic Pixel Detectors for ATLAS HL-LHC Upgrades

Towards Monolithic Pixel Detectors for ATLAS HL-LHC Upgrades Hans Krüger Bonn University FEE 2016 Meeting, Krakow Outline Comparison of Pixel Detector Technologies for HL-LHC upgrades (ATLAS) Design Challenges