PICSEL Group. Physics with Integrated Cmos Sensors and ELectron machines.
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- Elvin Preston
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1 PICSEL Group Physics with Integrated Cmos Sensors and ELectron machines
2 CMOS MAPS (Monolithic Active Pixel Sensors) for Particle Tracking: a short summary of 15 years R&D at Strasbourg 1. Pixel principle 2. Read out description 3. Chip validation process 3bis Process Details 4. Applications
3 Main evolution (done with AMS thechnology) Images/s *4 Data flow /3 Analog output sensor (mimosa5) 1 Million pixels 4 output at 10 Mhz Ti= 26 ms 40 frame/s 76 MB/s 17*17 mm Images/s *40 Data flow /4 Binary output sensor (mimosa23) (pixels + comparators) 410k pixels 4 output at 160 Mhz Ti = 640µs 1,56 kframes/s 20 MB/s 19,2*19,2 mm sparcify data sensor (mimosa28) (pixels+discri+ zero suppression) 890k pixels 2 output at 160 Mhz Ti = 185 µs 5,4 kframes/s ~7 MB/s (100 hit/frame +fake) 19.8*19.2 mm
4 1. Pixel principle 20µm
5 From the digital camera to the particule detection Starting of MAPS activity at Strasbourg: 1999 iphc MIMOSA (Minimum Ionising Particle MOS Active Pixel Sensor) 14-18/01/2008 Metal layers Polysilicon N+ N+ P+ N+ P-W ell N-W ell P-W ell Potential P-epitaxial barriers layer kt N sub (up V to ln to 20 q N epi m thick) P-substrate (~100s m thick) IPHC-DUT christine.hu@ires.in2p3.fr 7 Radiation Dielectric for insulation and passivation Charged particles 100% efficiency. R.T. The effective charge collection is achieved through the thermal diffusion mechanism, The device can be fabricated using a standard, cost-effective and easily available CMOS process, The charge generated by the impinging particle is collected by the n-well/pepi diode, created by the floating n-well implantation, The active volume is underneath the readout electronics allowing a 100% fill factor. Using a thin epitaxial layer (10 20 µm) for the detection of Minimum Ionising Particule (MIP). Industrial CMOS process for fabrication!
6 The CMOS sensor (Complementary Metal Oxide Semiconductor) Charge s collection diode Particule trajectory P doping High (p-well) Moderate (epitaxial layere) High (subtrat) Technology High develloping in the industrie Exploration of different process Key parameter Epitaxial layer ( 10µm et 10=>~1kΩ.cm) Grid size (0.35µm et 0.18 µm) Number of metallization (4-7 layer) Leakage current Etc. The R & D have to follow the technology evolution 20-40µm Electrons thermal diffusion Strong Points : Préampli. (1 per pixel) Free electron in the conduction band Potential in the diode region Radio-tolerance to ionizing and NIEL effect Fast integration time (temporal resolution) High granularity (spacial resolution) Integrated signal processing Low noise at room temperature Low Material budget (thinned to 50µm and no cooling)
7 (1) A particule (photon, proton, électron, ) cross throught the silicium of the integrated circuit (1) (4) The electronic signal generate, proportionnal at the electrons number collected, pass next in the preprocessing microcircuit (4) Basic element: (2) it ionise the active layer by ejecting the electrons of the atoms electronic cloud (2) (3) Sensible layer Active pixel substrat 20 µm (3) These electrons are catch by the collector Schematic of photodiodes and signal preprocessing microcircuit, this constitute a group of pixels Past Low resistivity ~10Ω.CM Present high resistivity ~1kΩ.CM Industrial availability of high resistivity substrate (epi) in a standard CMOS process Fast and more efficient charge collection should be radiation tolerant
8 The operation principle of MAPS +3.3V Reset +3.3V Output SiO 2 SiO 2 SiO 2 N++ N++ N+ P+ P- P+ From M. Deveaux IKF
9 Two Types of PIXEL Vdiode (Vclamp) Vdda Vdiode (Vclamp) Vdda Reset (or LineReset) plus Global Reset Pixel 3T Pixel -Self Bias Pixel Array Periphery Gnd Select (or LineSelect) Gnd Select (or LineSelect) Iref Out (or ColumnOut) Iref Out (or ColumnOut) Gnd Gnd
10 3T pixel
11 Self Bias diode DC level stabilization RESET transistor replaced by a forward-biased diode, equivalent of a ~TeraOhm resistor for a ~fa (typical) leakage current Typical RC constant: tens of ms (even after irradiation)
12 2a. Analog read-out description
13 The simplest readout electronics: diode + 3 transistors/pixel 1. Reset in order to inverse bias 2. Continuous serial addressing and readout (digitisation) of all pixels 3. Keeping two successive frames in external circular buffer 4. Following reset when needed (removing integrated dark current) 5. After trigger (or in a real time)), simple data processing in order to recognise hits Fast ADC 12 bits Buffer : 512 words/channel F0 256 kwords F1 256 kwords trigger!
14 Data processing: (Digital) Correlated Double Sampling ( - ) Useful signal on top of Fixed Pattern DC level Fixed Pattern dispersion: ~100 mv Typical signal amplitude: ~1mV frame 1) (frame2 - frame1) subtraction frame2) ( - ) frame2 frame1) Pedestal (dark current) subtraction Hit candidates!
15 2b. Digital read-out description
16 a binary readout Clamping based CDS in pixel On-chip FPN suppression On-chip discrimination
17 a binary readout Offset compensated comparator at the end of each column Comparator threshold voltage scan for ALL pixels (of one type) - Output noise: 0.9 mv (ENC = 15 electrons) - Pixel-to-pixel FPN: 0.45 mv 17
18 Discriminator
19 2c. Sparcify read-out description
20 Zero suppression logic (suze) In order to optimize the data bandwith (On mimosa26 and Ultimate sensor) discriminators SDS Mux 15x6 to 9 Memory storage 160 MHz SuZe LVDS The SuZe logic is split on three blosks: Suze part 1) The Sparse Data Scan (SDS) => Hit detection per line and data encoding, until 6 states of consecutive pixels (1 to 4 pixels ) per block of 64 columns 2) The Multiplexing Logic (Mux) giving up to 9 states. 3) Two Memory blocks to store the states of the full frame, switching to avoid dead time (during one acquire states of event N the second transfer the information of frame N-1)
21 Zero suppression logic (suze02) Information by windows (On FSBB sensor) Representation of hit windows in a matrix of pixels The hit window format: column address of the first hit pixel (upper left of the window), followed by 20 bits encoding the number of contiguous pixels in the window delivering a signal above threshold Mhit windows by S line can be processed. This limit was derived from a statistical study based on the occupancy expected in the pixel array
22 Rolling shutter, column parallel processing: only processed pixel row dissipate power!
23 3. Different step for the validation of a sensor
24 * Probe test on silicium wafer Wafer 6-8 inchs MAPS Probe Station Wafer map Good chip Bad chip Some operational test are done to evaluate the yield of each wafer. To evaluate the consumption (short circuit), the configuration response (if slow control), its digital part (clock and marker output) and the number of dead pixels (light response)
25 Photon detection * Laboratory calibrations MAPS & Source Fe55 Source On-Line Monitoring Photons from 55 Fe source MAPS detector Sensor s signal is link to the charge deposit (number of electron-ions pair created) The output signal is digitize by an external imager board (12 bits) We want to know the output conversion factor to have the correspondence of the number of electron collected. Ionization (separation of an electron-ion pair) = 3.6 ev Source of 55 Fe Radioactive source which emit X-ray ( ) at 5.9 kev (1640 e/h pair) & 6.49 kev Energy deposit: The energy of X-ray are totally absorb by the sensor Sensor Evaluation Noise (& homogeneity) and pedestal dispersion CCE (Charge Collection efficiency) Pixel gain X-Ray Photons Hits
26 Calibration of the conversion gain - with soft X-rays Emission spectra of a low energy X-ray source e.g. iron 55 Fe emitting 5.9 kev photons. very high detection efficiency even for thin detection volumes, constant number of charge carriers about 1640 e/h pairs per one 5.9 kev photon Charge collection Peak The warmest colour represents the lowest potential in the device Calibration Peak 5.9keV 6.49keV
27 Charge Collection Efficiency (CCE) Seed : 37% cluster 2*2 : 80% Cluster 5*5 : 100%
28 * Detector Tracking Performances Validation with MIPS on particle beam For silicon The particule deposit 80 e/µm Electrons, pions or others charged particles
29 scintillator ~ 15 cm scintillator trigger Acquisition and monitoring PC Analysis offline PC 8 reference detectors (strips, X-Y orientation, 50 µm pitch) Or 4 planes of MAPS 2 coincidence scintillators (~1cm²) Analyze : Alignment, cluster reconstruction, hits separation Efficiency Noise and hot pixels study Signal/noise Spatial Resolution Influence of temperature, irradiation, incidence s angle,. Epitaxy study, uniformity
30 X1 strips Y1 X2 strips Y2 X3 strips Y3 X4 strips Y4 Online Monitoring CDS array 0_0 Strip Telescope cluster from an electron track in the MAPS detector.
31 Multiple scattering effects Real path L/2 x tan = 13.6 MeV x z (x/x 0 ) [ ln(x/x 0 ) ] (.c.p) Multiple scattering : e - (6 GeV) > > ± (120 GeV) p = 3 or 5 GeV/c ~ 1 z = charge number x = Si thickness ~ 500 μm (Mi9) + additional material: 500 μm? X 0 = 9.36 cm (Si) ~ 0.39 mrad ~ 0.23 mrad ms ms ~ L/4 x tan ~ 15 μm ms ~ L/4 x tan ~ 10 μm L ~ 160 mm Reconstructed track + cut on 2 of the track fit bias (<2) Impact Parameter Resolution Without Multiple Scattering With Multiple Scattering 2 I 2 1 ( r r1 r 2 1 ) P t X 0 So we want: -small r 1, large r 2 X r P t X 0 r P tz 2 -small 1, 2
32 3Bis. Details Bonding Thining irradiation
33 Bonding techniques Wedge bonding Ball studs bumps
34 Thinning Process (until 50 µm)
35 Back thinning to 20 µm
36 Radiation hardness of MAPS To be measured and improved: Radiation hardness against Ionising radiation: Energy deposited into the electron cloud May ionise atoms and destroy molecules Caused by charged particles and photons Non-ionising radiation: Energy deposited into the crystal lattice Atoms get displaced Caused by heavy (fast leptons, hadrons) charged and neutral particles Farnan I, HM Cho, WJ Weber, "Quantification of Actinide α-radiation Damage in Minerals and Ceramics." Nature 445(7124): From M. Deveaux IKF
37 Radiation tolerance against ionising radiation +3.3V Reset +3.3V Output SiO 2 N++ N++ Positive Charge SiO 2 N+ P+ P- P+ From M. Deveaux IKF
38 How to improve radiation tolerance +3.3V Reset Output SiO 2 N++ N++ Positive Charge SiO 2 N+ P+ From M. Deveaux IKF
39 Improvement of radiation tolerance +3.3V Output +3.3V GND SiO GND 2 SiO 2 SiO 2 N+ SiO 2 P++ P++ N++ P++ P++ guard ring cuts conduction paths From M. Deveaux IKF
40 How 1000 to improve radiation hardness MIMOSA-2 before and after 400kRad Entries in Histogram Entries Charge Collected in 4 Pixels [ADC] Before After Irradiation MIMOSA-11 before irradiation after 1 MRad Charge collected in four pixels [ADC] From M. Deveaux IKF
41 Tolerance against non-ionising radiation +3.3V Output +3.3V GND SiO GND 2 SiO 2 SiO 2 N+ SiO 2 P++ P++ N++ P++ Bulk damage From M. Deveaux IKF
42 Tolerance against non-ionising radiation +3.3V Output +3.3V GND SiO GND 2 SiO 2 SiO 2 N+ SiO 2 P++ P++ N++ P++ From M. Deveaux IKF
43 What means n eq /cm²? My current understanding Ljubljana ~1.8e13n ~0.9e13n ~0.9e13n 1 1,1 Damage factor [n eq /cm²] 0,1 0,01 1E-3 1E-4 75% 25% 1E Neutron kinetic energy [MeV] From M. Deveaux IKF
44 What means n eq /cm²? My current understanding Munich ~0.03e13 ~0.97e13 Damage factor [n eq /cm²] 1 0,1 0,01 1E-3 1E-4 3% NIEL of both sources should be equal. 97% But Ljubljana applies four times more neutrons. Mismatch could be caused by overlooked effect of slow neutrons. Neutron capture in boron doping? 1,0 1E Neutron kinetic energy [MeV] From M. Deveaux IKF
45 4. Applications of Cmos sensor 4a integration study 4b Experiments
46 SERVIETTE: use of UTCP by IMEC Stands for : ULTRA THIN FILM CHIP PACKAGING In short : Result : Off-the-shelf die Thinned down to ± µm Packaged between two polyimide foils Metallisation : fan-out Circuit contact through vias Flexible package Thin : µm Embeddable in commercial flexible PCB Chip thinning Polyimide on rigid carrier with release layer (KCl) Dispense/spin of BCB Placement (face up) of IC Photo definable polyimide spinning (20µm)) Opening vias using lithography Cleaning of contact pads Metallization: TiW (50nm) + Cu(1µm) Electroplating : Cu (5µm) Lithography to pattern metal Encapsulation polyimide spinning Release from carrier Polyimide 2 Polyimide 1 60 m
47 PLUME concept: double-sided ladder (ILC compatible) - 2x6 Mimosa26 sensors - Standard flex PCB: kapton + Cu (two layers) - SiC foam for spacer between layers
48 CERNWIET: standard PCB process for chip embedding in plastic foils (R. de Oliveira, CERN) Gluing between two kapton foils Single module: intermediate tests Opening vias using lithography Metallization: Al (5-10 µm) Lithography to pattern metal Complete ladder assembling, laser cut along sensor edges Gluing of another kapton foil for deposition of second metal layer
49 On going work and future plans: use of Vertical Integration Process (3D Electronics) Sensor comprised of several active silicon layers: sensor, analog processing, digital processing, memory, optoelectronics layer Total thickness of this stack is still ~50 µm! Bonding pads 3-tiers, heterogeneous CMOS, ultra-thin and edgeless MAPS 20 µm - Possible decrease of power per pixel (by order of magnitude): - Elimination of some hot spots
50 Future techniques: stitching ( one die per wafer ) Maximum length of monolithic ladder (8 wafer): cm
51 512x x512 Discriminators Memory 2 SUZE Memory 1 512x x512 Discriminators SUZE Memory 1 Memory 2 512x x x x x x x x512 Discriminators Discriminators Discriminators Discriminators SUZE SUZE SUZE SUZE Memory 1 Memory 2 Memory 1 Memory 2 Memory 1 Memory 2 Memory 1 Memory 2 512x x512 Discriminators SUZE Memory 1 Memory 2 512x x x x x x x x512 Discriminators SUZE Discriminators SUZE Discriminators SUZE Discriminators SUZE Memory 2 Memory 1 Memory 2 Memory 1 Memory 2 Memory 1 Memory 2 Memory 1 512x x512 Discriminators SUZE Memory 2 Memory 1 ~1 cm 512x x512 Discriminators Discriminators SUZE SUZE MUX Memory 1 Memory 2 MUX Memory 1Memory 2 Serial read out For Alice (mistral) Reticule mask Discriminators SUZE Memory 1 Memory 2 512x512 Discriminators SUZE Memory 1 Memory 2 512x512 Discriminators SUZE MUX Memory 1Memory 2 With tower technology For AIDA (SALAT) ~1 cm
52 4b. Applications of MAPS CMOS sensors in physics experiments Generic beam telescope internationale tests infrastructure x y z EUDET (EU FP6) AIDA (EU FP7) Vertex detectors subatomic physics experiments STAR (RHIC, Brookhaven) And also a possibility for vertex detector for ALICE and SuperB electromagnetic calorimeter (FoCal) for ALICE/LHC CBM (SIS, Darmstadt) ILC (?)
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