Chapter 4 Vertex. Qun Ouyang. Nov.10 th, 2017Beijing. CEPC detector CDR mini-review

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1 Chapter 4 Vertex Qun Ouyang Nov.10 th, 2017Beijing Nov.10 h, 2017 CEPC detector CDR mini-review CEPC detector CDR mini-review

2 Contents: 4 Vertex Detector 4.1 Performance Requirements and Detector Challenges 4.2 Baseline Design 4.3 Detector Performance Studies 4.4 Beam-Induced Background in the Vertex Detector 4.5 Sensor Technology Options 4.6 Mechanics and Integration 4.7 Critical R&D 4.8 Summary Nov.10 h, 2017 CEPC detector CDR mini-review 2

3 Detector Requirements impact parameter resolution 10 σ 5 µ m r φ = 3 2 p( GeV )sin ( θ ) Detector system requirements: σ SP near the IP: <3 µm material budget: 0.15%X 0 /layer first layer located at a radius: ~1.6 cm pixel occupancy: 1 % ~16μm pixel pitch power consumption < 50mW/cm 2, if air cooling used ~μs level readout Target: fine pitch, low power, fast pixel sensor + light structure Nov.10 h, 2017 CEPC detector CDR mini-review 3

4 Baseline Detector Layout VXD: ILD like layout 3 layers of double-sided pixels σ SP =2.8µm, inner most layer Polar angle θ~15 degrees VXD parameters VXD SIT FTD R (mm) z (mm) cos θ σ sp (µm) Readout time (µs) Layer Layer Layer Layer Layer Layer Nov.10 h, 2017 CEPC detector CDR mini-review 4

5 Performance Studies Baseline Material budget Nov.10 h, 2017 CEPC detector CDR mini-review 5

6 Performance Studies Single point resolution Distance to IP Nov.10 h, 2017 CEPC detector CDR mini-review 6

7 Radiation level -TID ~2.5 MRad/ year -NIEL ~ MeV n eq / (cm 2 year) (safety factor: 10) Beam-Induced Backgrounds (to be updated) Hit density ~2.5 hit cm -2 BX -1 detector occupancy: <1% by estimating tolerable hit density, with a safety factor of 10 included Nov.10 h, 2017 CEPC detector CDR mini-review 7

CMOS Pixel Sensor R&D Activities Sensor design & TCAD simulation Different

optimization and radiation tolerance study sensing node AC-coupled to increase

(in-pixel discriminator) Tow different readout schemes: rolling shutter &

8 CMOS Pixel Sensor R&D Activities Sensor design & TCAD simulation Different sensor diode geometries, epitaxial-layer properties and radiation damage First submission in Nov Exploratory prototype, analog pixel, rolling shutter readout mode Sensor optimization and radiation tolerance study sensing node AC-coupled to increase biased voltage Second submission in May 2017 Tow prototypes with digital pixels (in-pixel discriminator) Tow different readout schemes: rolling shutter & asynchronous Design goals Spatial resolution 5 µm Integration time < 10 µs Power consumption < 80mW/cm 2 Nov.10 h, 2017 CEPC detector CDR mini-review 8

9 First submission (CPV1) in June *16 μm with in-pixel-discrimination Double-SOI process for shielding and radiation enhancement Second submission (CPV2) in June 2016 In-pixel CDS stage inserted To improve RTC and FPN noise To replace the charge injection threshold CPV2 performance SOI Pixel Sensor R&D Activities Thinned down to 75um thick Temporal noise ~6e - Threshold dispersion (FPN) ~114e - Single point resolution measurement under infrared laser beam Nov.10 h, 2017 CEPC detector CDR mini-review 9

10 Future R&D Pixel pitch shrinkage Novel readout scheme Radiation hardness Light structure Nov.10 h, 2017 CEPC detector CDR mini-review 10

11 Thank you for your attention! BeihangU., Sept.2 nd 2016 Status report of vertex CEPC-SppCstudy group meeting

12 CEPC and Its Beam Timing Circular e + e - Higgs (Z) factory two detectors, 1M ZH events in 10yrs E cm 240GeV, luminosity ~ cm -2 s -1, ( cm -2 s -1 at the Z-pole) Single Ring - 54Km Baseline design in pre-cdr Bunch number 50 Colliding every 3.6μs, continuously Power pulsing not applicable Fully Partial Double Ring - 100Km Baseline design in CDR Bunch number 286 (half ring) Bunch spacing 0.537μs Reference: CEPC Accelerator CDR - Status, J. Gao, Workshop plenary talk Nov.10 h, 2017 CEPC detector CDR mini-review 12

13 R&D activities Initial sensor R&D targeting on Pixel single point resolution <3-5μm Power consumption at the current level <100mW/cm 2 Integration time μs CMOS pixel sensor (CPS)-funded by MOST and IHEP TowerJazz CIS 0.18 μm process SOI pixel sensor-funded by NSFC LAPIS 0.2 μm process BeihangU., Sept.2 nd 2016 Status report of vertex CEPC-SppCstudy group meeting

fabricated Single analog readout channel verified with oscilloscope ADC debugging in

14 1 st CPS Prototype Characterization Test system being developed Prototype analog readout Daughter-board ADC sampling by mother-board Two versions of daughter-board designed and fabricated Single analog readout channel verified with oscilloscope ADC debugging in progress WANG Ke, WANG Na et al. SHI Xin, KiuchiRyuta et al. Nov.10 h, 2017 CEPC detector CDR mini-review 14

cancellation technique; Version 2 has higher signal gain, but suffers more from Latch input voltage distortion.

15 2 nd CPS Submission: Rolling-shutter Mode Y. Zhou (IHEP) Two different pixel versions: Pixel size: 22μm 22μm 65% of ASTRAL chip Same amount of transistors; Offset cancellation technique; Version 2 has higher signal gain, but suffers more from Latch input voltage distortion. Chip features: mm pixels with 8 sub-matrix Processing speed: 11.2μs/frame with 100 ns/row Output data speed: 160 MHz Power: 3.7μA/pixel (14.4 mw/cm matrix) Nov.10 h, 2017 CEPC detector CDR mini-review 15

16 2 nd CPS Submission: AsynchronousMode P.Yang(CCNU) 8*8 pixels Pix_OR_logic ADDRX<0:7> ADDRY<0:7> ADDR<0:3> 20 address lines to the Periphery Matrix readout architecture: AERD (Address-Encoder and Reset-Decoder) many connection lines occupy larger area than the logic circuit itself OR gate chain: speed is limited with the number of the chain pixels Combine these two solutions: 64 pixels as a group using OR gate chain, groups using AERD structure to readout Nov.10 h, 2017 CEPC detector CDR mini-review 16

2 nd CPS Submission: AsynchronousMode Y. Zhang (IHEP) & P.Yang(CCNU) front-end I: Same structure as ALPIDE chip front-end II: CSA based front-end circuit -ENC: 8 e - - Power cons.

17 2 nd CPS Submission: AsynchronousMode Y. Zhang (IHEP) & P.Yang(CCNU) front-end I: Same structure as ALPIDE chip front-end II: CSA based front-end circuit -ENC: 8 e - - Power cons.: 61 na/pixel -Threshold: 140 e - -Peaking time < 1 us -Pulse duration < 3μs -Pixel size: μm 2 -ENC: 24 e - -Power cons.: 50 nw/pixel (8 mw/cm matrix) -Threshold: 170 e - -Peaking time < 500 Qin < 1.5 ke - -Pulse duration < 9.4 Qin < 1.5 ke - MIC4 chip mm pixels Integration time: < 5 μs/10 μs Power consumption: < 80 mw/cm 2 Chip periphery Band gap Voltage DAC Current DAC Matrix configuration LVDS Custom designed PADs Nov.10 h, 2017 CEPC detector CDR mini-review 17

18 Parameters for CEPC double ring BeihangU., Sept.2 nd 2016 Status report of vertex CEPC-SppCstudy group meeting

Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

PICSEL group Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments Serhiy Senyukov (IPHC-CNRS Strasbourg) on behalf of the PICSEL group 7th October 2013 IPRD13,