More Imaging Luc De Mey - CEO - CMOSIS SA

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1 More Imaging Luc De Mey - CEO - CMOSIS SA Annual Review / June 28, 2011

2 More Imaging CMOSIS: Vision & Mission CMOSIS s Business Concept On-Going R&D: More Imaging

3 CMOSIS s Vision Image capture is a key technology with ever growing number of applications. Specific imaging applications require specific and optimized Image Sensors.

4 CMOSIS s Mission Be a leading supplier of Image Sensors optimized for Industrial, Professional and Scientific Applications.

5 CMOSIS s Business Model Development, Qualification, Production and Supply of CMOS Image Sensors Standard of-the-shelf Sensors Custom(ised) Sensors

6 CMOSIS Markets

7 CMOSIS s Company Details Creation November 16, 2007 Capital Investors Management and Personnel Financial Investors: Capital-E, Vinnof, ING Belgium, ING Activator Fund Personnel 35

8 CMOSIS Company Details Facilities Antwerp

9 CMOSIS Company Details Facilities Antwerp Area: 1100 m 2 class 100 cleanroom 8 and 12 wafer tester

10 CMOSIS class 100 Clean Room

11 CMOSIS: 25 years of CMOS Image Sensor History

12 CMOSIS s Team Publications > 100 man-years of relevant experience

13 Patent/Patent Applications New CMOS pixel architectures (8-T) New on-chip ADC s BSI technology CMOS TDI Wafer scale imagers CMOS binning techniques Total: 12 patent families

CMOSIS s Patents - IP 12 CMOSIS patents filed in 2009-2010 1

14 CMOSIS s Patents - IP 12 CMOSIS patents filed in st patent granted, protecting our column AD converter structure

15 CMOSIS Standard Products Standard Products

16 CMOSIS Standard Products CMOSIS Machine Vision: CMV CMOSIS Low Noise: CLN

17 CMOSIS Standard Products CMV Applications Machine Vision - Factory Automation Broadcast Motion Analysis High End Surveillance Matrix Code Reading Intelligent Traffic Systems - ITS CMV2000 CMV4000 CMV12000

18 CMOSIS Standard Products CMV Type Pixel pitch µm Optical format FPS Bits Status 300 7,4 1/ Samples August ,5 2/ Production , Production ,5 28 mm APS-like Samples May 11

19 CMOSIS Standard Products CMV Common features Global pipelined shutter (8-T) Low FPN Digital serial LVDS interface Low dark noise High electronic shutter efficiency Column ADCs Integrated sequencer/controller 0.18 µm CMOS Image sensor technology

20 CMOSIS Standard Products CMOSIS New CMV12000

21 New CMOSIS CMV12000 What makes this sensor unique? Global pipelined 8T pixel shutter with CDS Global shutter required in machine vision market High sensitivity achieved through CDS and high conversion gain High shutter efficiency because of pixel architecture High speed column ramp ADC architecture High resolution with high frame rate 12 Mpixels Fully pipelined readout scheme Designed for > bit resolution I/O speed > 36 GbpsCurrently ongoing tests show even: > 400 fps (full 10 bit resolution I/O speed > 50 Gbps > 1000 fps (HD 10 bit resolution I/O speed > 25 Gbps

22 CMV12000 Sensor features Feature Resolution 4096 x 3072 Pixel size 5.5 µm x 5.5 µm Max. frame rate 180 fps (12 bit) 300 fps (10 bit) 350 fps (8 bit) Pixel control Row windowing (up to 32 separate ROIs), sub-sampling, 2x2 binning Image flipping X and Y mirroring Output 64 LVDS 600 Mbps Multiplexing To 32, 16, 8, 4 and 2 or 1 output(s) Sensor output 8 bit, 10 bit, 12 bit Package Ceramic µpga package (237 pins) Power consumption < 2.5 W (full frame, 300 fps, 10 bit) Technology 0.18 µm CIS 1P4M Noise < 10/13 e- Dynamic range > 62/60 db

23 CMV12000 Sample image

24 CMV Standard Products CMV2000/4000 à Industry standard à CMOSIS inside

25 CMOSIS CMV2000 Movie CMV2000, 300fps

26 CLN1000 Standard Product - Low Noise Type Pixel pitch µm Optical format FPS Bits Status Analog Samples Available

27 CLN1000 Standard Products CLN - Low Noise Common features 4T, dual transfer gate rolling shutter pixel Low dark noise: 3,3 e- High full well: e- High linear dynamic range: 89 db 0.18 µm CMOS Image sensor technology

CLN1000 - Low Noise Applications Surveillance Microscopy

28 CLN Low Noise Applications Surveillance Microscopy Diagnostics Astronomy X-ray Fluorescence Luminescence...

29 Standard Products Custom Design

30 CMOSIS Custom Design Device Qualification & Production Device Test & Characterization Prototyping Detailed Design & Layout Analysis and Architectural Study

31 CMOSIS Full Custom CIS Projects Active projects: 3 Space customers, 5 active projects: ESA, CNES, >12 Industrial customers

32 CMOSIS Customised Standard Products Custom packages Chip-Scale Packaging Custom cover glass: NIR filter, ARC, band-pass filters, Integrated Thermo Electric Cooler (TEC) Custom color filters Back Side Illumination...

33 CMOSIS Custom Package Integrated Thermo Electric Cooler

34 CMOSIS Custom Package Chip-Scale Packaging

35 CMOSIS R&D More Imaging

36 CMOSIS Technology differentiators Fast column AD converters Low noise global shutter pixels High frame rates Thin back-end process High dynamic range pixels Backside illumination technology

37 CMOSIS Core Technologies Global shutter pixels with low read noise, high shutter efficiency, and low FPN High speed on chip 10/12/14 bit column ADC s Backside Thinning and Illumination CMOS Time Delay and Integration (TDI) Radiation hardened CIS Large area (wafer scale) imagers with high yields (stitching!) CIS system-on-a-chip Very high frame rate imagers

38 CMOSIS Long Term R&D Plan Move to more advanced CMOS technologies: µm or below Smaller pixels More complex pixels Better electro-optical performance On chip image processing electronics > smart imagers Improved image sensor performances: Lower read noise: 1e- Increase full well: higher SNR High performance ADC: resolution, speed 1 GBit/s LVDS type interfaces

39 CMOSIS Long Term R&D Plan Smaller Technologies

40 Global shutter pixel smaller pixels Need for smaller optical formats & complex pixels smaller technologies 8 transistors, 2 source followers, 2 capacitors

41 The importance of a thin back-end even for a large pixel 6 µm pixel

42 CMOSIS moves to smaller technologies First tape-out s in 110/90 nm/300mm Moving to 90/65 nm/300mm

43 Excellent quantum efficiency

44 Excellent angular response > 95% at 20 angel

45 CMOSIS smaller architectures 300mm

46 CMOSIS smaller architectures 300mm

47 CMOSIS Long Term R&D Plan Back Side Illumination

lines Resolution Smaller pixels Angular Response No metal

48 Backside Illumination Address Many Challenges Dynamic Range Higher sensitivity Sensitivity Higher QE Frame Rate More readout lines Resolution Smaller pixels Angular Response No metal blocking Functionality More complex pixels Picture by Dr. Avi Strum, TowerJazz

49 High End Image Sensor Challenges Sensitivity Dynamic Range Frame Rate Resolution Functionality Angular Response Picture by Dr. Avi Strum, TowerJazz

50 Backside illumination: applications Scientific and industrial vision markets Performance : low noise, high QE Large pixels: MTF / cross-talk less problematic Monochrome Increased UV sensitivity: for inspection, analysis applications, EUV for science/space. Global shutter, without degradation of noise and PLS in BSI Performance: low dark current, good read noise Our developments focuses on this area

51 FSI & BSI CMV Mpixel 180 fps

52 FSI & BSI CMV Mpixel 340 fps

sensor Not (only) for visible light QE improvement Extension of

53 CMOSIS Back Side Illumination Development on CMOSIS CMV2000 / CMV4000te (EUV), Excellent PLS: 1/20,000 best in world for BSI global shutter sensor Not (only) for visible light QE improvement Extension of sensitivity to UV, EUV, electron detection Frontside CMV2000 with µlens Backside CMV2000

54 Backside illumination: quantum efficiency + improvement of yield (hot clusters)

55 Cause of low sensitivity in blue & UV Dead-zone below 450nm caused by pre-doped profile outdiffusing during CMOS processing.

56 Solutions to enhance blue response Get rid of the dead zone through either: 1. Backside implant + (laser) anneal with Excico Laser 2. Further etching of the silicon 3. Deposition of a layer with fixed negative charge (Sapphire Al 2 O 3 ) 4. A combination of 2 & 3

57 QE further etch improves QE again Some improvement in blue but not good enough yet 57

58 CMOSIS BSI Flow Start material: SOI wafer specific doping profile! Backside implant! Silicon etch! Wafer processing:! 0.18 µm CMOS! Laser anneal! Al2O deposition! Wafer test! AR coating (+CFA, )! Wafer bonding! (adhesive or ox-ox)! Thinning - stop on BOX! Pad opening! Packaging (assembly)! BOX etch! Final test! CMOSIS Proprietary Flow

59 CMOSIS Long Term R&D Plan > High Dynamic Range

More dynamic range with 2 transfer gates FD2 TX2 PPD_P TX1 FD1 Out image1 PPD_N P- epi Pixel with 2 floating diffusions First transfer to smallest FD High gain for dark signals Second transfer of

60 More dynamic range with 2 transfer gates FD2 TX2 PPD_P TX1 FD1 Out image1 PPD_N P- epi Pixel with 2 floating diffusions First transfer to smallest FD High gain for dark signals Second transfer of remaining photocharges to larger FD low gain for bright signals 2 outputs per pixel Simplification: select which FD to use based upon required gain. C fd1 << C fd2 FD2 FD1 image2 illumination TX1 PPD TX2

61 CLN db + 70 db = 90 db

62 CLN1000 CHARACTERIZATION TABLE

63 CLN1000 SENSOR FUNCTIONALITY LOW GAIN CHANNEL HIGH GAIN CHANNEL

64 High Dynamic Range & BSI BSI version:! Fully functional! SOI start material: 3um epi! Customized post-processing! Buried oxide (BOX) remove! Excellent QE in UV Future development! Digital out (on-chip column-level ADC)! Timing on-chip! Full product

65 QE 10 µm pixel, 3 µm thickness BSI UV sensitivity

66 CMOSIS Manufacturing Flow Fabs: - 110/90nm - 90/65nm - 180nm - 180nm - 180nm - 180nm

67 Thanks' for your attention! More Imaging Luc De Mey - CEO - CMOSIS SA Annual Review / June 28, 2011

Jan Bogaerts imec

Jan Bogaerts imec imec 2007 1 Radiometric Performance Enhancement of APS 3 rd Microelectronic Presentation Days, Estec, March 7-8, 2007 Outline Introduction Backside illuminated APS detector Approach CMOS APS (readout)